Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements filed 3/7/2023 and 9/16/2024 have been considered by the examiner.
Drawings
The drawings filed 3/7/2023 are approved by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-9, 11-15, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fu et al (United States Patent Application Publication No. 2021/0247501).
With respect to claim 15, Fu et al disclose: An apparatus [ taught by figure 4 ] comprising: one or more front-end devices each configured to couple to a respective of one or more arrays of detectors [ taught by the nodes (302-1 to 302-M), timing readout paths (220-1 to 220-M), and intensity readout paths (222-1 to 222-M) receiving data from an array of receiver channels (301-1 to 301-M) ], each of the one or more front-end devices comprising: a first plurality of input ports coupled to a first plurality of channels configured to receive a first plurality of input signals based on a pulse detected by a respective one of the one or more arrays of detectors [ taught by the plurality timing readout paths (220-1 to 220-M) coupled to a plurality of threshold detectors (330-1 to 330-M) and TDC elements (328-1 to 328-M) ]; a second plurality of input ports coupled to a second plurality of channels configured to receive a second plurality of input signals based on the detected pulse [ taught by the plurality of intensity readout paths (222-1 to 222-M) coupled to a plurality of hold circuits (340-1 to 340-M) and ADC elements (338-1 to 338-M) ]; a first interface circuit configured to extract first signal components in a first bandwidth of the first plurality of input signals and output a first intermediate signal [ taught by the operation of the plurality of threshold detectors (330-1 to 330-M) ]; a second interface circuit configured to extract second signal components in a second bandwidth of the second plurality of input signals and to output a plurality of second intermediate signals, the second bandwidth having a smaller and lower frequency band than the first bandwidth [ taught by the operation of the plurality of hold circuits 340-1 to 340-M); paragraph [0023] states, “…By including the hold circuit, a low-performance analog-to-digital converter can sample an output of the hold circuit. The low-performance analog-to-digital converter can operate at a slower sampling rate and have a smaller bandwidth relative to other high-performance analog-to-digital converters that can provide both time-sensitive information and non-time-sensitive information…” ]; a first channel circuit coupled to the first interface circuit and configured to process the first intermediate signal [ figure 4 shows the output of the nodes (302-1 to 302-M) dividing into two paths; therefore, the plurality of the two paths input to the plurality of timing readout paths (220-1 to 220-M) defines first channel circuits coupled to the interface and configured to process the first intermediate signals ]; and a second channel circuit coupled to the second interface circuit and configured to process the plurality of second intermediate signals [ figure 4 shows the output of the nodes (302-1 to 302-M) dividing into two paths; therefore, the plurality of the two paths input to the plurality of intensity readout paths (222-1 to 222-M) defines second channel circuits coupled to the interface and configured to process the second intermediate signals ]; and a central evaluation device coupled to the one or more front-end devices, the central evaluation device [ met by the combination of the processor (214), the TDC elements (328-1 to 328-M), ADC elements (338-1 to 338-M) producing and evaluating timing data (322-1 to 322-M) and intensity data (324-1 to 324-M) ] comprising: a first evaluation circuit comprising at least a time-to-digital converter (TDC) configured to evaluate timing information associated with the pulse using at least an output of the first channel circuit of a respective one of the one or more front-end devices [ figure 4 teaches the use of TDC elements (328-1 to 328-M); a second evaluation circuit comprising at least the second plurality of analog-to-digital circuits (ADCs) configured to evaluate energy information associated with the pulse using at least a plurality of outputs of the second channel circuit of the respective one of the one or more front-end devices [ figure 4 teaches the use of ADC elements (338-1 to 338-M) ]; and a digital logic circuit coupled to the first evaluation circuit and the second evaluation circuit and configured to extract the timing information and the energy information associated with the pulse [ figure 4 teaches a processor (214) operating on timing and intensity data (304-1 to 304-M and 306-1 to 306-M) ].
Claim 1 is anticipated by the subject matter of Fu et al, as applied to claim 15.
Claim 18 is anticipated by the subject matter of Fu et al, as applied to claim 15, Note, that the smaller bandwidth of the low performance ADC in the intensity readout path renders a bandwidth difference respect to the timing readout path; thus inherently creating a relative difference in frequency range.
With regard to claim 2, the device of Fu et al has M inputs wherein the paths created by division after the M number of nodes is input to M number of timing readout paths and intensity readout paths; thus, meeting the limitations set forth.
Claim 3 is met by the M number of receiver channels.
Claim 4 is met by the device of Fu et al producing M number of intensity signals.
Claim 7 is shown schematically by figure 4.
Paragraph [0038] teaches using a current-to-voltage converter including a transimpedance amplifier, thus teaching claims 8 and 19.
Paragraph [0061] teaches the use of a low pass filter, thus meeting claim 9.
With regard to claim 11, paragraph [0061] teaches that the low pass filter attenuates high frequency noise, thus acting as a band pass for lower frequencies.
With regard to claim 12, Fu et al disclose: a first evaluation circuit coupled to the first channel circuit, the first evaluation circuit comprising at least a time-to-digital converter operating at a first frequency range, the first frequency range being based on the first bandwidth [ taught by the timing readout path (220) ]; a second evaluation circuit coupled to the second channel circuit, the second evaluation circuit comprising a plurality of analog-to-digital converters operating at a second frequency range, the second frequency range being based on the second bandwidth [ taught by the intensity readout path (222) ]; and a digital logic circuit comprising a digital signal processor or field-programmable gate array circuit configured to extract timing information associated with the pulse based on outputs of the first evaluation circuit and extract energy information associated with the pulse based on outputs of the second evaluation circuit [ taught by the processor (214) operating on timing and intensity data (304-1 to 304-M and 306-1 to 306-M) ].
Claim 13 is met by the plurality of ADC elements (338) in the plurality of intensity readout paths (2220.
Claim 14 is met by the node connections (3040 and (306).
Claim 20 is met by the high pass filter (332) in paragraph [0051].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fu et al (United States Patent Application Publication No. 2021/0247501).
With regard to claim 10, paragraph [0060] of Fu et al states, “…The hold circuit 340 can be implemented as an integrate-and-hold circuit 342 or a peak-and-hold circuit 344. The integrate-and-hold circuit 342 measures an amount of charge within the pulse 320 (e.g., measures an amount of current or voltage over time) and generates a voltage, which represents the intensity of the pulse 320…”.
Therefore, it would have been a reasonable expectation of a skilled artisan to have used an integrating amplifier in the device of Fu et al because integrating amplifiers were known in electrical engineering to have performed the function of measuring current or voltage with respect to time.
Claim 17 would have been a reasonable expectation of skilled artisan because mounting separate chips on a substrate was a well known form of circuit construction.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Fu et al (United States Patent Application Publication No. 2021/0247501) in view of Thevenin et al (United States Patent Application Publication No. 2015/0110225).
Thevenin et al teaches a method of processing signals from multiple channels wherein paragraph [0030] states, “…More generally, the presence of a channel data item and a time data item for each elementary signal, associated with the capacity of the method of the invention to store the elementary signals, advantageously allows asynchronous processing of the detected events, whether these events be deterministic or non-deterministic…”.
Therefore, the subject matter of claim 16 would have been obvious as a reasonable expectation of a skilled artisan because it merely recites a known method of using a processor to process channel data.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Fu et al (United States Patent Application Publication No. 2021/0247501) in view of Dussan et al (United States Patent Application Publication No. 2018/0224533).
With respect to claim 5, Fu et al discloses: first interface circuit comprises a high-pass filter [ taught by the high pass filter (332) ] and a multiplexer, the high-pass filter being configured in series with the input ports to extract the first signal components from the M channels [ figure 3-2 shows the high pass filter (332) in series with node (302) and threshold detector (330) ], the multiplexer being configured to sum up the first signal components for the M channels.
Fu et al does not teach a multiplexer for summing signal components for the M channels.
Figure 6A of Dussan et al teaches that it was known before the effective filing date of the present application to have used a multiplexer (604) to multiplex data from an array of pixels to a signal processing circuit (606).
Therefore, it would have been obvious for a person of ordinary skill in the art to have had a reasonable expectation of success in using the multiplexing method of Dussan et al in the device of Fu et al, when seeking to process data derived from receiver channels deriving input from a pixel array.
Claim 6 would have been an obvious reasonable expectation of a skilled artisan because a capacitor was a well known component of a high pass filter.
Any inquiry concerning this communication should be directed to MARK HELLNER at telephone number (571)272-6981.
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
/MARK HELLNER/Primary Examiner, Art Unit 3645