DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/19/2026 has been entered.
Response to Amendment
The amendments filed 6/19/2026 have been accepted. Claims 1-13 are still pending. Claims 1, 4, and 7 are amended. Applicant’s amendments to the claims have overcome each and every 103 rejection previously set forth in the Final Office Action mailed 2/19/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over NVM ExpressTM Base Specification, NVM ExpressTM Revision 1.4, June 10, 2019, pp. 1-403, NVM Express Workgroup (hereafter referred to as NVM19) in view of Berner et al. (US PGPub 2019/0289230, hereafter referred to as Berner) in view of Bensity et al. (US PGPub 2017/0322897, hereafter referred to as Bensity) in view of Kajihara et al. (US PGPub 2021/0149599, hereafter referred to as Kajihara) in view of Koch et al. (US PGPub 2012/0151472, hereafter referred to as Koch).
Regarding claim 1, NVM19 teaches a memory system capable of performing a preset command queue-based interface operation with a host, the memory system comprising: a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host, or head doorbell information for N completion queues capable of storing an execution result of the command (Section 5.7 Doorbell Buffer Config command on p.106, provide two separate memory buffers that mirror the controller's doorbell registers defined in section 3; wherein the two buffers are known as “Shadow Doorbell” and “EventIdx”. The reference shows a memory mapped buffer of head/tail doorbell information [Submission/Completion Queue 0-y Tail/Head Doorbell on Figure 68 of p.42-43 and mirrored by the Shadow Doorbell buffer]), and 2N control registers, wherein each control register stores a position of an index for searching for the tail doorbell information or the head doorbell information on the buffer memory (Figure 68 on p.42-43, control registers shown with the start and end addresses (i.e. index) of the position where to find the particular doorbell information for one of the queues), wherein the index indicates an address in which the tail doorbell information or the head doorbell information is stored in the buffer memory (Sections 3.1.24 and 3.1.25 on p.60-61, Offset = (1000h + ((2y) * (4 << CAP.DSTRD))) shows how an address is calculated to find a particular submission queue tail doorbell information), and wherein N is a natural number (Sections 3.1.24 and 3.1.25 on p.60-61, the value of y is equivalent to the Queue Identifier). NVM19 does not teach wherein the tail doorbell information for a submission queue of the N submission queues comprises information that is stored in the buffer memory and that is sent by the host to the memory system to inform the memory system that a tail of the submission queue storing commands in the buffer memory has changed, and the head doorbell information for a completion queue of the N completion queues comprises information stored in the buffer memory and sent by the host to the memory system to inform the memory system that a head of the completion queue storing execution results in the buffer memory has changed and wherein the index lists an address of where the tail doorbell information or the head doorbell information is stored in the buffer memory and that is sent by the host to the memory system to inform the memory system and wherein N is determined according to the capability of the memory system.
Berner teaches wherein the index lists an address of where the information is stored in the buffer memory (Fig. 6C and Paragraphs [0072]-[0073], describe the index buffer which is used to store the addresses of where the corresponding timestamp data is stored in the memory. Paragraph [0043], shows the memory can be a buffer memory). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19 to utilize the index buffer of Berner so as to speed up the reading of the map (Berner, Paragraph [0075]). NVM19 and Berner do not explicitly teach wherein the tail doorbell information for a submission queue of the N submission queues comprises information sent by the host to the memory system to inform the memory system that a tail of the submission queue storing commands in the buffer memory has changed, and the head doorbell information for a completion queue of the N completion queues comprises information sent by the host to the memory system to inform the memory system that a head of the completion queue storing execution results in the buffer memory has changed and wherein N is determined according to the capability of the memory system.
Bensity teaches wherein the tail doorbell information for a submission queue of the N submission queues comprises information sent by the host to the memory system to inform the memory system that a tail of the submission queue storing commands in the buffer memory has changed, and the head doorbell information for a completion queue of the N completion queues comprises information sent by the host to the memory system to inform the memory system that a head of the completion queue storing execution results in the buffer memory has changed (Paragraphs [0052]-[0053], states that the head and tail pointer values can be updated with new values (head and tail information) when an operation is completed and chosen for processing). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19 and Berner to utilize the queue information as taught in Bensity so that submission queue processing may thus continue without a delay caused by waiting for space to store the completion queue entry in the corresponding queue (Bensity, Paragraph [0022]). NVM19, Berner, and Bensity do not explicitly teach information sent by the host to the memory system to inform the memory system and wherein N is determined according to the capability of the memory system.
Kajihara teaches information sent by the host to the memory system to inform the memory system (Abstract, states that a controller is receives update frequency information of a submission queue from a host). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19, Berner, and Bensity to use the communication processes of Kajihara so an efficiency of communication between a processor and a controller which controls a nonvolatile memory in accordance with a command issued by the processor, and an efficiency of control executed by the processor and the controller, are improved (Kajihara, Paragraph [0035]). NVM19, Berner, Bensity, and Kajihara do not explicitly teach wherein N is determined according to the capability of the memory system.
Koch teaches wherein N is determined according to the capability of the memory system (Paragraphs [0140]-[0141], states that the number of queues can be based on the capabilities of the system). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19, Berner, Bensity, and Kajihara to utilize the queues of Koch so to have a logical partition may be permitted to configure and access a desired number of virtual transmit and/or receive queues, and have an adjunct partition that interfaces the logical partition with the self-virtualizing IO resource handle the appropriate mappings between the hardware and virtual queues (Koch, Paragraph [0013]).
Regarding claim 2, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 1. NVM19 further teaches wherein an offset between the two adjacent control registers is determined according to a set stride value (Section 8.6 on p.325, the doorbell stride, specified in CAP.DSTRD, may be used to separate doorbells by a number of bytes in memory space. Figure 69 on p.43-45, Doorbell Stride (DSTRD): This register indicates the stride between doorbell registers). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 3, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 2. NVM19 further teaches wherein a size of an area used for storing the tail doorbell information or the head doorbell information in the buffer memory is set based on the number of the submission queues, the number of the completion queues, and the stride value (Figure 68 on p.42-43, total size of memory (buffer size) used for storing doorbell information is 3h + ((2y + 1) * (4 << CAP.DSTRD)); clearly a function of the number of queues “y” and the stride “CAP.DSTRD).
Regarding claim 4, NVM19 teaches an operating method of a memory system capable of performing a preset command queue-based interface operation with a host, the operating method comprising: receiving, from the host, an update request for tail doorbell information for one of N submission queues capable of storing a command fetched from the host, or head doorbell information for one of N completion queues capable of storing an execution result of the command (Section 4.1 Submission Queue & Completion Queue Definition on p. 63-64; Section 7.1 Introduction (to Controller Architecture) on p.274-275; and Section 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer on p.306, The submitter of entries to a queue uses the current Tail entry pointer to identify the next open queue slot. The submitter increments the Tail entry pointer after placing the new entry to the open queue slot. If the Tail entry pointer increment exceeds the queue size, the Tail entry shall roll to zero. The submitter may continue to place entries in free queue slots as long as the Full queue condition is not met. A Submission Queue entry is submitted to the controller when the host writes the associated Submission Queue Tail Doorbell with a new value that indicates that the Submission Queue Tail Pointer has moved to or past the slot in which that Submission Queue entry was placed), searching for, in a buffer memory for storing the tail doorbell information or the head doorbell information, an address in which the tail doorbell information or the head doorbell information is stored in the buffer memory (Sections 3.1.24 and 3.1.25 on p.60-61, Offset (1000h + ((2y) * (4 << CAP.DSTRD)))), and updating the tail doorbell information or the head doorbell information stored in the buffer memory (Section 3.1.24 on p.60, updates the Tail entry pointer for Submission Queue y), wherein a position of an index for searching for the tail doorbell information or the head doorbell information on the buffer memory is indicated by one of 2N control registers included in the memory system (Figure 162 show the addresses (or indexes) of the registers (i.e. buffer elements) where the tail/head doorbell information is located), wherein the index indicates the address in which the tail doorbell information or the head doorbell information is stored in the buffer memory (Figure 162, Start/End addresses), and wherein N is a natural number (Sections 3.1.24 and 3.1.25 on p.60-61, the value of y is equivalent to the Queue Identifier). NVM19 does not teach wherein the tail doorbell information for a submission queue of the N submission queues comprises information that is stored in the buffer memory and that is sent by the host to the memory system to inform the memory system that a tail of the submission queue storing commands in the buffer memory has changed, and the head doorbell information for a completion queue of the N completion queues comprises information stored in the buffer memory and sent by the host to the memory system to inform the memory system that a head of the completion queue storing execution results in the buffer memory has changed and wherein the index lists an address of where the tail doorbell information or the head doorbell information is stored in the buffer memory and that is sent by the host to the memory system to inform the memory system.
Berner teaches wherein the index lists an address of where the information is stored in the buffer memory (Fig. 6C and Paragraphs [0072]-[0073], describe the index buffer which is used to store the addresses of where the corresponding timestamp data is stored in the memory. Paragraph [0043], shows the memory can be a buffer memory). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19 to utilize the index buffer of Berner so as to speed up the reading of the map (Berner, Paragraph [0075]). NVM19 and Berner do not explicitly teach wherein the tail doorbell information for a submission queue of the N submission queues comprises information sent by the host to the memory system to inform the memory system that a tail of the submission queue storing commands in the buffer memory has changed, and the head doorbell information for a completion queue of the N completion queues comprises information sent by the host to the memory system to inform the memory system that a head of the completion queue storing execution results in the buffer memory has changed.
Bensity teaches wherein the tail doorbell information for a submission queue of the N submission queues comprises information that a tail of the submission queue storing commands in the buffer memory has changed, and the head doorbell information for a completion queue of the N completion queues comprises information that a head of the completion queue storing execution results in the buffer memory has changed (Paragraphs [0052]-[0053], states that the head and tail pointer values can be updated with new values (head and tail information) when an operation is completed and chosen for processing. Paragraph [0020], states the submission and completion queues are located in buffers (buffer memory)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19 and Berner to utilize the queue information as taught in Bensity so that submission queue processing may thus continue without a delay caused by waiting for space to store the completion queue entry in the corresponding queue (Bensity, Paragraph [0022]). NVM19, Berner, and Bensity do not explicitly teach information sent by the host to the memory system to inform the memory system.
Kajihara teaches information sent by the host to the memory system to inform the memory system (Abstract, states that a controller is receives update frequency information of a submission queue from a host). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19, Berner, and Bensity to use the communication processes of Kajihara so an efficiency of communication between a processor and a controller which controls a nonvolatile memory in accordance with a command issued by the processor, and an efficiency of control executed by the processor and the controller, are improved (Kajihara, Paragraph [0035]). NVM19, Berner, Bensity, and Kajihara do not explicitly teach wherein N is determined according to the capability of the memory system.
Koch teaches wherein N is determined according to the capability of the memory system (Paragraphs [0140]-[0141], states that the number of queues can be based on the capabilities of the system). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NVM19, Berner, Bensity, and Kajihara to utilize the queues of Koch so to have a logical partition may be permitted to configure and access a desired number of virtual transmit and/or receive queues, and have an adjunct partition that interfaces the logical partition with the self-virtualizing IO resource handle the appropriate mappings between the hardware and virtual queues (Koch, Paragraph [0013]).
Regarding claim 5, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 4. NVM19 further teaches wherein an offset between the two adjacent control registers is determined according to a set stride value (Section 8.6 on p.325, the doorbell stride, specified in CAP.DSTRD, may be used to separate doorbells by a number of bytes in memory space. Figure 69 on p.43-45, Doorbell Stride (DSTRD): This register indicates the stride between doorbell registers). The combination of and reason for combining are the same as those given in claim 4.
Regarding claim 6, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 5. NVM19 further teaches wherein a size of an area used for storing the tail doorbell information or the head doorbell information in the buffer memory is set based on the number of the submission queues, the number of the completion queues, and the stride value (Figure 68 on p.42-43, total size of memory (buffer size) used for storing doorbell information is 3h + ((2y + 1) * (4 << CAP.DSTRD)); clearly a function of the number of queues “y” and the stride “CAP.DSTRD). The combination of and reason for combining are the same as those given in claim 4.
Regarding claim 8, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 1. Berner further teaches wherein the address is a starting address of where the tail pointer information is stored in the buffer (Fig. 6C and Paragraphs [0072]-[0073], as stated in the rejection to claim 1, the indexes store the address for the timestamp). NVM19 further teaches tail and head doorbell information (Section 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer, as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 9, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 4. Berner further teaches wherein the address is a starting address of where the tail pointer information is stored in the buffer (Fig. 6C and Paragraphs [0072]-[0073], as stated in the rejection to claim 1 the indexes store the address for the timestamp). NVM19 further teaches tail and head doorbell information (Section 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer, as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 4.
Regarding claim 11, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 1. Berner further teaches wherein a location of where the is stored in the buffer memory is dynamically changed to manage resources for storing the information (Fig. 6C and Paragraphs [0072]-[0073], the indexes and memory allocated to the timestamps are constantly updated whenever a new timestamp is created. It should be noted the claims do not specified how the location is changed and what constitutes resources to be managed). NVM19 further teaches tail and head doorbell information (Section 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer, as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 12, NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claim 4. Berner further teaches wherein a location of where the is stored in the buffer memory is dynamically changed to manage resources for storing the information (Fig. 6C and Paragraphs [0072]-[0073], the indexes and memory allocated to the timestamps are constantly updated whenever a new timestamp is created. It should be noted the claims do not specified how the location is changed and what constitutes resources to be managed). NVM19 further teaches tail and head doorbell information (Section 7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer, as stated in the rejection to claim 1). The combination of and reason for combining are the same as those given in claim 4.
Regarding claims 7, 10, and 13, claims 7, 10, and 13 are the system claims associated with claims 1, 8, and 11. Since NVM19, Berner, Bensity, Kajihara, and Koch teach all the limitations to claims 1, 8, and 11 and Berner further teaches the information that the position in the buffer memory has changed (Paragraphs [0072]-[0073], this is part of the information that is added to the index), they also teach all the limitations to claim 7, 10, and 13; therefore the rejections to claims 1, 8, and 11 also apply to claims 7, 10, and 13.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the applicant amended the claims with the limitation “wherein N is a natural number and determined according to the capability of the memory system” to overcome the prior rejections set forth in the Final Rejection mailed 2/19/2026. To address this, new reference Koch has been incorporated into the rejections to help teach the amended limitations to the independent claims.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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