18/180,204
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Takebayashi (U.S. Patent Application Publication No. 2017/0280509).
Regarding claim 1.
Takebayashi discloses Figs. 1 and 2:
A wafer placement table comprising:
a ceramic base (26)having a wafer placement surface(W);
resistance heating elements(34) buried in the ceramic base(34 in 26);
jumper layers(36) having a planar shape and provided in a different layer from the resistance heating elements(36 having planar shape and different layer from 34);
an inner via(35) connecting the jumper layer and an end of the resistance heating element; ([0029] disclosing that jumper provides power to electrodes 34 through vias 35)and
a feed via(41) connected to the jumper layer, wherein
each of the resistance heating elements is provided for each of zones of a surface parallel to the wafer placement surface(resistance heating elements shown in fig. 2, as 34 being provided for each radial zone Z1.),
each of the jumper layers is provided for each of the resistance heating elements(36 is provided for each 34 as shown in fig. 2), and
Takebayashi does not discloses:
a center-to-center distance between the inner via and the feed via in each of the jumper layers is greater than or equal to 50 mm.
However, the recited feature is a mere change in size of the working parts. Here the claimed size would not perform differently from the device of Takebayashi, as such, the features would have been obvious to one having ordinary skill In the art prior to the effective filing date of this application. See MPEP 2144.04(IV)(A).
Regarding claim 2.
Takebayashi discloses
The wafer placement table according to claim 1, further comprising a high-resistance section in each of the jumper layers at a position between the inner via and the feed via to block a shortest route between the inner via and the feed via. ([0038] and [0050], jumper layer 36 having conductor 36 and therebetween insulator. The insulator being the high resistance that blocks shorts between areas of conductor 36.[0029], second electrode area has conductor and surrounding conductor is higher resistance)
Regarding claim 3.
Takebayashi discloses
The wafer placement table according to claim 2, wherein the high-resistance section is a slit in each of the jumper layers. ([0038] and [0050], jumper layer 36 having conductor 36 and therebetween insulator. The insulator being the high resistance that blocks shorts.[0029], second electrode area has conductor and surrounding conductor is higher resistance. 36 cut in slits as shown in fig. 2)
Further, the recited features is a mere change in shape of the working parts of Takebayashi. Here there is no persuasive evidence that the particular configuration of the claimed shape is significant especially in view of the large space between vias claimed. It would have been obvious to one having ordinary skill in the prior to the effective filing date of this application for the obvious benefit of providing a stage to heat a wafer having a desired shape, by providing the vias and jumper wires in the recited locations and configurations, and to provide insulation between vias. As such, the features of claim 3 would have been obvious to one having ordinary skill in the art. See MPEP 2144.04(A)(B)
Regarding claim 4.
Takebayashi discloses all of the features of claim 2
Takebayashi does not disclose:
The wafer placement table according to claim 2, wherein the high-resistance section intersects two tangent lines that are tangent to each of an outline of the inner via and an outline of the feed via
However, the recited features is a mere change in shape of the working parts of Takebayashi. Here there is no persuasive evidence that the particular configuration of the claimed shape is significant. IT would have been obvious to one having ordinary skill in the prior to the effective filing date of this application for the obvious benefit of providing a stage to heat a wafer having a desired shape. As such, the features of claim 4 would have been obvious to one having ordinary skill in the art. See MPEP 2144.04(A)(B)
Regarding claim 5.
Takebayashi discloses
. ([0038] and [0050], jumper layer 36 having conductor 36 and therebetween insulator. The insulator being the high resistance that blocks shorts.[0029], second electrode area has conductor and surrounding conductor is higher resistance.)
Takebayashi does not disclose:
The wafer placement table according to claim 2, wherein the high-resistance section is an arc-shaped section centered at one of the inner via and the feed via.
However, the recited features is a mere change in shape of the working parts of Takebayashi. Here there is no persuasive evidence that the particular configuration of the claimed shape is significant. It would have been obvious to one having ordinary skill in the prior to the effective filing date of this application for the obvious benefit of providing a state to heat a wafer having a desired shape, by providing the vias and jumper wires in the recited locations and configurations. As such, the features of claim 4 would have been obvious to one having ordinary skill in the art. See MPEP 2144.04(A)(B)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT G BACHNER whose telephone number is (571)270-3888. The examiner can normally be reached on Monday-Friday, 10-6 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached at (571)273-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT G BACHNER/Primary Examiner, Art Unit 2898