DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/11/2026 has been entered.
Response to Arguments
Applicant’s arguments, see Applicant’s Response, filed 5/11/2026, with respect to the rejections of the claims under Pivonka have been fully considered and are persuasive. Therefore, the rejection using the Pivonka reference have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Muller et al. US 2019/0282817/Pansell et al. US 2014/0044290 or Muller et al. US 2019/0282817/ Andersen US 2013/0108046.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “comprises NxM bits of parallel simultaneous data”. This language is not understood. It is not understood how the bits are both parallel and simultaneous. For the purpose of examination it will be assumed that a SAR ADC in connection with a cypher module performs this function.
Claims 9-13 are also rejected in that they depend rom claim 8 which is rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Muller et al. US 2019/0282817 previously cited and further in view of Pansell et al. US 2014/0044290.
Regarding claim 1: Muller discloses a neural interface device (the abstract discloses an apparatus, system and method for neuromodulation via an electrode array) comprising;
an electrode array 150 (figures 1-6) implanted between a brain and scalp (paragraphs 0097 and 0098) for recording neural signals (recording circuitry 400 in figure 6 and 400C in figure 27 records neural signals)
an integrated circuit 100 (figures 1-6, element 100 is an NMIC neural modulation integrated circuit) in electrical communication with the electrode array 150 (figures 1-6, paragraph 0097; “The electrode array 150 is coupled, typically using wires or bus 205 through one or more holes 108, to the NMIC 100”);
the integrated circuit 100 (figures 1-6) comprising and ADC producing digitized electrical signal output (paragraphs 0018, 00189, and 0194 “During recording on a selected electrode 150, any voltage on the selected electrode 150, as an analog voltage level, is compared to the voltage level on the reference electrode 150.sub.N-1 (e.g., as a voltage level indicative of baseline neural activity), by the delta-sigma ADC 1300 or SAR ADC 1300A, to provide a differential voltage level value which is also converted to a digital value”) and;
a transmitter 930 (figure 22) for transmitting to an external device 180 (figures 3-5) of a brain-computer interface (figures 1-6 show a brain computer interface as is known in the art).
Muller therefore discloses the claimed invention, however Muller does not disclose an encryption module which receives digitized sensed signals from an ADC, encrypts the digitized signal using a symmetric cryptographic algorithm and provides the encrypted output to a transmitter to be transmitted to an external device.
Pansell however teaches of a device 201(figure 2) which receives an audio signal 220 (figure 2), the analog audio signal is received at an analog-to-digital converter 223 (figure 2). Once the analog signal is digitized by the ADC the signal is then encrypted at 223 (figure 2) and transmitted via transmitter 224 (figure 2). Pansell further teaches that the encryption used is symmetric encryption (paragraphs 0047-0048). It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller to include receiving a digitized signal from an ADC at a symmetric encryption module, as taught by Pansell, in order to securely send data. It is noted that both Muller and Pansell disclose an ADC.
Regarding claim 2: Muller discloses that the ADC is an SAR ADC (paragraph 0115, figure 27 element numbers 1300/1300A).
Regarding claim 6: Muller discloses a wireless transmitter 930 (figure 22) coupled to the integrated circuit (coupled via DATA I/O in figure 22) and an external processor 180 (figure 4, paragraph 0200; “The recorded data is transmitted to a processor, such as a processor within the system controller and power supply 180”).
Regarding claim 7: Muller disclose control logic for operating the integrated circuit (paragraphs 0138-0141); memory for storing recordings from the electrode array 305 (figure 7, and paragraphs 0104 and 0213); and power management 920 (figure 22 and paragraphs 0173 and 0211) for providing power to the IC.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Muller et al. US 2019/0282817 previously cited in view of Pansell et al. US 2014/0044290 and further in view of Andersen US 2013/0108046 previously cited herein Andersen ’046.
Regarding claim 3: Muller/Pansell discloses the claimed invention however Muller/Pansell does not specifically disclose a bit stream cipher. Andersen ‘046 however teaches of a “stream cipher” which could include a stream cipher based on scrambling bits (paragraph 0059, which is considered to be a bit-stream cipher). It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller/Pansell to include a bit stream cipher, as taught by Andersen ‘046, in order to utilize a low cost cipher (Andersen ‘046, paragraph 0059).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Muller et al. US 2019/0282817 previously cited in view of Pansell et al. US 2014/0044290 and further in view of in view of Andersen US 2014/0185805 previously cited herein Anderson ‘805 .
Regarding claim 5: Muller/Pansell discloses the claimed invention, however Muller/Pansell does not disclose a cipher of the encryption module is 128 or 156 bits. Andersen teaches of secure cypher key exchange (title and abstract) and that a key can be either 128 or 156 bits (paragraph 0039). It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller/Pansell to include cipher encryption keys of 128 or 156 bits in order to follow ASE standards (Andersen ‘805; paragraph 0028).
Claims 8-9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Muller et al. US 2019/0282817 previously cited in view of Andersen US 2013/0108046 previously cited herein Andersen ‘046 .
Regarding claim 8: Muller discloses a plurality of electrode arrays 150 (figures 1-6) which include N electrode arrays 1501/1502 etc (figure 1) which are implanted between the scalp and brain (figure 3, paragraph 0097; “in top of or into (animal) cortical tissue 102”); and an integrated circuit 100 (neuromodulation integrated circuit (NMIC), paragraph 0094, figure 3) operably attached to the electrode arrays 150 (figure 3); the integrated circuit including a 5-bit (paragraph 0056; M is an integer in this case 5) successive approximation register analog-to-digital converter (“SAR ADC”, paragraphs 0018, 0056, 0115). However, Muller does not disclose a cypher module to generate encrypted signals. Andersen ‘046 however teaches of a stream cipher module 214 (paragraphs 0058-0059, figure 4A) which receives digitally converted data from converting module 216 (figure 4A), the converting module can include an ADC (paragraph 0080). Therefore in Andersen, sensor signals are received at the converting module, which converts the analog signal to a digital signal to then the converted digital signal is received at the cryptographic module. The cryptographic module includes stream cipher capability. It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller to include a stream cipher module which receives digitized sensor data from a converting module which also includes an ADC, as taught by Andersen ‘046, in order to generate private cryptographic data (abstract).
Regarding claim 9: Muller/Andersen‘046 discloses the claimed invention, Andersen‘046 further discloses stream ciphers which are based on scrambling a bit stream (paragraph 0059). This is considered to be a bit stream cipher. It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller/Andersen’046 to further include a bit stream cipher, as taught by Andersen’046 in order to utilize a low cost solution (paragraph 0059 Andersen’046)
Regarding claim 11: Muller/Andersen‘046 discloses the claimed invention, Andersen‘046 further discloses that the key is an 8 bit key (paragraph 0049). It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Pivonka/Andersen‘046 to include an encryption keys of 8 bits in order to follow ASE standards (Andersen‘046; paragraph 0028).
Regarding claim 12: Muller further discloses a wireless transmitter 175A (figure 4, paragraph 0095) which is coupled to the NMIC circuit 100 (figure 4) and an external processor 180 (figure 4)
Regarding claim 13: Muller further discloses control logic (paragraph 0138-0139) which operates the controller, memory for recording (paragraphs 0104 and 0117-0118) and a power management unit 180 (figures 1-2) which powers the circuit (paragraph 0096).
Claims 10 are rejected under 35 U.S.C. 103 as being unpatentable over Muller et al. US 2019/0282817 previously cited in view of Andersen US 2013/0108046 herein Andersen ‘046 and further in view of Matsumoto et al. US 2013/0265180.
Regarding claim 10: Muller/Andersen’046 discloses the claimed invention, however Muller/Andersen’046 does not specifically disclose that the SAR DAC includes a sample and hold circuit electrically coupled to a comparator and the DAC electrically coupled to the comparator which uses a binary search algorithm. Matsumoto however teaches of an integrated circuit which includes a successive approximation register A/D converter 100 (figure 1) which includes a sample/hold circuit 11 (figure 1) connected to a comparator 12 (figure 1) as well as a local DAC 13 (figure 1, paragraph 0041). Matsumoto further teaches the use of a binary search algorithm (paragraph 0041) It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller/Andersen’046 to include a SAR DAC includes a sample and hold circuit electrically coupled to a comparator and the DAC electrically coupled to the comparator which uses a binary search algorithm. It therefore would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Muller/Andersen’046 to include a SAR DAC which has a sample and hold circuit electrically coupled to a comparator with the DAC electrically coupled to the comparator which uses a binary search algorithm in order to compare an analog input signal with a plurality of comparison reference voltages and convert the analog input signal into a digital signal on the basis of the comparison result, as taught by Matsumoto in paragraph 0002.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin, C.-H., Wu, J.-X., Chen, P.-Y., Li, C.-M., Pai, N.-S., & Kuo, C.-L. (2021). Symmetric cryptography with a chaotic map and a multilayer machine learning network for Physiological Signal Infosecurity: Case Study in Electrocardiogram. IEEE Access, 9, 26451–26467. https://doi.org/10.1109/access.2021.3057586. Lin et al. teaches of an ADC which collects ECG data and then uses an encryption process (figure 1). In this paper a biopotential signals are digitized by and ADC and stored in memory or encrypted using symmetric cryptology.
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PAULA J. STICE
Primary Examiner
Art Unit 3796
/PAULA J STICE/Primary Examiner, Art Unit 3796
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