DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The present application is being examined under the claims filed 5/28/2026. Claims 1, 4-6, 10-11, and 16 have been amended. Claims 19-30 are canceled.
Response to Arguments
Applicant’s arguments filed on 5/28/2026 with respect to claim(s) 1, 11, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Paul et al. (US 2015/0355692 A1) [previously cited] in view of Wang et al. “APC: A Novel Memory Metric and Measurement Methodology for Modern Memory Systems” [previously cited], Li et al. (US 20210232429 A1), and Partiwala et al. (US 20210326232 A1).
Regarding Claim 1, Paul discloses a processor (Paul Figure 1, accelerated processing unit 105) comprising:
a central processing unit (CPU) (Paul Figure 1, CPU cores 110) configured to drive a dynamic voltage and frequency scaling (DVFS) module (Paul Fig. 1 and par. 16, performance controller 125 implements dynamic voltage and frequency scaling (DVFS));
a memory hierarchy configured to store data for an operation of the CPU (Paul Figure 1, system memory 130; also see par. 14, memory 130 is a memory hierarchy that is used by the CPU); and
a memory hierarchy configured to store data for an operation of the CPU (Paul par. 14, a memory hierarchy is used by the CPU and GPU), the memory hierarchy including […] a memory device (Paul FIG. 1 and par. 14, system contains CPU and GPU cores and system memory 130 [i.e., memory device]);
an activity monitoring unit (AMU) (Paul Figure 1, CPU activity counter 140, a GPU activity counter 145, and memory activity counter 150, which may all be integrated together into performance controller 125 [see par. 25]) configured to generate microarchitecture information by monitoring performance of the CPU (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle) or monitoring traffic of a system bus connected to the memory hierarchy (Paul par. 39, memory activity counter 150 monitors activity over memory bus), [a DVFS module] configured to determine [when] a memory stall occurs (Paul Figure 4 step 488 and par. 43, gradients in memory access rates determine the appropriate DVFS state for CPU [see par. 16 and 17, higher states have greater voltage and frequency]), and to adjust a frequency of the CPU […] in response to [the memory] being accessed (Paul Figure 4 step 488 and par. 43, gradients in memory access rates determine the appropriate DVFS state for CPU, DVFS rate can be increased after the analysis of memory access [i.e. select DVFS state]; also see Paul par. 46, CPU in lower DVFS states may provide power savings, but may result in performance degradation, and par. 39, memory accesses may indicate a bottleneck in performance, lowering the CPU DVFS state in response [i.e., the frequency of the CPU is increased based on memory access information]).
an execution order of adjustment of the frequency of the CPU […] and the frequency of the [GPU] is based on the microarchitecture information (Paul Figure 2 illustrate an order of increasing the frequency of the GPU or the CPU, where [0034] teaches the performance controller determines if the GPU.sub.FSEN is greater than a “high” GPU frequency sensitivity threshold, HFSTH.sub.GPU. If the GPU.sub.FSEN is high, the performance controller determines if the CPU.sub.FSEN is lower than a “low” CPU frequency sensitivity threshold, LFSTH.sub.CPU in method block 215. If the CPU.sub.FSEN is low, the performance controller 125 shifts power credits from the CPU to the GPU in method block 220 to allow the frequency of the GPU to be increased. If the CPU.sub.FSEN is not low in method block 215, the performance controller 125 determines if the CPU.sub.FSEN greater than a “high” CPU frequency sensitivity threshold, HFSTH.sub.CPU, in method block 225. If the CPU.sub.FSEN is high, the performance controller 125 distributes power credits proportionally to the CPU and GPU according in method block 230 to improve performance. [0035] teaches If the GPU.sub.FSEN is low in method block 240, the performance controller 125 determines if the CPU.sub.FSEN is greater than HFSTH.sub.CPU in method block 245. If the CPU.sub.FSEN is high, the performance controller 125 shifts power credits from the GPU to the CPU in method block 250. If the CPU.sub.FSEN is not high in method block 245, the performance controller 125 determines if the CPU.sub.FSEN is less than LFSTH.sub.CPU in method block 255. If the CPU.sub.FSEN is low, the performance controller 125 shifts power credits away from the CPU and the GPU to save power.)
Paul does not explicitly disclose:
the memory hierarchy including a cache memory and a memory device.
wherein the DVFS module is configured to determine a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information, and to adjust […] a frequency of the cache memory and a frequency of the memory device, and an execution order of adjustment of […] the frequency of the cache memory and the frequency of the memory device.
In the analogous art of analyzing accesses in a memory hierarchy to optimize performance and power use of a device, Wang teaches:
determining a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information (Wang pg. 1627 Sec. 2.1, evaluate memory system performance by monitoring accesses per cycle at each layer of the memory hierarchy; and pg. 1628 section 2.2, MSHR is a table that records cache miss information [cache misses result in memory stalls], such as access type, access address, and return register [access address would reveal layer]; and pg. 1628 section 2.2, MSHR table is full, the cache cannot queue more cache accesses and the CPU's memory accesses or next-level memory accesses are blocked [i.e., the memory layer with the misses is tracked]).
[Wang further teaches that memory performance is closely linked to overall system performance (Wang pg. 1632 Sec. 4.1.1, Load and store instructions occupy 34.0% of all instructions; memory accesses are the most time-consuming portion of the whole operations) and cache misses at different layers of the memory hierarchy results in different CPU performance penalties (Wang pg. 1632 Sec. 4.1.1, two-cycle hit latency to L1 cache, 12-cycle of hit latency for L2 cache, 200-cycle of main memory access latency), i.e., rationale for tracking the layer in which the cache miss occurs].
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Paul and Wang before them, to combine Paul's analysis of memory access rate for frequency adjustments and methodology to save power by lowering CPU frequency in response to a memory bottleneck with Wang’s use of determining the layer of the hierarchy where the stall occurs and knowing a stall’s effect on performance at each layer, the motivation being to further improve power saving in the system by addressing the individual performance penalties of each layer (Wang pg. 1632 Sec. 4.1.1, two-cycle hit latency to L1 cache, 12-cycle of hit latency for L2 cache, 200-cycle of main memory access latency).
Paul in view of Wang does not explicitly disclose:
the memory hierarchy including a cache memory and a memory device; to adjust […] a frequency of the cache memory and a frequency of the memory device, and an execution order of adjustment of […] the frequency of the cache memory and the frequency of the memory device is based on the microarchitecture information.
In the analogous art of adjusting hardware operating parameters to optimize performance and power use of a device, Li teaches:
the memory hierarchy including a cache memory and a memory device; and to adjust a frequency of the CPU, a frequency of the cache memory and a frequency of the memory device (Li [0067] teaches and optimization policy adjusting the hardware resource as required, which includes boosting an operating frequency of a CPU, adjusting an operating frequency of an L3 cache, adjusting an operating frequency of a GPU, and adjusting both an operating frequency of the CPU and an operating frequency of the DDR to enable the adjusted operating frequency of the CPU and the adjusted operating frequency of the DDR to still match each other; see also [0128]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Paul, Wang, and Li before them, to combine Paul and Wang’s methodology for reducing power use in a system by identifying memory bottlenecks with Li's adjusting of operating frequencies of the CPU, L3 cache, and DDR, the motivation being to further accelerate startup tasks and improve CPU processing performance (Li [0067] & [0069]).
Paul in view of Wang and Li does not explicitly disclose:
an execution order of adjustment of […] the frequency of the cache memory and the frequency of the memory device is based on the microarchitecture information.
In the analogous art of adjusting hardware operating parameters to optimize performance and power use of a device, Partiwala in combination with Li teaches:
an execution order of adjustment of the frequency of the CPU, the frequency of the cache memory and the frequency of the memory device is based on the microarchitecture information (Partiwala Fig. 4A and [0035-0038] illustrate an order of incrementing CPU frequency (404) followed by incrementing cache frequency (414), where Li [0067] & [0128] teach adjusting of operating frequencies of the CPU, L3 cache, and DDR).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Paul, Wang, Li, and Partiwala before them, to combine Paul, Wang, and Li’s methodology for reducing power use in a system by identifying memory bottlenecks with Partiwala's incrementing CPU frequency and cache frequency, the motivation being to determine the basic stability of the system and to avoid causing a system failure (Partiwala [0033], [0038], and [0042]).
Regarding Claim 2, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 1. Paul further discloses wherein the AMU includes:
a performance monitoring unit (Paul Figure 1, CPU activity counter 140; Paul par. 25 stating CPU activity counter can be implemented as a component of performance controller 125) configured to monitor the performance of the CPU (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle); or
a bus traffic monitoring circuit (Paul Figure 1, memory activity counter 150; Paul par. 25 stating memory activity counter can be implemented as a component of performance controller 125) configured to monitor the traffic of the system bus (Paul par. 39, memory activity counter 150 monitors activity over memory bus).
Regarding Claim 3, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 2, wherein the performance monitoring unit is configured to:
count a number of instructions processed by the CPU per cycle (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle); or
count a number of memory stalls of the CPU per cycle (Wang pg. 1638 Sec. 6, miss rate [which results in a memory stall/miss penalty] is used in calculation of MLP(t), which finds main memory accesses [resulting in a stall] per cycle)
Regarding Claim 4, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 3, wherein the DVFS module is configured to limit the frequency of the CPU (Paul par. 25, DVFS state of CPU is changed; DVFS state includes change in frequency [see Paul par. 16 and 17) when the number of instructions is less than or equal to a first reference value (Paul par. 39, number of memory activities is compared to a memory threshold, if bottleneck is present CPU is set to a LOW DVFS state [i.e. frequency is limited]) or the number of memory stalls is less than or equal to a second reference value (Wang pg. 1633 Col 2 First par., APC and AMAT consider lower-level cache performance in memory performance calculation; and Paul Figure 4 step 488 and par. 43, gradients in memory access rates determine the appropriate DVFS state for CPU, DVFS rate can be increased after the analysis of memory access).
Regarding Claim 5, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 4, wherein a magnitude of the frequency of the CPU is based on the number of instructions and the number of memory stalls (Paul Figure 4 step 488 and par. 43, gradients in memory access rates determine the appropriate DVFS state for CPU [i.e., frequency of the CPU], DVFS rate can be increased after the analysis of memory access [i.e., analyzing number of memory access instructions and memory stalls]; and Wang pg. 1638 Sec. 6, miss rate is a common parameter for analyzing memory accesses).
Regarding Claim 6, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 3, wherein the DVFS module is configured to determine the layer within the memory hierarchy in which the memory stall occurs using the number of memory stalls (Wang pg. 1628 section 2.2, MSHR table is full, the cache cannot queue more cache accesses and the CPU's memory accesses or next-level memory accesses are blocked [implying misses are tracked per layer; stalls are resulting from multiple uncleared misses).
Regarding Claim 7, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 1, wherein the DVFS module is configured to determine the frequency so as to increase the frequency (Paul Figure 4 step 488 and par. 43, gradients in memory access rates determine the appropriate DVFS state for CPU, DVFS rate can be increased based on the analysis) or reduce power consumption based on to a number of memory stalls in the layer within the memory hierarchy in which the memory stall occurs (Paul par. 39, a memory bottleneck is located and CPU frequency is subsequently reduced [which saves power, see Paul par. 46, CPU in lower DVFS states may provide power savings, but may result in performance degradation]; and Wang pg. 1632 Sec. 4.1.1, two-cycle hit latency to L1 cache, 12-cycle of hit latency for L2 cache, 200-cycle of main memory access latency [misses at each level result in a delay, different layers result in different penalties, see combination in Claim 1]).
Regarding Claim 8, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 1, wherein the memory hierarchy includes:
the cache memory configured to temporarily store the data for the operation of the CPU (Wang pg. 1626 Introduction, L1 and L2 cache are used for CPU operation); and
a memory interface circuit configured to transmit the data from the cache memory to the memory device through the system bus (Paul FIG. 1 and par. 14, CPU cores 110 and GPU cores 115 on a common semiconductor die, allowing them to share on-die resources such as the memory hierarchy and interconnect; or Wang pg. 1629 Col 1 Last par, discloses buses at CPU/Cache interface bus, Prefetcher/MSHR bus, or inside the Cache, or if outstanding cache miss/misses are registered in the MSHR to track all memory accesses at all layers of the hierarchy).
Regarding Claim 9, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 8, wherein the DVFS module is configured to determine to increase the frequency of the cache memory, when the microarchitecture information indicates that a number of memory stalls per cycle is greater than or equal to a reference value (Liu Figure 4 steps 404-410, LMPR increases when memory stalls increase [see Col 5 Lines 35-55 for equations], therefore frequency adjustment 410 occurs if LMPR is greater or equal to T1 ["no" branch of tree at 408]).
Regarding Claim 10, Paul in view of Wang, Li, and Partiwala discloses the processor of claim 9, wherein the DVFS module is configured to determine to increase a frequency of the memory interface circuit, in response to the number of the memory stalls per cycle being greater than or equal to the reference value even with the frequency of the cache memory being increased (Liu Figure 4 steps 404-410, LMPR increases when memory stalls increase [see Col 5 Lines 35-55 for equations], therefore frequency adjustment 410 occurs if LMPR is greater or equal to T1 ["no" branch of tree at 408]; this branch can be reevaluated after frequency is increased if it must be increased additional times).
Regarding Claim 11, Paul teaches a method of operating a processor (Paul Figure 1, accelerated processing unit 105), the method comprising:
monitoring microarchitecture information (Instant application par. 47 states microarchitecture information may include information related to usages of the cache memory 120 and the memory interface circuit 130 or traffic of a bus 101; Paul par. 39, memory activity counter 150 monitors activity over memory bus and par. 25, memory activity counter may be a part of performance controller 125) by a performance monitoring unit (Paul Figure 1, performance controller 125 [see par. 25, activity counter 140, a GPU activity counter 145, and memory activity counter 150, which may all be integrated together in performance controller 125]) or a bus traffic monitoring unit (Paul Figure 1, memory activity counter 150);
controlling a frequency of a CPU (Paul Figure 4, showing method to change CPU DVFS state; Paul par. 16 and 17, DVFS state affects frequency) […], using the microarchitecture information (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle);
monitoring performance of the CPU, by the performance monitoring unit (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle); and
monitoring traffic of a system bus between the cache memory and the memory device, by the bus traffic monitoring unit (Paul par. 39, memory activity counter 150 monitors activity over memory bus).
The remaining clauses in claim 11 are similar in scope to claim 1 as addressed above, and thus rejected under the same rationale.
Regarding Claim 12, Paul in view of Wang, Li, and Partiwala discloses the method of claim 11, wherein the monitoring the microarchitecture information includes:
counting a first count value of executing instructions per cycle by the CPU (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle); and
counting a second count value for memory stalls of the CPU per cycle (Wang pg. 1638 Sec. 6, miss rate [which results in a memory stall/miss penalty] is used in calculation of MLP(t), which finds main memory accesses [resulting in a stall] per CPU cycle).
Regarding Claim 13, Paul in view of Wang, Li, and Partiwala discloses the method of claim 12, further comprising:
increasing the frequency of the cache memory based on the first count value and the second count value (Liu Figure 4 steps 404-410, LMPR is affected by instructions per cycle and memory stalls [see Col 5 Lines 35-55 for equations]; frequency adjustment at 410 based on LMPR value).
Regarding Claim 14, Paul in view of Wang, Li, and Partiwala discloses the method of claim 13, further comprising:
after increasing the frequency of the cache memory, increasing the frequency of the memory device, based on the first count value and the second count value (Liu Figure 4 steps 404-410, LMPR is affected by instructions per cycle and memory stalls [see Col 5 Lines 35-55 for equations]; frequency adjustment at 410 based on LMPR value; Liu Figure 4"no" branch of tree at 408, this branch can be reevaluated after frequency is increased if it must be increased additional times).
Regarding Claim 15, Paul in view of Wang, Li, and Partiwala discloses the method of claim 11 further comprising:
monitoring a temperature of the processor (Paul par. 20, check if CPU is at maximum temp allowed by thermal budget [check would require monitoring the temperature]); and
controlling at least one of the frequencies of the CPU, the frequency of the cache memory, and the frequency of the memory device using the temperature (Paul par. 19, current thermal characteristics of the cores 110, 115 and the thermal budget represent thermal headroom that could be used to increase the DVFS state of one or more of the CPU cores 110; changing the DVFS state results in frequency change [see par. 16 table 1]).
Regarding Claim 16, Paul teaches an electronic device (Paul Figure 1, computer system 100) comprising:
a processor (Paul Figure 1, accelerated processing unit 105); and
a memory device connected to the processor (Paul FIG. 1, system memory 130);
wherein the processor includes:
at least one central processing unit (CPU) (Paul Figure 1, CPU cores 110 inside accelerated processing unit 105) configured to drive a dynamic voltage and frequency scaling (DVFS) module (Paul Figure 1, performance controller 125; and par. 16, performance controller 125 implements dynamic voltage and frequency scaling (DVFS) to adapt voltage and clock levels of the CPU cores 110),
a cache memory configured to temporarily store data for an operation of the at least one CPU (Paul par. 48, functionality supported by processors executing software programs tangibly stored at a computer readable medium, which may include cache [par. 49]),
an activity monitoring unit (AMU) (Paul Figure 1, CPU activity counter 140, a GPU activity counter 145, and memory activity counter 150, which may all be integrated together into performance controller 125 [see par. 25]) configured to monitor performance of the at least one CPU (Paul par. 27, CPU activity counter 145 tracks clock weighted micro-operations per cycle), or monitor traffic of the system bus (Paul par. 39, memory activity counter 150 monitors activity over memory bus),
wherein the DVFS module (Paul Figure 1, performance controller 125) is configured to:
collect microarchitecture information from the AMU (Instant application par. 47 states microarchitecture information may include information related to usages of the cache memory 120 and the memory interface circuit 130 or traffic of a bus 101; and Paul par. 39, memory activity counter 150 monitors activity over memory bus and par. 25, memory activity counter may be a part of performance controller 125);
The remaining limitations of claim 16 are similar in scope to claim 1 as addressed above and are thus rejected under the same rationale.
Regarding Claim 17, Paul in view of Wang, Li, and Partiwala discloses the electronic device of claim 16, wherein the at least one CPU includes an internal cache memory (Liu Col 6 Lines 30-50, memory disclosed may be a first-level (L1) cache, which refers to the smallest and fastest cache memory directly embedded within the processor), and the DVFS module is configured to change a frequency of the internal cache memory using the microarchitecture information (Liu Figure 4 steps 404-410, LMPR is affected by instructions per cycle and memory stalls (i.e., microarchitecture information) [see Col 5 Lines 35-55 for equations]; frequency adjustment at 410 based on LMPR value).
Regarding Claim 18, Paul in view of Wang, Li, and Partiwala discloses the electronic device of claim 16, wherein the DVFS module includes:
a first manager configured to determine the frequency of the at least one CPU using the microarchitecture information (Paul Figure 1, CPU activity counter 140; and Paul par. 27, CPU activity counter tracks clock weighted micro-operations per cycle);
a second manager configured to determine the frequency of the cache memory using the microarchitecture information (Wang pg. 1638 Sec. 6, discusses metrics to monitor memory performance, such as total memory access cycles [i.e., frequency]); and
a third manager configured to determine the frequency of the memory interface circuit using the microarchitecture information (Paul Figure 1, memory activity counter 150; and Paul par. 39, memory activity counter 150 monitors activity over memory bus).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
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