Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24-28 and 33-43 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 20220240014 A1, hereinafter “Sakai”) in view of TS5A22364.
Regarding claim 24, Sakai teaches an audio codec integrated circuit (IC), comprising: an audio input interface; (see Fig. 2: audio IC 900)
an audio output interface, wherein a first one of the audio input interface and the audio output interface comprises a plurality of interface pins, each interface pin configured to receive a respective one of a plurality of audio input signals or output a respective one of a plurality of audio output signals; (see [0005]: serial input interface with four pins; [0032]: audio signals are input to the N (N>1) input pins; [0058]: output coupled to input pins is applied to the output pins of sound source. A plurality of audio input signals or output signals comprise a plurality of interface pins, receiving respective signals)
a plurality of data converters for converting the plurality of audio input signals into the plurality of audio output signals; (see [0032]-[0033]: D/A and A/D converter that converts audio input signals into output signals)
and routing circuitry for routing the plurality of audio input signals to the data converters and the plurality of audio output signals from the data converters, (see [0032]-[0033]: the converters are included in the internal circuit, in which the plurality of audio signals are internally routed in the circuitry)
a second one different from the first one of the audio input interface and the audio output interface comprises: a digital serial interface configured to multiplex the plurality of audio output signals into a serial audio output signal or to demultiplex a received serial audio input signal into the plurality of audio input signals. (see [0060]-[0065]: audio IC 900 includes a serial interface circuit receiver 902. Multi-channel audio signals are combined through multiplexing or serial data received is separated into L and R-channel digital signal, hence demultiplexing)
Sakai is silent to the digital serial interface configurable by at least one select pin to adjust a multiplexing operation of the digital serial interface.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to have chosen to apply the broad teachings of TS5A22364 to the routing circuitry of the IC chip of Sakai in order use a pin to adjust a multiplexing operation of the digital serial interface.
Regarding claim 33, Sakai teaches the serial audio output signal or the received serial audio input signal are encoded using time division multiplexing (TDM) (see [0060]: time division multiplexing (TDM) format is employed )
Regarding claim 34, Sakai teaches the time division multiplexing is synchronous or asynchronous (see [0060]-[0062]: input of a serial audio signal includes several clocks to adjust synchronizing multiple components in time division multiplexing)
Regarding claim 35, Sakai teaches the audio input interface comprises the digital serial interface, wherein the audio input interface is configured to receive the serial audio input signal (see [0065]: the digital audio signals are input to the input pins which are configured to receive the serial audio input signal of the audio interface)
Regarding claim 36, Sakai teaches the audio output interface comprises the digital serial interface, wherein the audio output interface is configured to output the serial audio output signal (see [0066], [0097]: the output selectors select the audio output signals configured to processing the output of the serial audio interface)
Regarding claim 37, Sakai teaches the digital serial interface comprises an audio serial port (ASP) (see [0060]: digital audio signal may include PCM audio data in the I’S format which would require an audio serial port)
Regarding claim 38, Sakai in view of TS5A22364 teaches the routing circuitry is configurable by the at least one select pin to adjust a multiplexing order of the plurality of audio output signals in the serial audio output signal or to adjust an order of extraction of the plurality of audio input signals from the serial audio input signal. (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art that multiplexing order is essentially another form of data routing order.
Regarding claim 39, Sakai teaches an audio processor configured to process one or more of the plurality of audio input signals or the plurality of audio output signal to generate respective processed audio input signals or audio output signals. (see [0028]-[0033]: an internal circuit to process audio signal passed through audio interface circuit, processing the audio input signals or audio output signals)
Regarding claim 40, Sakai teaches the audio input interface comprises the plurality of interface pins; and the plurality of data converters each comprise an analog-to-digital converter (ADC). (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Regarding claim 41, Sakai the audio output interface comprises the plurality of interface pins; and the plurality of data converters each comprise a digital-to-analog converter (DAC). (see [0032]: internal circuit includes a D/A converter when the analog audio signals are input to the N (N>1) input pins, the D/A converter is activated)
Regarding claim 42, Sakai teaches at least one select pin comprises a single select pin drivable at two or more voltage levels, the routing circuitry configurable into two or more routing configurations based on a voltage at the single select pin. (see Fig. 3, [0046]-[0049]: a bias voltage applied to N input pins by two levels where one is obtained by dividing a power supply voltage using a resistor dividing circuit, which is routed to each single select pin)
Regarding claim 43, Sakai teaches at least one select pin comprises a plurality of select pins, the routing circuitry configurable into three or more routing configurations based on a combination of voltages at the plurality of select pins. (see Fig. 3, [0035], [0046]-[0049]: a bias voltage applied to N input pins from P.sub.1 through P.sub.N which can exceed three routing configurations based on the combination of voltage at the plurality of select pins.)
Response to Arguments
On page 5-6 of applicant’s remarks, applicant mainly argues that the art of record fails to disclose digital serial interface configurable by at least one select pin to adjust a multiplexing operation of the digital serial interface. The Examiner disagrees and maintains as pointed out in the rejection above, Sakai teaches a plurality of audio input interfaces for receiving analog audio input signals; a plurality of data converters assignable to the audio input interfaces to convert the analog audio input signals into digital audio signals; (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Sakai fails to teach a hardware pin to select an order of audio inputs from at least first and second predefined input orders, and to assign the selected input order to the digital audio output signals.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Thus, the above arguments are moot because the Office does not rely only on the TS5A22364 for the limitations, but rather a combination with Sakai for a digital output signal while the broadest teaching of TS5A22364 is relied upon for the teaching of using a select pin which controls the routing order.
In regards to page 7 of applicant’s remarks, dependent claims 33-43 are not allowable for the reasons set forth in the rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANNABELLE KANG whose telephone number is (571)270-3403. The examiner can normally be reached Monday-Thursday 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vivian Chin can be reached at 571-272-7848. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANNABELLE KANG/Examiner, Art Unit 2695
/VIVIAN C CHIN/Supervisory Patent Examiner, Art Unit 2695
Prosecution Insights