Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US 20220240014 A1, hereinafter “Sakai”) in view of TS5A22364 and Dabral (US 6192431 B1, hereinafter “Dabral”)
Regarding claim 1, Sakai teaches an audio codec integrated circuit (IC), comprising: an audio input interface; (see Fig. 2: audio IC 900)
an audio output interface, wherein a first one of the audio input interface and the audio output interface comprises a plurality of interface pins, each interface pin configured to receive a respective one of a plurality of audio input signals or output a respective one of a plurality of audio output signals; (see [0005]: serial input interface with four pins; [0032]: audio signals are input to the N (N>1) input pins; [0058]: output coupled to input pins is applied to the output pins of sound source. A plurality of audio input signals or output signals comprise a plurality of interface pins, receiving respective signals)
a plurality of data converters for converting the plurality of audio input signals into the plurality of audio output signals; (see [0032]-[0033]: D/A and A/D converter that converts audio input signals into output signals)
and routing circuitry for routing the plurality of audio input signals to the data converters and the plurality of audio output signals from the data converters, (see [0032]-[0033]: the converters are included in the internal circuit, in which the plurality of audio signals are internally routed in the circuitry)
Sakai fails to teach the routing circuitry configurable by at least one select pin to adjust an order in which of the plurality of audio input signals
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to have chosen to apply the broad teachings of TS5A22364 to the routing circuitry of the IC chip of Sakai in order to adjust the order of routing of signal configured by at least one select pin.
However, Sakai in view of TS5A22364 fail to teach the audio input and output signals are routed in parallel to the data converters.
Dabral teaches the audio input and output signals routed in parallel to the data converters. (see Fig. 1b, Column 4, line 27-40: have a parallel signal bus 141 with bit positions inverted…)
Sakai in vies of TS5A22364 and Dabral are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to have chosen to apply the broad teachings of Dabral to the routing circuitry of the IC chip of Sakai in view of TS5A22364 in order to adjust the order of routing of signal configured by at least one select pin routed in parallel, allowing to receive a plurality of inputs.
Regarding claim 2, Sakai teaches a second one different from the first one of the audio input interface and the audio output interface comprises: a digital serial interface configured to multiplex the plurality of audio output signals into a serial audio output signal or to demultiplex a received serial audio input signal into the plurality of audio input signals. (see [0060]-[0065]: audio IC 900 includes a serial interface circuit receiver 902. Multi-channel audio signals are combined through multiplexing or serial data received is separated into L and R-channel digital signal, hence demultiplexing)
Regarding claim 3, Sakai teaches the serial audio output signal or the received serial audio input signal are encoded using time division multiplexing (TDM) (see [0060]: time division multiplexing (TDM) format is employed )
Regarding claim 4, Sakai teaches the time division multiplexing is synchronous or asynchronous (see [0060]-[0062]: input of a serial audio signal includes several clocks to adjust synchronizing multiple components in time division multiplexing)
Regarding claim 5, Sakai teaches the audio input interface comprises the digital serial interface, wherein the audio input interface is configured to receive the serial audio input signal (see [0065]: the digital audio signals are input to the input pins which are configured to receive the serial audio input signal of the audio interface)
Regarding claim 6, Sakai teaches the audio output interface comprises the digital serial interface, wherein the audio output interface is configured to output the serial audio output signal (see [0066], [0097]: the output selectors select the audio output signals configured to processing the output of the serial audio interface)
Regarding claim 7, Sakai teaches the digital serial interface comprises an audio serial port (ASP) (see [0060]: digital audio signal may include PCM audio data in the I’S format which would require an audio serial port)
Regarding claim 8, Sakai in view of TS5A22364 teaches the routing circuitry is configurable by the at least one select pin to adjust a multiplexing order of the plurality of audio output signals in the serial audio output signal or to adjust an order of extraction of the plurality of audio input signals from the serial audio input signal. (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art that multiplexing order is essentially another form of data routing order.
Regarding claim 9, Sakai teaches an audio processor configured to process one or more of the plurality of audio input signals or the plurality of audio output signal to generate respective processed audio input signals or audio output signals. (see [0028]-[0033]: an internal circuit to process audio signal passed through audio interface circuit, processing the audio input signals or audio output signals)
Regarding claim 10, Sakai teaches the audio input interface comprises the plurality of interface pins; and the plurality of data converters each comprise an analog-to-digital converter (ADC). (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Regarding claim 11, Sakai the audio output interface comprises the plurality of interface pins; and the plurality of data converters each comprise a digital-to-analog converter (DAC). (see [0032]: internal circuit includes a D/A converter when the analog audio signals are input to the N (N>1) input pins, the D/A converter is activated)
Regarding claim 12 and 13, Sakai is silent to an analog and digital multiplexer.
However, it would have been obvious to a person of ordinary skill in the art that an analog multiplexer is simply another well-known type of multiplexer that could have been used in the routing circuitry. The decision to incorporate an analog multiplexer to the IC chip would have been based on the designer’s preference, needs, and considerations such as cost reduction. Since both analog and digital multiplexers are established technologies capable of effectively routing signals, the use of either would not alter the scope of the limitation. The choice between the two would have been a matter of design preference and optimization rather than a novel distinction
Regarding claim 14, Sakai teaches at least one select pin comprises a single select pin drivable at two or more voltage levels, the routing circuitry configurable into two or more routing configurations based on a voltage at the single select pin. (see Fig. 3, [0046]-[0049]: a bias voltage applied to N input pins by two levels where one is obtained by dividing a power supply voltage using a resistor dividing circuit, which is routed to each single select pin)
Regarding claim 15, Sakai teaches at least one select pin comprises a plurality of select pins, the routing circuitry configurable into three or more routing configurations based on a combination of voltages at the plurality of select pins. (see Fig. 3, [0035], [0046]-[0049]: a bias voltage applied to N input pins from P.sub.1 through P.sub.N which can exceed three routing configurations based on the combination of voltage at the plurality of select pins.)
Regarding claim 16, the claimed limitations directly correspond to claim 1; therefore, is rejected for the significant similar reasons as claim 1 as discussed above.
Regarding claim 17, Sakai teaches the digital audio output interface comprises a digital serial interface configured to time division multiplex the plurality of digital audio output signals into a serial digital audio signal. (see [0060]: time division multiplexing (TDM) format is employed to digital audio signals)
Regarding claim 18, the claimed limitations directly correspond to claim 1; therefore, is rejected for the significant similar reasons as claim 1 as discussed above.
Regarding claim 19, Sakai teaches the audio input interface comprises a digital serial interface configured to convert a received digital serial audio input signal into the plurality of digital audio input signals. (see [0065]: the digital audio signals are input to the input pins which are configured to receive the serial audio input signal of the audio interface which converts the received digital serial data)
Regarding claim 20, Sakai teaches a plurality of audio input interfaces for receiving analog audio input signals from respective ones of the plurality of I/O pins; a plurality of data converters assignable to the audio input interfaces to convert the analog audio input signals into digital audio signals; (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Sakai is silent to the data converter in a multiplexed order to one of the plurality of I/O pins, wherein the IC further comprises a hardware pin to selectably configure the IC between at least first and second predefined pinout configurations of the plurality of I/O pins.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to apply a hardwire pin to switch the IC between a first and second interface layout from the teachings of TS5A22364.
Regarding claim 21, Sakai in view of TS5A22364 teaches the hardware pin is configured to selectably configure a multiplexing order of the digital audio output signals based on a voltage at the hardware pin. (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to apply a hardwire pin to switch the IC between a first and second interface layout, as this approach follows the well-known methods of using hardware control signals to modify routing configurations from the teachings of TS5A22364.
Regarding claim 22, Sakai teaches The audio codec IC of claim[[s]]20, wherein the output audio serial interface is configured to output digital audio signals as a time domain multiplexed (TDM) signal. (see [0060]: time division multiplexing (TDM) format is employed)
Regarding claim 23, Sakai teaches a plurality of audio input interfaces for receiving analog audio input signals; a plurality of data converters assignable to the audio input interfaces to convert the analog audio input signals into digital audio signals; (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Sakai fails to teach a hardware pin to select an order of audio inputs from at least first and second predefined input orders, and to assign the selected input order to the digital audio output signals.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to have chosen to apply the broad teachings of TS5A22364 to the routing circuitry of the IC chip of Sakai in order for a device to be modified to adjust the routing order of input signals and assign them to desired digital output signals configured by a hardwire pin.
Regarding claim 24, Sakai teaches an audio codec integrated circuit (IC), comprising: an audio input interface; (see Fig. 2: audio IC 900)
an audio output interface, wherein a first one of the audio input interface and the audio output interface comprises a plurality of interface pins, each interface pin configured to receive a respective one of a plurality of audio input signals or output a respective one of a plurality of audio output signals; (see [0005]: serial input interface with four pins; [0032]: audio signals are input to the N (N>1) input pins; [0058]: output coupled to input pins is applied to the output pins of sound source. A plurality of audio input signals or output signals comprise a plurality of interface pins, receiving respective signals)
a plurality of data converters for converting the plurality of audio input signals into the plurality of audio output signals; (see [0032]-[0033]: D/A and A/D converter that converts audio input signals into output signals)
and routing circuitry for routing the plurality of audio input signals to the data converters and the plurality of audio output signals from the data converters, (see [0032]-[0033]: the converters are included in the internal circuit, in which the plurality of audio signals are internally routed in the circuitry)
a second one different from the first one of the audio input interface and the audio output interface comprises: a digital serial interface configured to multiplex the plurality of audio output signals into a serial audio output signal or to demultiplex a received serial audio input signal into the plurality of audio input signals. (see [0060]-[0065]: audio IC 900 includes a serial interface circuit receiver 902. Multi-channel audio signals are combined through multiplexing or serial data received is separated into L and R-channel digital signal, hence demultiplexing)
Sakai is silent to the digital serial interface configurable by at least one select pin to adjust a multiplexing operation of the digital serial interface.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Sakai and TS5A22364 are considered to be analogous to the claimed invention because both are in the field of an audio codec integrated circuit (IC) chip. It would have been obvious to a person of ordinary skill in the art to have chosen to apply the broad teachings of TS5A22364 to the routing circuitry of the IC chip of Sakai in order use a pin to adjust a multiplexing operation of the digital serial interface.
Regarding claim 25, Sakai teaches a device comprising the audio codec IC. (see Fig. 2: audio IC 900)
Regarding claim 26, Sakai is silent to the device comprises an audio interface, the audio interface comprising: the audio codec IC; an input and/or output connector for coupling with the audio input interface and/or the audio output interface of the IC; and a hardware switch or jumper coupled with the at least one select pin of the IC.
However, it would have been obvious to a person of ordinary skill in the art to couple a hardware switch or jumper with at least one select pin of the IC, as this is a well-known practice for enabling operational switching. Such switches are commonly used to activate different modes or configurations based on the design needs. The switch would simply trigger the adjustment of the routing order, allowing input signals to be readjusted to desired digital outputs.
Regarding claim 27, Sakai is silent to the device comprises a mobile phone, a tablet computer, a laptop, a speaker system, an audio amplifier, an audio mixing desk, an audio card.
However, official notice is taken that the IC chip could be used in a multimedia electronic. As such systems commonly integrate known components to enhance functionality, it would have been obvious to incorporate such features.
Regarding claim 28, Sakai is silent to the device is configured for mounting in an audio rack.
However, it is a well-known technique in the art to mount a device on an audio rack to improve accessibility and usability.
Regarding claims 29-32, the claimed limitations directly correspond to claims 25-28; therefore, is rejected for the significant similar reasons as claims 25-28 as discussed above.
Response to Arguments
Applicant's arguments filed July 25, 2025 have been fully considered but they are not persuasive. On page 11-14 of Applicant’s remarks, Applicant mainly argues that the combined teaching from prior art Sakai and TS5A22364 cited in the previous office action fails to teach the newly amended limitation which states routing circuitry configurable by at least one select pin to adjust an order in which routing of a plurality of audio input signals are routed in parallel to the data converters or an order in which the plurality of audio output signals are routed in parallel from the data converters, as recited in newly amended independent Claims 1, 16, and 18. The above arguments are moot due to the new ground rejections as set forth above.
On page 15 of Applicant’s remarks, Applicant mainly argues that the combined teaching from prior art Sakai and TS5A22364 cited in the previous office action fails to teach the newly amended limitation which states a multiplexed order to one of the plurality of I/O pins, wherein the IC further comprises a hardware pin to selectably configure the IC between at least first and second predefined pinout configurations of the plurality of I/O pins recited in claim 20. The Office disagrees. As pointed out in the rejection above, Sakai in view of TS5A22364 clearly teaches a plurality of audio input interfaces for receiving analog audio input signals from respective ones of the plurality of I/O pins; a plurality of data converters assignable to the audio input interfaces to convert the analog audio input signals into digital audio signals; (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Sakai is silent to the data converter in a multiplexed order to one of the plurality of I/O pins, wherein the IC further comprises a hardware pin to selectably configure the IC between at least first and second predefined pinout configurations of the plurality of I/O pins.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces as shown in the figure).
The above arguments are moot because the Office does not rely only on the TS5A22364 for the above teachings, but rather a combination with Sakai for a digital output signal while the broadest teaching of TS5A22364 is relied upon for the teaching of using a select pin which controls the routing order.
On page 16-18 of Applicant’s remarks, Applicant mainly argues that the combined teaching from prior art Sakai and TS5A22364 cited in the previous office action fails to teach the disclosed switch to route digital audio output signals as recited in claim 23 and digital serial interface is configurable by at least one select pin to adjust a multiplexing operation of the digital serial interface as recited in claim 24. The Office disagrees. As pointed out in the rejection above, Sakai teaches a plurality of audio input interfaces for receiving analog audio input signals; a plurality of data converters assignable to the audio input interfaces to convert the analog audio input signals into digital audio signals; (see [0033]: internal circuit includes an A/D converter when the analog audio signals are input to the N (N>1) input pins, the A/D converter is activated)
Sakai fails to teach a hardware pin to select an order of audio inputs from at least first and second predefined input orders, and to assign the selected input order to the digital audio output signals.
However, TS5A22364 teaches the idea of using a select pin (see figure of page 1: "input select") which controls the routing order (e.g., switching of two different audio interfaces by a selector pin as shown in the figure).
Thus, the above arguments are moot because the Office does not rely only on the TS5A22364 for the limitations, but rather a combination with Sakai for a digital output signal while the broadest teaching of TS5A22364 is relied upon for the teaching of using a select pin which controls the routing order.
Conclusion
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/ANNABELLE KANG/Examiner, Art Unit 2695
/VIVIAN C CHIN/Supervisory Patent Examiner, Art Unit 2695