DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In view of the appeal brief filed on April 13, 2026, PROSECUTION IS HEREBY REOPENED. New grounds of rejection set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 2, 4 – 6 and 9 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirler et al. (US 2004/0089910).
PNG
media_image1.png
513
505
media_image1.png
Greyscale
(Claim 1) Hirler et al. teach a semiconductor device comprising:
a semiconductor layer (7) in which a trench (6) is formed;
a buried electrode (63) provided inside the trench;
an upper electrode (62) provided above the buried electrode inside the trench;
an insulating film (33/32/322) provided inside the trench;
a first electrode (53) provided on an upper surface of the semiconductor layer; and
a second electrode (52) provided on a lower surface of the semiconductor layer,
wherein the insulating film includes a first portion (32) between the buried electrode (53) and a side wall of the trench (6),
a second portion (33) between the upper electrode (62) and the side wall of the trench (8), and
a third portion (332) between the buried electrode (63) and the upper electrode (62), and
a fourth portion (32, under the bottom of 63) between a lower surface of the buried electrode (63) and a lower surface of the trench (6),
a lower (bottom) surface of the upper electrode (62) has a dent (see region 332) in a central portion; and
the upper electrode has a portion in which a side surface has an incline inward of the trench such that the incline extends all the way to a lowest surface of the upper electrode (see incline at lower sidewall of #62).
(Claim 2) Hirler et al. teach the second portion (33) of the insulating film is thicker (divergence of 33 at the incline) downward.
(Claim 4) Hirler et al. teach wherein the semiconductor layer includes a first semiconductor layer (21) of a first conductive type (N, paragraph 36), and a second semiconductor layer (22) of a second conductive type (P, paragraph 36) provided on the first semiconductor layer, the second conductive type being different from the first conductive type, and
among the second portion (33) of the insulating film, a portion (from the incline) adjacent to the first semiconductor layer (21) is thicker than a portion (33) adjacent to the second semiconductor layer (22).
(Claim 5) Hirler et al. teach wherein the third portion (322) is thicker than the second portion (33, paragraph 38).
(Claim 6) Hirler et al. teach wherein the first portion (32) is thicker than the second portion (33, paragraph 38).
(Claim 9) Hirler et al. teach wherein the semiconductor layer is made with a wide band gap semiconductor (paragraph 37).
(Claim 10) Hirler et al. teach wherein the wide band gap semiconductor is silicon carbide, gallium-nitride-based material or diamond (paragraph 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 7 and 11 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al. (US 2017/0062574) in view of Hirler et al. (US 2004/0089910).
PNG
media_image2.png
671
411
media_image2.png
Greyscale
(Claim 1) Nagata et al. teach a semiconductor device comprising:
a semiconductor layer (2) in which a trench (13) is formed;
a buried electrode (22) provided inside the trench;
an upper electrode (21) provided above the buried electrode inside the trench;
an insulating film (20/23/25) provided inside the trench;
a first electrode (fig. 4 #4) provided on an upper surface of the semiconductor layer; and
a second electrode (paragraph 46, drain) provided on a lower surface of the semiconductor layer,
wherein the insulating film includes a first portion (24) between the buried electrode (22) and a side wall of the trench (13),
a second portion (25/30) between the upper electrode (21) and the side wall of the trench (13), and
a third portion (23) between the buried electrode (22) and the upper electrode (21), and
a fourth portion (20) between a lower surface of the buried electrode and a lower surface of the trench,
a lower (bottom) surface of the upper electrode (21) has a dent (see curvature of #23) in a central portion.
Nagata et al. lack wherein the upper electrode has a portion in which a side surface has an incline inward of the trench such that the incline extends all the way to a lowest surface of the upper electrode.
However, Hirler et al. teach wherein the upper electrode (fig. 3 #62) has a portion in which a side surface has an incline inward of the trench such that the incline extends all the way to a lowest surface of the upper electrode for the benefit of reducing gate/drain capacitance (paragraph 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of reducing gate/drain capacitance.
(Claim 2) Nagata et al. teach the second portion (25) of the insulating film is thicker (30) downward.
(Claim 4) Nagata et al. teach wherein the semiconductor layer includes a first semiconductor layer (17) of a first conductive type (N), and a second semiconductor layer (16) of a second conductive type (P) provided on the first semiconductor layer, the second conductive type being different from the first conductive type, and
among the second portion (25) of the insulating film, a portion (30) adjacent to the first semiconductor layer (17) is thicker than a portion (25) adjacent to the second semiconductor layer (16).
(Claim 5) Nagata et al. teach wherein the third portion (23) is thicker than the second portion (25).
(Claim 6) Nagata et al. teach wherein the first portion (24) is thicker than the second portion (25).
(Claim 7) Nagata et al. teach wherein irregularities on an upper surface of the buried electrode (oxidized, paragraph 89) are smaller than irregularities on an upper surface of the upper electrode.
(Claim 11) Nagata et al. teach a method for manufacturing a semiconductor device, the method comprising:
forming a trench (fig. 6A #13) in a semiconductor layer;
forming a buried electrode (fig. 6C #22) and a first oxide film (53, paragraphs 69, 70) that separates the buried electrode (22) from a side wall of the trench, and separates a lower surface (13) of the buried electrode (22) from a lower surface of the trench, inside the trench;
removing part of the first oxide film so that a portion (fig. 6D #55) above the buried electrode (22), among the first oxide film, has a tapered shape;
forming a second oxide film (fig. 6G #56/23/30, paragraph 77) so as to cover an upper surface of the buried electrode (22), the side wall of the trench and the portion having the tapered shape; and
forming an upper electrode (fig. 6H #57) on the second oxide film (56/23/30) inside the trench.
Nagata et al. lack wherein the upper electrode has a portion in which a side surface has an incline inward of the trench such that the incline extends all the way to a lowest surface of the upper electrode.
However, Hirler et al. teach wherein the upper electrode (fig. 3 #62) has a portion in which a side surface has an incline inward of the trench such that the incline extends all the way to a lowest surface of the upper electrode for the benefit of reducing gate/drain capacitance (paragraph 43).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of reducing gate/drain capacitance (paragraph 43).
(Claim 12) Nagata et al. teach wherein among the second oxide film (56), a portion (30) between the upper electrode (57) and the side wall of the trench is thicker downward.
(Claim 13) Nagata et al. teach wherein a thickness of the first portion (24) and a thickness of the second portion (30) are substantially equal (paragraphs 56, 57; at T1 =1000 and T4 = 999, T4/T1 = 0.999, which is substantially = 1).
(Claim 14) Nagata et al. teach wherein a thickness of the first oxide film (53/24) between the buried electrode and the semiconductor layer is substantially equal to a thickness of the second oxide film (30) between the upper electrode and the semiconductor layer (paragraphs 56, 57; at T1 =1000 and T4 = 999, T4/T1 = 0.999, which is substantially = 1).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hirler et al. (US 2004/0089910) in view of Chen et al. (US 2019/0378902).
PNG
media_image3.png
453
516
media_image3.png
Greyscale
(Claim 8) Hirler et al. teach wherein the buried electrode (63) is formed of doped polycrystalline silicon (polysilicon, paragraph 38), but lack amorphous silicon.
However, Chen et al teach wherein the buried electrode (106) is formed of amorphous silicon (paragraph 17) as art recognized equivalents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents.
Response to Arguments
Applicant’s arguments with respect to claims filed September 10, 2025 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IGWE U ANYA/Primary Examiner, Art Unit 2891
May 12, 2026
Prosecution Insights