SYSTEMS AND METHODS FOR REDUCING LOCAL OSCILLATOR LEAKAGE

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dawe (Pub. No.: US 2010/0171542 A1). With respect to claim 1: Dawe discloses a circuit, comprising: a mixer having a first local oscillator input port (fig. 1, item 100 is a mixer with local oscillator 106); and a bias control circuit, configured to control a bias at the first local oscillator input port (parag. 0050). With respect to claim 2: Dawe discloses the circuit of claim 1, wherein: the first local oscillator input port is a first positive local oscillator input port, and the mixer further has: a second positive local oscillator input port; a first negative local oscillator input port; and a second negative local oscillator input port (fig. 5, parag. 0055). With respect to claim 3: Dawe discloses the circuit of claim 2, wherein the bias control circuit comprises a first bias supply circuit for adjusting: a bias at the first positive local oscillator input port and a bias at the second positive local oscillator input port relative to: a bias at the first negative local oscillator input port and a bias at the second negative local oscillator input port (fig. 5, parag. 0055). With respect to claims 4, 19: Dawe discloses the circuit of claim 3, wherein the first bias supply circuit comprises a four-output current digital to analog converter (fig. 19 with 408a-408d). With respect to claims 11, 16: Dawe discloses the circuit of claim 1, wherein the mixer comprises four switches (fig. 14, parag. 0070). With respect to claims 12, 17: Dawe discloses the circuit of claim 11, wherein each of the four switches is a field effect transistor (fig. 14). With respect to claims 13, 18: Dawe discloses the circuit of claim 12, wherein the mixer has four local oscillator input ports including the first local oscillator input port, each of the four local oscillator input ports being a gate of a respective one of the field effect transistors (fig. 14, LOP, LOM). With respect to claims 14, 20: Dawe discloses a circuit comprising: a mixer having four local oscillator input ports (fig. 14, with LOP and LOM represents oscillator input ports as in parag. 0055); and a bias control circuit (fig. 5, item 306); the bias control circuit being configured: to provide, to the four respective local oscillator input ports of the mixer: a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal, respectively; to control second harmonic local oscillator leakage (fig. 5, item 306 provide to bias LOP and LOM). With respect to claim 15: Dawe discloses the circuit of claim 14, further comprising the mixer, wherein: the first bias signal is connected to a first positive local oscillator input port of the mixer, the second bias signal is connected to a second positive local oscillator input port of the mixer, the third bias signal is connected to a first negative local oscillator input port of the mixer, the fourth bias signal is connected to a second negative local oscillator input port of the mixer (fig. 5, parag. 0055). Allowable Subject Matter Claims 5-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claims 1, 14 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJIBOLA A AKINYEMI whose telephone number is (571)270-1846. The examiner can normally be reached Monday-Friday 8:00am-5:00pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AJIBOLA A AKINYEMI/Primary Examiner, Art Unit 2649