DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on11/17/25 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 2, 3, 5, 11, 14-16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mu (Pub. No.: US 2010/0081408 A1) and further in view of Chakraborty (Pub. No.: US 2024/0162921 A1) and Patel (Pub. No.: US 2020/0266842 A1).
With respect to claim 1:
Mu discloses a circuit, comprising a mixer (fig. 2, item 100 as in parag. 0016); and a bias control circuit (fig. 2, item 140 as in parag. 0022), the mixer having a first local oscillator input (fig. 2, with item 130 that generate LO1), the bias control circuit being configured to control a bias at the first local oscillator input. (fig. 2, item 140 controls LO1 through 130).
Mu does not explicitly disclose the bias control circuit comprising a first current digital to analog converter and a second current digital to analog converter, wherein the first current digital to analog converter is configured to adjust local oscillator leakage, and the second current digital to analog converter is configured to adjust second harmonic local oscillator leakage.
Chakraborty discloses bias control circuit (fig. 1, item 190 is a control which contain component of the bias control as disclosed in parag. 0068) comprising a first current digital to analog converter (fig. 1, item 121) connected to the first local oscillator input of the mixer (fig. 1) and a second current digital to analog converter (fig. 1, item122) connected to the first local oscillator input of the mixer (fig. 1) wherein the first current digital to analog converter is configured to adjust local oscillator leakage (parag. 0079), and the second current digital to analog converter is configured to adjust second local oscillator leakage (parag. 0080, 0105).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Chakraborty into the teaching of MU in order to calibrate and suppress unwanted sideband images and spurious signals.
Mu and Chakraborty do not explicitly mention the word harmonic.
Patel discloses cancellations for images, sidebands and LO leakages second and third order harmonic distortion (parag. 0063). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Patel into the teaching of MU in view of Chakraborty in order to reduce clocking leakage, nonlinearities, and undesired sidebands.
With respect to claim 2:
Mu discloses the circuit of claim 1, wherein: the first local oscillator input is a first positive local oscillator input, and the mixer further has: a second positive local oscillator input; a first negative local oscillator input; and a second negative local oscillator input (fig. 5, parag. 0032).
With respect to claim 3:
MU discloses the circuit of claim 2, wherein the bias control circuit comprises a first bias supply circuit for adjusting: a bias at the first positive local oscillator input and a bias at the second positive local oscillator input relative to: a bias at the first negative local oscillator input and a bias at the second negative local oscillator input (parag. 0030, 0032 discloses that each mixer has its own bias).
With respect to claim 5:
Mu discloses the circuit of claim 3, wherein the bias control circuit further comprises a second bias supply circuit for adjusting: a bias at the first positive local oscillator input and a bias at the first negative local oscillator input relative to: a bias at the second positive local oscillator input and a bias at the second negative local oscillator input (parag. 0032-0034).
With respect to claims 11, 16:
Mu discloses the circuit of claim 1, wherein the mixer comprises four switches (parag. 0032 and fig. 3).
With respect to claim 14:
Mu discloses a circuit comprising a bias control circuit (fig. 2, item 140 as in parag. 0022); the bias control circuit being configured to provide, to four respective local oscillator inputs of a mixer (fig. 3, with mixers 112 and bias signals Gb1…..Gb(M)); a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal (fig. 3, Gb(1)…..Gb(M) represents first bias-fourth bias signals) and to control second harmonic local oscillator leakage (parag. 0030).
Mu does not explicitly disclose the bias control circuit comprising a first current digital to analog converter and a second current digital to analog converter, wherein the first current digital to analog converter is configured to adjust local oscillator leakage, and the second current digital to analog converter is configured to adjust second harmonic local oscillator leakage.
Chakraborty discloses bias control circuit (fig. 1, item 190 is a control which contain component of the bias control as disclosed in parag. 0068) comprising a first current digital to analog converter (fig. 1, item 121) connected to the first local oscillator input of the mixer (fig. 1) and a second current digital to analog converter (fig. 1, item122) connected to the first local oscillator input of the mixer (fig. 1) wherein the first current digital to analog converter is configured to adjust local oscillator leakage (parag. 0079), and the second current digital to analog converter is configured to adjust second local oscillator leakage (parag. 0080, 0105).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Chakraborty into the teaching of MU in order to calibrate and suppress unwanted sideband images and spurious signals.
Mu and Chakraborty do not explicitly mention the word harmonic.
Patel discloses cancellations for images, sidebands and LO leakages second and third order harmonic distortion (parag. 0063). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Patel into the teaching of MU in view of Chakraborty in order to reduce clocking leakage, nonlinearities, and undesired sidebands.
With respect to claim 15:
Mu discloses the circuit of claim 14, further comprising the mixer, wherein: the first bias signal is connected to a first positive local oscillator input of the mixer, the second bias signal is connected to a second positive local oscillator input of the mixer, the third bias signal is connected to a first negative local oscillator input of the mixer, the fourth bias signal is connected to a second negative local oscillator input of the mixer (parag. 0030, 0032 discloses that each mixer has its own bias).
With respect to claim 20:
Mu discloses a circuit comprising: means for bias control (fig. 2, item 140 as in parag. 0022); the means for bias control being configured to provide, to four respective local oscillator inputs of a mixer (fig. 3, with mixers 112 and bias signals Gb1…..Gb(M)); a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal; and to control second harmonic local oscillator leakage(fig. 3, Gb(1)…..Gb(M) represents first bias-fourth bias signals and parag. 0030).
Mu does not explicitly disclose the bias control circuit comprising a first current digital to analog converter and a second current digital to analog converter, wherein the first current digital to analog converter is configured to adjust local oscillator leakage, and the second current digital to analog converter is configured to adjust second harmonic local oscillator leakage.
Chakraborty discloses bias control circuit (fig. 1, item 190 is a control which contain component of the bias control as disclosed in parag. 0068) comprising a first current digital to analog converter (fig. 1, item 121) connected to the first local oscillator input of the mixer (fig. 1) and a second current digital to analog converter (fig. 1, item122) connected to the first local oscillator input of the mixer (fig. 1) wherein the first current digital to analog converter is configured to adjust local oscillator leakage (parag. 0079), and the second current digital to analog converter is configured to adjust second local oscillator leakage (parag. 0080, 0105).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Chakraborty into the teaching of MU in order to calibrate and suppress unwanted sideband images and spurious signals.
Mu and Chakraborty do not explicitly mention the word harmonic.
Patel discloses cancellations for images, sidebands and LO leakages second and third order harmonic distortion (parag. 0063). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Patel into the teaching of MU in view of Chakraborty in order to reduce clocking leakage, nonlinearities, and undesired sidebands.
Claims 4, 6, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Mu (Pub. No.: US 2010/0081408 A1), Chakraborty (Pub. No.: US 2024/0162921 A1), Patel (Pub. No.: US 2020/0266842 A1) applied to claim 1 above, and further in view of Tanaka (Pub. No.: US 2006/0189283 A1).
With respect to claims 4, 6, 19:
The rejection of claim 1 is incorporated; Mu, Chakraborty and Patel do not explicitly disclose wherein the first bias supply circuit comprises a four- output current digital to analog converter.
Tanaka discloses wherein the first bias supply circuit comprises a four- output current digital to analog converter (parag. 0048).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Tanaka into the teaching of Mu in view of Chakraborty and Patel in order to suppress a carrier leak occurring with non-constant envelope modulation by which frequency modulation is conducted.
Claims 7-9, 12, 13, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mu (Pub. No.: US 2010/0081408 A1), Chakraborty (Pub. No.: US 2024/0162921 A1), Patel (Pub. No.: US 2020/0266842 A1) as applied to claim 1 above, and further in view of Ito (Pub. No.: US 2019/0068129 A1).
With respect to claim 7:
The rejection of claim 1 is incorporated; Mu, Chakraborty and Patel do not explicitly disclose a combining circuit for combining a bias generated by the first bias supply circuit with a bias generated by the second bias supply circuit.
Ito discloses a combining circuit for combining a bias generated by the first bias supply circuit with a bias generated by the second bias supply circuit (fig. 1, with combiner 150 combining bias signal 121 and 122 at 150). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to utilize the teaching of Ito into the teaching of Mu in view of Chakraborty and Patel in order to suppress the harmonic distortion.
With respect to claim 8:
Ito discloses the circuit of claim 7, wherein the combining circuit comprises a resistor network (fig. 5).
With respect to claim 9:
Ito discloses the circuit of claim 8, wherein the combining circuit is further configured to combine a common mode bias with the bias generated by the first bias supply circuit and the bias generated by the second bias supply circuit (fig. 2 and 5).
With respect to claim 10:
Ito discloses the circuit of claim 9, further comprising a unity-gain operational amplifier to produce the common mode bias (parag. 0051).
With respect to claims 12, 17:
Ito discloses the circuit of claim 1, wherein the mixer comprises four switches is a field effect transistor. (parag. 0036).
With respect to claim 13:
Mu discloses the circuit of claim 12, wherein the mixer has four local oscillator inputs including the first local oscillator input, each of the four local oscillator inputs being a gate of a respective one of the field effect transistors (fig. 3 with LO(1)….LO(M).
With respect to claim 18:
Ito discloses the circuit of claim 17, wherein each of the local oscillator inputs of the mixer is a gate of a respective one of the field effect transistors (parag. 0037 and 0040).
Response to Arguments
Applicant’s arguments with respect to claims 1, 14 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/AJIBOLA A AKINYEMI/Primary Examiner, Art Unit 2649