DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raj et al. (US 20150139257).
Regarding claim 1, Raj et al. discloses in figure 6 and specification:
1. An edge detector (see, 630, fig. 6, see also, paragraph [0041]-[0042]) applied to a vertical-cavity surface-emitting laser (see, 602, fig. 6), the edge detector comprising:
an alignment circuit (see, 620, fig. 6, see also, paragraph [0043], here, equalization delay module 620) configured to receive a plurality of sets of differential input data, and align the plurality of sets of differential input data to output a plurality of sets of corresponding differential output data, wherein the plurality of sets of differential output data comprise a set of delayed differential output data (see, paragraph [0043]);
a rising-edge detecting circuit (see, paragraph [0043], here, the rising edge detector 430) coupled to the alignment circuit, the rising-edge detecting circuit configured to detect rising edges of the plurality of sets of differential output data to output a plurality of sets of corresponding differential rising data; and
a falling-edge detecting circuit (see, paragraph [0043], here, the falling edge detector 440) coupled to the alignment circuit, the falling-edge detecting circuit configured to detect falling edges of the plurality of sets of differential output data to output a plurality of sets of corresponding differential falling data (see, paragraph [0043]).
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Regarding claim 2, Raj et al. discloses in figure 6 and specification the edge detector according to claim 1, wherein the alignment circuit receives N sets of differential input data and outputs N+1 sets of differential output data, and the edge detector is a one-Nth-rate edge detector (see, paragraph [0043]-[0044]).
Regarding claim 3, Raj et al. discloses in figure 6 and specification the edge detector according to claim 2, wherein the alignment circuit receives four sets of differential input data, the edge detector is a quarter-rate edge detector, and an operating speed of the edge detector is 5 gigabit per second (see, paragraph [0082]).
Regarding claim 4, Raj et al. discloses in figure 6 and specification the edge detector according to claim 1, wherein the rising-edge detecting circuit comprises a plurality of first type logic gates and a plurality of second type logic gates, and each of the first type logic gates and the second type logic gates receives differential output data of a same timing (see, paragraph [0082]).
Regarding claim 5, Raj et al. discloses in figure 6 and specification the edge detector according to claim 4, wherein each of the first type logic gates and the second type logic gates receives in-phase differential output data of different data sequences (see, paragraph [0082]).
Regarding claim 6, Raj et al. discloses in figure 6 and specification the edge detector according to claim 4, wherein a first logic gate among the first type logic gates receives first differential data in the set of delayed differential output data, and a second logic gate among the second type logic gates receives the first differential data in the set of delayed differential output data (see, paragraph [0082]).
Regarding claim 7, Raj et al. discloses in figure 6 and specification the edge detector according to claim 6, wherein the falling-edge detecting circuit comprises a plurality of third type logic gates and a plurality of fourth type logic gates, and each of the third type logic gates and the fourth type logic gates receives differential output data of a same timing, wherein the first type logic gates and the third type logic gates are logic gates of the same type, and the second type logic gates and the fourth type logic gates are logic gates of the same type (see, paragraph [0082]).
Regarding claim 8, Raj et al. discloses in figure 6 and specification the edge detector according to claim 7, wherein each of the third type logic gates and the fourth type logic gates receives in-phase differential output data of different data sequences (see, paragraph [0082]).
Regarding claim 9, Raj et al. discloses in figure 6 and specification the edge detector according to claim 7, wherein a third logic gate among the third type logic gates receives second differential data in the set of delayed differential output data, and a fourth logic gate among the third type logic gates receives the second differential data in the set of delayed differential output data (see, paragraph [0082]).
Regarding claim 10, Raj et al. discloses in figure 6 and specification the edge detector according to claim 9, wherein the plurality of sets of differential rising data and the plurality of sets of differential falling data form a full-rate pulse sequence through a multiplexer circuit (see, paragraph [0082]).
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kinam Park whose telephone number is (571) 270-1738. The examiner can normally be reached on from 9:00 AM-5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, MINSUN HARVEY, can be reached on (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/KINAM PARK/Primary Examiner, Art Unit 2828
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