Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/10/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, filed 11/14/2025, with respect to the rejection(s) of claim(s) 1 - 20 under 35 U.S.C. 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Mortazavi.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mortazavi (US 9209762 B1).
Regarding Independent Claim 1, Mortazavi teaches,
An apparatus (Fig. 1, 10), comprising:
an input circuit (Fig. 1, 12) configured to:
receive an input signal (Fig. 1, signal input at 12); and
generate a buffered signal (Fig. 1, signal output at 12) using the input signal (Fig. 1, signal input at 12);
a power supply circuit (Fig. 1, LDO1) configured to adjust, based on a magnitude of the buffered signal (Fig. 1, signal output at 12), a voltage level (Fig. 1, Vdd) of a driver power supply node (Fig. 1, Vdd node) over a first continuous range of voltages (Figs. 3A and 3B, Vdd);
a ground supply circuit (Fig. 1, LDO2) configured to adjust, based on the magnitude of the buffered signal (Fig. 1, signal output at 12), a voltage level (Fig. 1, Vss) of a driver ground supply node (Fig. 1, Vss node) over a second continuous range of voltages (Figs. 3A and 3B, Vss); and
a switching amplifier circuit (Fig. 1, 14, N1, and N2) configured to generate an amplified version of the buffered signal (Fig. 1, signal output of 14, N1, and N2) that switches between the voltage level of the driver power supply node and the voltage level of the driver ground supply node (See column 3, lines 48 – 59, “Switching transistors N1 and N2 alternatively conduct to generate an output signal that is filtered by an inductor L1 and a capacitor C1, to provide a power audio output signal Audio Out. Power supply rail voltages VDD and VSS are provided to switching transistors N1 and N2 from the outputs of low-dropout regulators (LDOs) LDO1 and LDO2, respectively. In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 2,
The apparatus (Fig. 1, 10) of claim 1, wherein to adjust the voltage level (Fig. 1, Vdd) of the driver power supply node (Fig. 1, Vdd node) over the first continuous range of voltages (Figs. 3A and 3B, Vdd), the power supply circuit is further configured to increase the voltage level of the driver power supply node in response to a determination that the magnitude of the buffered signal has increased (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 3,
The apparatus (Fig. 1, 10) of claim 1, wherein to adjust the voltage level (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node) over the second continuous range of voltages (Figs. 3A and 3B, Vss), the ground supply circuit is further configured to decrease the voltage level of the driver ground supply node relative to a ground reference (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 4,
The apparatus (Fig. 1, 10) of claim 1, wherein to adjust the voltage level (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node) over the second continuous range of voltages (Figs. 3A and 3B, Vss), the ground supply circuit is further configured to increase the voltage level of the driver ground supply node relative to a ground reference (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 5,
The apparatus (Fig. 1, 10) of claim 1, wherein to adjust the voltage level (Fig. 1, Vdd) of the driver power supply node (Fig. 1, Vdd node) over the first continuous range of voltages (Figs. 3A and 3B, Vdd), the power supply circuit is further configured to decrease the voltage level of the driver power supply node in response to a determination that the magnitude of the buffered signal has decreased (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 6,
The apparatus (Fig. 1, 10) of claim 1, wherein to generate the amplified version of the buffered signal (Fig. 1, signal output of 14, N1, and N2), the switching amplifier circuit (Fig. 1, 14, N1, and N2) is configured to:
generate a series of pulses (Fig. 3A and 3B, 14 generates pulse signals to N1 and N2. See column 3, lines 45 – 48, “…Class D Amplifier/Gate driver circuit 14 receives audio input signal Audio In and provides pulse-width modulated output gate control signals to the gates of switching transistors N1 and N2.”) that switch between the voltage level (Fig. 1, Vdd) of the driver power supply node (Fig. 1, Vdd node) and the voltage level (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node); and
adjust respective widths of the series of pulses based on the magnitude of the buffered signal (See column 3, lines 48 – 51, “Switching transistors N1 and N2 alternatively conduct to generate an output signal that is filtered by an inductor L1 and a capacitor C1, to provide a power audio output signal Audio Out.”).
Regarding independent claim 7, Mortazavi teaches,
A method, comprising,
receiving an input signal (Fig. 1, signal input at 12) by a switching amplifier circuit (Fig. 1, 14, N1, and N2) that is coupled to a driver power supply node (Fig. 1, Vdd node) and a driver ground supply node (Fig. 1, Vss node);
adjusting, by a power supply circuit (Fig. 1, LDO1) and based on a magnitude of the input signal (Fig. 1, signal output at 12), a driver power supply voltage (Fig. 1, Vdd) of the driver power supply node (Fig. 1, Vdd) over a first continuous voltage range (Figs. 3A and 3B, Vdd);
adjusting, by a ground supply circuit (Fig. 1, LDO2) and based on the magnitude of the input signal (Fig. 1, signal output at 12), a driver ground supply voltage (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node) over a second continuous voltage range (Figs. 3A and 3B, Vss); and
generating, by the switching amplifier circuit (Fig. 1, 14, N1, and N2), an output signal (Fig. 1, output signal of 14, N1, and N2) that is an amplified version of the input signal (Fig. 1, signal output of 12) that switches between the driver power supply voltage and the driver ground supply voltage (See column 3, lines 48 – 59, “Switching transistors N1 and N2 alternatively conduct to generate an output signal that is filtered by an inductor L1 and a capacitor C1, to provide a power audio output signal Audio Out. Power supply rail voltages VDD and VSS are provided to switching transistors N1 and N2 from the outputs of low-dropout regulators (LDOs) LDO1 and LDO2, respectively. In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 8,
The method of claim 7, wherein adjusting the driver power supply voltage (Fig. 1, Vdd) includes increasing the driver power supply voltage in response to determining that the magnitude of the input signal has increased (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 9,
The method of claim 7, wherein adjusting the driver ground supply voltage (Fig. 1, Vss) includes decreasing the driver ground supply voltage relative to a ground reference (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 10,
The method of claim 7, wherein adjusting the driver ground supply voltage (Fig. 1, Vss) includes increasing the driver ground supply voltage relative to a ground reference (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 11,
The method of claim 7, further comprising adjusting the driver ground supply voltage (Fig. 1, Vss) in phase with adjusting (See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”) the driver power supply voltage (Fig. 1, Vdd).
Regarding claim 12,
The method of claim 7, further comprising adjusting the driver ground supply voltage (Fig. 1, Vss) out-of-phase with the adjusting (See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”) the driver power supply voltage (Fig. 1, Vss).
Regarding claim 13,
The method of claim 7, wherein the input signal (Fig. 1, signal input at 12) includes a plurality of data packets (Fig. 1, Digital Volume In) encoded according to a communication protocol, and further comprising:
translating, by a buffer circuit (Fig. 1, 12), the plurality of data packets to a plurality of words (Fig. 1, Digital Volume In gets translated into CV1 and CV2);
adjusting, by the power supply circuit (Fig. 1, LDO1) using the plurality of words (Fig. 1, CV1), the driver power supply voltage (Fig. 1, Vdd); and
adjusting, by the ground supply circuit (Fig. 1, LDO2) using the plurality of words (Fig. 1, CV2), the driver ground supply voltage (Fig. 1, Vss).
Regarding independent claim 14, Mortazavi teaches,
An apparatus, comprising:
a supply tracking amplifier circuit (Fig. 1, 10) including a switching amplifier circuit (Fig. 1, 14, N1, and N2), wherein the supply tracking amplifier circuit (Fig. 1, 10) is configured to:
receive an input signal (Fig. 1, signal input at 12);
adjust, over a first continuous range of voltages (Figs. 3A and 3B, Vdd), a first magnitude of a first voltage level (Fig. 1, Vdd) of a driver power supply node (Fig. 1, Vdd node) based on a magnitude of the input signal (Fig. 1, signal output at 12);
adjust, over a second continuous range of voltages (Figs. 3A and 3B, Vss), a second magnitude of a second voltage level (Fig. 1, Vss) of a driver ground supply node (Fig. 1, Vss node) based on the magnitude of the input signal (Fig. 1, signal output at 12); and
generate an amplified signal (Fig. 1, signal output of 14, N1, and N2) based on the input signal (Fig. 1, signal input at 12), wherein the amplified signal switches (See column 3, lines 48 – 59, “Switching transistors N1 and N2 alternatively conduct to generate an output signal that is filtered by an inductor L1 and a capacitor C1, to provide a power audio output signal Audio Out. Power supply rail voltages VDD and VSS are provided to switching transistors N1 and N2 from the outputs of low-dropout regulators (LDOs) LDO1 and LDO2, respectively. In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”) between the first voltage level (Fig. 1, Vdd) and the second voltage level (Fig. 1, Vss); and
a speaker (Fig. 1, L1 and C1) configured to generate sounds waves (Fig. 1, Audio Out) using the amplified signal (Fig. 1, signal output at 14, N1, and N2. See column 3, lines 48 – 51, “Switching transistors N1 and N2 alternatively conduct to generate an output signal that is filtered by an inductor L1 and a capacitor C1, to provide a power audio output signal Audio Out.”).
Regarding claim 15,
The apparatus of claim 14, wherein to adjust the second magnitude of the second voltage level (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node), the supply tracking amplifier circuit (Fig. 1, 10) is further configured to increase the second voltage level of the driver ground supply node in response to a determination that the magnitude of the input signal has increased (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 16,
The apparatus of claim 14, wherein to adjust the second magnitude of the second voltage (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node), the supply tracking amplifier circuit (Fig. 1, 10) is further configured to decrease the second voltage level of the driver ground supply node relative to a ground reference (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 17,
The apparatus of claim 14, wherein to adjust the second magnitude of the second voltage (Fig. 1, Vss) of the driver ground supply node (Fig. 1, Vss node), the supply tracking amplifier circuit (Fig. 1, 10) is further configured to increase the second voltage level of the driver ground supply node relative to a ground reference (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 18,
The apparatus of claim 14, wherein the supply tracking amplifier circuit (Fig. 1, 10) is further configured to adjust the second magnitude of the second voltage level (Fig. 1, Vss) of the driver ground supply node in phase with adjusting the first magnitude of the first voltage level (Fig. 1, Vdd) of the driver power supply node (Figs. 3A and 3B, Vdd and Vss both respectively increase or decrease in response to input signals CV1 and CV2. See column 3, lines 54 – 59, “In order to provide volume control in class-D power amplifier integrated circuit 10, the power supply rail voltages are varied by changing power supply control input signals CV1 and CV2 provided to reference voltage inputs of LDOs LDO1 and LDO2, which improves performance of class-D power amplifier integrated circuit 10.”).
Regarding claim 19,
The apparatus of claim 14, wherein to generate the amplified signal (Fig. 1, signal output at 14, N1, and N2), the supply tracking amplifier circuit (Fig. 1, 10) is configured to:
generate a series of pulses (Fig. 3A and 3B, 14 generates pulse signals to N1 and N2. See column 3, lines 45 – 48, “…Class D Amplifier/Gate driver circuit 14 receives audio input signal Audio In and provides pulse-width modulated output gate control signals to the gates of switching transistors N1 and N2.”) that switch between the first voltage level (Fig. 1, Vdd) of the driver power supply node and the second voltage level (Fig. 1, Vss) of the driver ground supply node; and
adjust a frequency of the series of pulses based on the magnitude of the input signal (See column 3, lines 48 – 51, “Switching transistors N1 and N2 alternatively conduct to generate an output signal that is filtered by an inductor L1 and a capacitor C1, to provide a power audio output signal Audio Out.”).
Regarding claim 20,
The apparatus of claim 14, wherein the input signal (Fig. 1, signal input at 12) includes a plurality of data packets (Fig. 1, Digital Volume In) encoded according to a communication protocol, and wherein the supply tracking amplifier circuit (Fig. 1, 10) is further configured to:
translate the plurality of data packets to a plurality of words (Fig. 1, Digital Volume In gets translated into CV1 and CV2);
adjust the first magnitude of the first voltage level (Fig. 1, Vdd) of the driver power supply node using the plurality of words (Fig. 1, CV1); and
adjust the second magnitude of the second voltage level (Fig. 1, Vss) of the driver ground supply node using the plurality of words (Fig. 1, CV2).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843