Office Action Predictor
Last updated: April 15, 2026
Application No. 18/182,692

IMAGE PROCESSING APPARATUS, NOTIFICATION METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM

Final Rejection §103
Filed
Mar 13, 2023
Examiner
MCFARLAND-BARNES, KELAH JANAE
Art Unit
2431
Tech Center
2400 — Computer Networks
Assignee
Seiko Epson Corporation
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
2y 12m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
2 granted / 2 resolved
+42.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
18 currently pending
Career history
20
Total Applications
across all art units

Statute-Specific Performance

§101
12.9%
-27.1% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
14.1%
-25.9% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2 resolved cases

Office Action

§103
DETAILED ACTION In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This Office Action is in response to the communication filed on 10/09/2025. Claims 1-3, 6-7, and 10-11 have been amended. Claims 1-11 are pending for consideration. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claims 1, 10, and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Michishita (U.S. 11,669,609)(hereinafter Michishita) in view of Kawazu (U.S. 12,316,818)(hereinafter Kawazu). Regarding claims 1, 10, and 11, Michishita teaches an image processing apparatus (Michishita: see FIG. 1 item 100) comprising: a first printing unit (Michishita: see FIG. 1 item 130; Col 4 lines 3-5, "The image forming apparatus 100 includes a main controller 110, an embedded controller 103, an operation panel 120, a printer unit 130, and a scanner unit 140"); a printing controller that performs control of the first printing unit (Michishita: see FIG. 2 item 213; Col 5 lines 63-65, "The printer control unit 213 is a program for controlling the printer unit 130 via the printer I/F 116"); a controller that performs at least control other than the control of the first printing unit (Michishita: see FIG. 1 item 110; see Col 5 lines 47-57, "The main controller 110 includes a main system 210 as a software configuration, and programs for realizing various functions of the image forming apparatus 100 according to the present embodiment are arranged in the main system 210. The main system 210 includes a boot control unit 211, an operation unit control unit 212, a printer control unit 213, a scanner control unit 214, a USB control unit 215, a communication processing unit 216, an update processing unit 217, a white list managing unit 218, a detection control unit 219, a control switching unit 220, and a verification unit 221"); a first tampering detector that performs detection of tampering of a first program to be stored in a first nonvolatile memory and to be executed by the controller (Michishita: see FIG. 2 see item 221; Col 7 lines 33-35, "The verification unit 221 functions as a first verification unit and verifies programs stored in the ROM 112 when the system-boot by the main controller 110 is performed"); and a second tampering detector that performs detection of tampering of a second program to be stored in a second nonvolatile memory different from the first nonvolatile memory and to be executed by the printing controller (Michishita: see FIG. 2 item 219; Col 6 lines 44-47, "The detection control unit 219 functions as a second verification unit and verifies validity (tampering or a change due to aging deterioration) when firmware is to be executed or a file is to be opened"; Col 6 lines 60-67, "The detection control unit 219 performs the followings to defend file access. (1) Control of rewriting into files stored in the ROM 112 and the HDD 114. (2) Control of reading of files stored in the ROM 112 and the HDD 114. (3) Control of binary execution in the ROM 112 and the HDD 114. (4) Control of script execution in the ROM 112 and the HDD 114. Details of these will be described later using FIG. 3"). However, Michishita does not teach a notification unit that performs a first notification and a second notification with a notification content that differs between the first notification corresponding to a first detection result obtained by the first tampering detector and the second notification corresponding to a second detection result obtained by the second tampering detector. Nevertheless, Kawazu-which is in the same field of endeavor- teaches a notification unit (Kawazu: see FIG. 3 item 314) that performs a first notification and a second notification with a notification content that differs between the first notification corresponding to a first detection result obtained by the first tampering detector and the second notification corresponding to a second detection result obtained by the second tampering detector (Kawazu: see Col 5 lines 48-52, "If the first alteration detection unit 311 detects an alteration of the white list, the first alteration detection unit 311 notifies the user of the alteration detection via a notification unit 314 (described below) and then deactivates the system"; Col 6 lines 12-18, "If an execution module is not registered in the white list, the second alteration detection unit 312 inhibits (stops) only the execution of the execution module, continuously operates the system without deactivation, and notifies the user that the execution module has been stopped via the notification unit 314 (described below)"). Michishita and Kawazu are analogous art because they are from the same field of endeavor. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to utilize Michishita tamper detection system with Kawazu’s notification method. The suggestion/motivation for doing so would be to provide a user with troubleshooting or repair information when tampering is detected. Regarding claim 8, Michishita and Kawazu teach the first program and the second program are different programs (Michishita: see Col 6 lines 44-47, “The detection control unit 219 functions as a second verification unit and verifies validity (tampering or a change due to aging deterioration) when firmware is to be executed or a file is to be opened”; Col 7 lines 33-42, “The verification unit 221 functions as a first verification unit and verifies programs stored in the ROM 112 when the system-boot by the main controller 110 is performed. Specifically, a signature and a public key, which is used to verify a signature of a program to be started next, are given to each program stored in the ROM 112 in advance, and signature verification is performed right before the programs are started, and the programs are started only when the verification is successful. Such verification of firmware is performed step by step when the system is booted, and firmware is sequentially started”). Motivation to combine Michishita and Kawazu in the instant claim, is the same as that in claims 1, 10, and 11. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Michishita and Kawazu, as applied to claims 1, 8, 10, and 11 above, and further in view of Fujii (U.S.2007/0047454)(hereinafter Fujii). Regarding claim 2, Michishita and Kawazu teach the invention detailed above. However, Michishita and Kawazu do not teach a first notification content of the first notification and a second notification content of the second notification include an intervention technique, and the notification content corresponds to the first notification content and the second notification content. Nevertheless, Fujii-which is in the same field of endeavor- teaches a first notification content of the first notification and a second notification content of the second notification include an intervention technique (Fujii: see FIG. 6A, 6B, 6C; Page 3 paragraph 0048, "The knowledge base, as seen from the specific examples in FIGS. 6A-6C, is a database that stores correspondence between the type of the job having been processed when the error occurred and the transmission destination to which the support information is to be transmitted (FIG. 6A), and correspondence between the type of the error in the job and the content (solution) to be displayed on the device at the transmission destination (FIGS. 6B, 6C)"), and the notification content corresponds to the first notification content and the second notification content (Fujii: see Page 1 paragraph 0014 lines 5-13, "the transmission destination determining step of determining a transmission destination of support information by accessing a storage device storing correspondence between the type of the job and the transmission destination of the support information, based on the information concerning the type of the job obtained in the obtaining step; and the transmitting step of transmitting the support information to the transmission destination determined in the determining step"). Michishita, Kawazu, and Fujii are analogous art because they are from the same field of endeavor. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to utilize Fujii’s condition based notification content with Michishita and Kawazu’s tamper detection system. The suggestion/motivation for doing so would be to provide specific details about the type/location of tampering that has occurred to the user. Regarding claim 3, Michishita, Kawazu, and Fujii teach the first notification content of the first notification differs from a notification content of failed handling (Kawazu: see Col 6 lines 57-67 - Col 7 lines 1-3, "When the execution module is stopped or the system is deactivated by the first alteration detection unit 311, the second alteration detection unit 312, and the error control unit 313, the notification unit 314 notifies the user of the stoppage/deactivation processing. An example of a notification method will be described below. For example, “Module with alteration detection/white list name”, “Detection time”, and “Performed error processing (module stoppage and system deactivation)” are stored in a log file for each event. Data is recorded and stored for each line as a log file in the data storage unit 302. The recorded and stored log file can be transmitted to an external management server and displayed on the operation unit 102, enabling the administrator to confirm the error status"), the second notification content of the second notification is the notification content of failed handling. (Fujii: see FIG. 6A, 6B, 6C "Content of Panel Display"). Motivation to combine Michishita, Kawazu, and Fujii in the instant claim, is the same as that in claim 2. Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Michishita and Kawazu, as applied to claims 1, 8, 10, and 11 above, and further in view of Refstrup (U.S. 9,141,816)(hereinafter Refstrup). Regarding claim 4, Michishita and Kawazu teach the invention detailed above. However, Michishita and Kawazu do not teach the controller is provided on a first substrate, and the printing controller is provided on a second substrate, the second substrate being configured to be replaced. Nevertheless, Refstrup-which is in the same field of endeavor- teaches the controller is provided on a first substrate, and the printing controller is provided on a second substrate, the second substrate being configured to be replaced (Refstrup: see Fig. 1 items 108 and 116; Col 2 lines 32-34, “Printer controller 116 controls the operation of printing system 104 and, as such, receives data and/or control signals from host 102”; Col 3 lines 42-48, “Replaceable printer component 108 includes a memory device 109 that stores information for replaceable printer component 108 and/or printing system 104. Memory device 109 includes a non-volatile memory (NVM) 110 and logic 111. In one embodiment, memory device 109 is tamper proof or tamper resistant. In one embodiment, logic 111 is a logic circuit or embedded software running on a processor”). Michishita, Kawazu, and Refstrup are analogous art because they are from the same field of endeavor. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine Refstrup’s replaceable dual substrate arrangement with Michishita and Kawazu’s tamper detection system. The suggestion/motivation for doing so would be to reduce the attack surface of the system by ensuring that the external controller would not compromise another controller. Regarding claim 9, Michishita, Kawazu, and Refstrup teach the first printing unit includes an ink jet head (Refstrup: see Col 2 lines 16-17, "Printing system 104 includes, for example, an inkjet printer, a laser printer, or other suitable printer"). Motivation to combine Michishita, Kawazu, and Refstrup in the instant claim, is the same as that in claim 4. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Michishita and Kawazu, as applied to claims 1, 8, 10, and 11 above, and further in view of Kageyama et al. (U.S. 4,992,958)(hereinafter Kageyama). Regarding claim 5, Michishita and Kawazu teach first detection processing performed by the first tampering detector (Michishita: see FIG. 2 see item 221; Col 7 lines 33-35, "The verification unit 221 functions as a first verification unit and verifies programs stored in the ROM 112 when the system-boot by the main controller 110 is performed"); and second detection processing performed by the second tampering detector (Michishita: see FIG. 2 item 219; Col 6 lines 44-47, "The detection control unit 219 functions as a second verification unit and verifies validity (tampering or a change due to aging deterioration) when firmware is to be executed or a file is to be opened"; Col 6 lines 60-67, "The detection control unit 219 performs the followings to defend file access. (1) Control of rewriting into files stored in the ROM 112 and the HDD 114. (2) Control of reading of files stored in the ROM 112 and the HDD 114. (3) Control of binary execution in the ROM 112 and the HDD 114. (4) Control of script execution in the ROM 112 and the HDD 114. Details of these will be described later using FIG. 3"). However, Michishita and Kawazu do not teach processing performed in parallel. Nevertheless, Kageyama-which is in the same field of endeavor- teaches processing performed in parallel (Kageyama: see Col 9 lines 28-33, "As illustrated in FIG. 9, since the command reception, page buffers 1 to 3, the laser control of the printer and the paper control are performed in a parallel mode, no empty time is produced in use of the printer and page buffer and the printer engine can be operated at the maximum speed"). Michishita, Kawazu, and Kageyama are analogous art because they are from the same field of endeavor. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to utilize Kageyama’s parallel processing with the tampering detection methods of Michishita and Kawazu. The suggestion/motivation for doing so would be to improve the efficiency of the detection system by decreasing the amount of time that it takes to detect tampering. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Michishita and Kawazu, as applied to claims 1, 8, 10, and 11 above, and further in view of Goda (U.S. 11,379, 589)(hereinafter Goda). Regarding claim 6, Michishita and Kawazu teach at least one of the first tampering detector detects the tampering of the first program or the second tampering detector detects the tampering of the second program, or each of the first tampering detector detects the tampering of the first program and the second tampering detector detects the tampering of the second program (Michishita: see Col 7 lines 33-35, "The verification unit 221 functions as a first verification unit and verifies programs stored in the ROM 112 when the system-boot by the main controller 110 is performed"; Col 6 lines 44-47, "The detection control unit 219 functions as a second verification unit and verifies validity (tampering or a change due to aging deterioration) when firmware is to be executed or a file is to be opened"). However, Michishita and Kawazu do not teach a recovery mode transition unit that transitions to a recovery mode after restarting when a predetermined first condition is fulfilled. Nevertheless, Goda-which is in the same field of endeavor- teaches a recovery mode transition unit that transitions to a recovery mode after restarting when a predetermined first condition is fulfilled (Goda: see Col 7 lines 12-16"...in step S402, it is determined that the boot program 310 has been altered, and the process proceeds to step S405. In step S405, the CPU 201 performs an error notification. For example, processing for causing the LED 214 to blink to warn a user is performed, and the process is terminated"). Michishita, Kawazu, and Goda are analogous art because they are from the same field of endeavor. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to utilize Goda’s recovery method with Michishita and Kawazu’s tamper detection method. The suggestion/motivation for doing so would be to protect the system by ensuring that the system returns to a safe state when a failure or tampering event is detected. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Michishita and Kawazu, as applied to claims 1, 8, 10, and 11 above, and further in view of Spath et al. (U.S. 10,140,454)(hereinafter Spath). Regarding claim 7, Michishita and Kawazu teach one of the first tampering detector detects the tampering of the first program or the second tampering detector detects the tampering of the second program or each of the first tampering detector detects the tampering of the first program and the second tampering detector detects the tampering of the second program (Michishita: see Col 7 lines 33-35, "The verification unit 221 functions as a first verification unit and verifies programs stored in the ROM 112 when the system-boot by the main controller 110 is performed"; Col 6 lines 44-47, "The detection control unit 219 functions as a second verification unit and verifies validity (tampering or a change due to aging deterioration) when firmware is to be executed or a file is to be opened"). However, Michishita and Kawazu do not teach a tampering event controller that transitions to processing other than processing of transitioning to a recovery mode after restarting when tampering is detected. Nevertheless, Spath-which is in the same field of endeavor- teaches a tampering event controller that transitions to processing other than processing of transitioning to a recovery mode after restarting when tampering is detected (Spath: see Col 1, lines 44-60 "In one example, a computer-implemented method for restarting computing devices into security-application-configured safe modes may include (1) configuring a security application to recognize a predetermined signal received via a predetermined hardware device that indicates that a user wants to restart the computing device into a security-application-configured safe mode that prevents suspicious applications from loading, (2) detecting the predetermined signal via an instance of the predetermined hardware device that is connected to the computing device, (3) setting, in response to detecting the predetermined signal, a registry key on the computing device that will instruct the computing device to boot into the security-application-configured safe mode during a restart sequence, and (4) restarting the computing device in the security-application-configured safe mode in response to detecting the registry key during the restart sequence"). Michishita, Kawazu, and Spath are analogous art because they are from the same field of endeavor. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to utilize Spath’s fail-safe method in response to detecting tampering with Michishita and Kawazu’s tampering detection system. The suggestion/motivation for doing so would be to isolate potential malware or tampering and allow the system to be placed into a safe operating state. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KELAH JANAE MCFARLAND-BARNES whose telephone number is (571)272-5953. The examiner can normally be reached Monday through Friday 8:00am until 4:00pm Central Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn D Feild can be reached at 571-272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KELAH JANAE MCFARLAND-BARNES/Examiner, Art Unit 2431 /MICHAEL R VAUGHAN/Primary Examiner, Art Unit 2431
Read full office action

Prosecution Timeline

Mar 13, 2023
Application Filed
Jul 07, 2025
Non-Final Rejection — §103
Oct 09, 2025
Response Filed
Dec 20, 2025
Final Rejection — §103
Mar 27, 2026
Request for Continued Examination
Apr 07, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12579256
LARGE LANGUAGE MODEL (LLM) SUPPLY CHAIN SECURITY
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 12m
Median Time to Grant
Moderate
PTA Risk
Based on 2 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in for Full Analysis

Enter your email to receive a magic link. No password needed.

Free tier: 3 strategy analyses per month