DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Publication No. 20130161749) in view of Avery et al (US Patent No. 6501632).
Regarding claim 1, Kim teaches an ESD protection circuit (i.e., ESD protection circuit 506) (fig. 7), connected in parallel with a protected circuit (i.e., any ESD protection circuit to be clamped to terminals PL41, BL41, respectively) operating at a predetermined operating voltage (i.e., predetermined operating voltage power source) between a first terminal (i.e., first terminal PL41) and a second terminal (i.e., second terminal BL41), wherein the ESD protection circuit comprises: an NMOS transistor (i.e., NMOS transistor N42) , in which at least a drain (i.e., drain CL42/PL41) is connected to the first terminal and a source (i.e., source CL42/BL41) is connected to the second terminal, a gate (i.e., gate CL42/PL41) of the NMOS transistor is connected to the first terminal (implicit, as seen in fig. 7).
Kim does not teach and a resistive element is connected between the first terminal and the gate of the NMOS transistor, wherein a threshold voltage and a trigger voltage of a parasitic bipolar transistor of the NMOS transistor are higher than the operating voltage and lower than a breakdown voltage of the protected circuit and a gate insulating film.
Avery teaches in a similar field of endeavor in ESD protection circuits (i.e., ESD circuit 300) (fig. 3); wherein a resistive element (i.e., resistive element Rz1) is connected between the first terminal and the gate of the NMOS transistor (implicit, as seen in fig. 3), wherein a threshold voltage (i.e., threshold voltage; Col. 3 lines 8+) and a trigger voltage (i.e., trigger voltage; Col. 3 lines 8+) of a parasitic bipolar transistor (i.e., parasitic bipolar transistor NPN) of the NMOS transistor are higher (i.e., voltage to rise quickly; Col. 3 lines 8+) than the operating voltage (i.e., the operating voltage PAD) and lower than (i.e., less than the breakdown voltage of Zener diode Z3; Col. 3 lines 8+) a breakdown voltage (i.e., breakdown voltage; Col. 3 lines 8+) of the protected circuit and a gate insulating film (i.e., the high voltage p-well 406 acts as the gate insulating film; fig. 4) (e.g., FIG. 4 shows a high voltage n-well 402 into which the high voltage p-well 406 is implanted electrically isolating the p-well in which Q.sub.1 is formed from the p-substrate 400. This allows for more precise control of the triggering of transistor Q.sub.1 ' than would be possible if the HVPW 406 was directly diffused into the p-substrate 400; Col. 4 lines 38+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally clamped the resistive element to the gate of the NMOS device in Kim, as taught by Avery, as it provides the advantage of optimizing the circuit design.
Regarding claim 4, Kim in view of Avery and the teachings of Kim as modified by Avery have been discussed above.
Avery further teaches the ESD protection circuit of claim 1; wherein a diode (i.e., diode Z2; fig. 3) having an avalanche breakdown voltage higher than the operating voltage (i.e., avalanche breakdown voltage higher than the operating voltage; Col. 3 lines 8+) is connected between the second terminal (i.e., the second terminal 304/GND) and the gate of the NMOS transistor (i.e., the gate of the NMOS transistor 308).
Regarding claim 13, Kim in view of Avery and the teachings of Kim as modified by Avery have been discussed above.
Kim further teaches the ESD protection circuit of claim 1; a semiconductor device (i.e., semiconductor device 500; fig. 7) and a protected circuit (i.e., any ESD protection circuit to be clamped to terminals PL41, BL41, respectively) protected from electrostatic discharge by the ESD protection circuit (i.e., the ESD protection circuit 506) are connected in parallel (implicit, as seen in fig. 7).
Allowable Subject Matter
Claims 6-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Kim in view of Avery teaches the invention set forth above. However, neither Kim nor Avery particularly teaches wherein the NMOS transistor comprises: a semiconductor substrate; a P type well region, formed on a surface side of the semiconductor substrate; an N type high concentration drain region and an N type high concentration source region, provided spaced apart over an upper part of the P type well region and having a higher impurity concentration than an impurity concentration of the P type well region; a P type intermediate concentration region, provided in a region in contact with at least the N-type high concentration drain region and having a higher P type impurity concentration than the impurity concentration of the P type well region; a gate insulating film, provided on a semiconductor surface between the N type high concentration drain region and the N type high concentration source region; and a gate electrode, provided on the gate insulating film.
Hence claim 6 will be deemed allowable if rewritten in an independent form.
Claims 7-12 depend on objected claim 6, consequently claims 7-12 will also be deemed allowable.
Claims 2-3 and 5 are cancelled.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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