Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/24/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102a as being anticipated by SUGIMOTO YOHEI (JP 2020177126 A)
Regarding Claim 1,
SUGIMOTO YOHEI discloses (Fig. 5 and pasted below) forming a recessed portion (see pasted figure below CNT2) at an insulating member (11c); forming a first capacitance electrode (16a), a capacitance insulation film (16b), and a second capacitance electrode (16c) along the recessed portion (where CNT2 is pointing to); concurrently patterning the first capacitance electrode (16a), the capacitance insulation film (16b), and the second capacitance electrode (16c); removing a portion of the second capacitance electrode (16c); forming an interlayer insulating film (12); and etching, at a region where the portion of the second capacitance electrode (16c) is removed (shown in figure below), the interlayer insulating film (12) and the capacitance insulation film (16b) concurrently, until a portion of the first capacitance electrode (16a) is exposed in plan view to form the first contact hole (CNT4a) penetrating through the interlayer insulating film (12) and the capacitance insulation film (16b).
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[AltContent: textbox (Etching at a region where the second capacitance 16c is removed, the interlayer insulating film (12) and capacitance insulation film (16b) concurrently over here. And this is where a portion of the first capacitance electrode (16a) is exposed.)][AltContent: textbox (Recessed portion)][AltContent: arrow]
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Regarding Claim 2,
SUGIMOTO YOHEI discloses (Fig. 5) wherein the capacitance insulation film (16b) contains silicon nitride (“...A dielectric layer 16b is provided on the capacitance lower electrode 16a by covering the capacitance lower electrode 16a. The dielectric layer 16b is provided using a dielectric material. Examples of the dielectric material include hafnium oxide, aluminum oxide, silicon oxide, silicon nitride, tantalum oxide and the like, and these films are used as a single layer or in combination. In this embodiment, silicon nitride is used as the dielectric material of the dielectric layer 16b. The film thickness of the dielectric layer 16b is not particularly limited, but is, for example, about 20 nm…”)
Regarding Claim 3,
SUGIMOTO YOHEI discloses (Fig. 5) wherein in the formation of the first contact hole (CNT4a), a second contact hole (CNT4b) configured to electrically couple the second capacitance electrode (16c) and a capacitance line (8,9a) is concurrently formed.
Regarding Claim 4,
SUGIMOTO YOHEI discloses (Fig. 5) wherein the recessed portion (CNT2) extends along a first direction at a position overlapping a semiconductor layer (30a) of a transistor extending along the first direction.
Regarding Claim 5,
SUGIMOTO YOHEI discloses (Fig. 5) the method comprising, after the formation of the interlayer insulating film (11c), forming a light shielding film (5), and forming the transistor at a position (30) overlapping the light shielding film in plan view, wherein before forming a gate electrode of the transistor, the first contact hole (CNT4a) is formed.
Regarding Claim 6,
SUGIMOTO YOHEI discloses (Fig. 5) concurrently with the formation of the gate electrode (30g), a source drain electrode is formed, so as to be in contact with the first capacitance electrode (16a) through the first contact hole (CNT4a).
Regarding Claim 7,
SUGIMOTO YOHEI discloses (Fig. 5) A method of manufacturing an electro-optical device, comprising: forming a recessed portion (CNT2) at an insulating member (11c); forming a first capacitance electrode (16a), a capacitance insulation film (16b), and a second capacitance electrode(16c) along the recessed portion (CNT2); concurrently patterning the first capacitance electrode (16a), the capacitance insulation film (16b), and the second capacitance electrode (16c); removing a portion of the second capacitance electrode (16c) forming an interlayer insulating film (12) so as to cover the light shielding film (5); forming a transistor (30) at a position overlapping the light shielding film (5) in plan view, and before forming a gate electrode (30g) of the transistor, etching, until a portion of the first capacitance electrode (16a) is exposed in plan view, a region where the portion of the second capacitance electrode (16c) is removed, to form a first contact hole (CNT4a) penetrating through the interlayer insulating film (12) and the capacitance insulation film (16b).
Regarding Claim 8,
SUGIMOTO YOHEI discloses (Fig. 5) wherein in the formation of the first contact hole (CNT4a), etching, until a portion of a semiconductor layer (30a) of the transistor (30) is exposed in plan view, and concurrently with the formation of the gate electrode (30g), a source drain electrode (6) is formed, as to be in contact with the portion of the semiconductor layer (30a) through the first contact hole (CNT4a).
Regarding Claim 9,
SUGIMOTO YOHEI discloses (Fig. 5) wherein in the formation of the first capacitance electrode (16a), the capacitance insulation film (16b), and the second capacitance electrode (16c), the first capacitance electrode (16a), the capacitance insulation film (16b), and the second capacitance electrode (16c) are formed so as to completely cover a side surface of the recessed portion (CNT2) and a bottom surface of the recessed portion (CNT2).
Conclusion
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/LUCY P CHIEN/Primary Examiner, Art Unit 2871