Prosecution Insights
Last updated: August 17, 2026
Application No. 18/184,111

POWER CONVERSION CIRCUIT WITH CURRENT LIMITED CLAMP

Non-Final OA §102§103
Filed
Mar 15, 2023
Priority
Mar 15, 2022 — provisional 63/320,170
Examiner
TRAN, NGUYEN
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Non-Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
912 granted / 1092 resolved
+15.5% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
32 currently pending
Career history
1130
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
55.1%
+15.1% vs TC avg
§102
29.3%
-10.7% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1092 resolved cases

Office Action

§102 §103
CTNF 18/184,111 CTNF 82560 DETAILED ACTION 1. This action is in response to the RCE filed on 5/4/26. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 AIA 3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/4/26 has been entered. Response to Arguments 4. Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA 6. Claim s 1, 6-7, 10, and 12 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lin et al. (US 9991775) . Regarding claim 1 : Lin et al. disclose (i.e. figure 4) an apparatus, comprising: a power conversion circuit (i.e. 100) having a power output (i.e. at Vout) , the power conversion circuit including: an amplifier circuit (i.e. 142) having a first input, a second input, and an output, the first input of the amplifier circuit (i.e. 142) coupled (i.e. electrically coupled) to the power output (i.e. at Vout) , the second input coupled (i.e. electrically coupled) to a reference input (i.e. for VN) ; a comparator (i.e. 148) having a first input, a second input, and an output, the first input of the comparator (i.e. 148) coupled (i.e. electrically coupled) to the output of the amplifier circuit (i.e. 142) to receive an input signal (i.e. output of 142) from the amplifier circuit (i.e. 142) ; a circuit (i.e. circuit excluding 142, 148) having inputs and outputs, at least some of the inputs coupled (i.e. electrically coupled) to the comparator (i.e. 148) , the outputs of the circuit (i.e. circuit excluding 142, 148) coupled (i.e. electrically coupled) to the first and second inputs of the comparator (i.e. 148) , the circuit (i.e. circuit excluding 142, 148) configurable to, in a first mode (i.e. first mode when switch 146 is open) , set a voltage difference across the first and second inputs (i.e. +/- inputs of 148) of the comparator (i.e. 148) to a value (i.e. value from 148) , and in a second mode (i.e. second mode when switch 146 is close) , set the voltage difference across the first and second inputs (i.e. +/- inputs of 148) of the comparator (i.e. 148) responsive to a state (i.e. state of 148 to 147) of the comparator (i.e. 148) ; and a controller (i.e. controller of figure 4) configured to cause the circuit (i.e. circuit excluding 142, 148) to operate in the first mode (i.e. first mode when switch 146 is open) or in the second mode (i.e. second mode when switch 146 is close) (i.e. see Col. 6 through 7) . Regarding claim 6 : (i.e. figure 4) wherein the power conversion circuit includes a capacitor (i.e. 144) coupled (i.e. electrically coupled) at the first input of the comparator. Regarding claim 7 : (i.e. figure 4) wherein the power conversion circuit includes a power stage (i.e. 112) and a driver circuit (i.e. 116) coupled between the output of the comparator (i.e. 148) and the power stage (i.e. 112) . Regarding claim 10 : Lin et al. disclose an apparatus (i.e. figure 4) comprising: a transconductance amplifier circuit (i.e. 142) having an output and configurable to provide a first output current (i.e. Igm) at its output based on a difference between a first voltage (i.e. Vp) and a second voltage (i.e. Vn) ; a current limiting circuit (i.e. 145, 144) having an output and configurable to provide a second output current (i.e. the difference of the current I1 and Igm) at its output that is an input current limited to no greater than the first output current (i.e. Igm) ; a comparator (i.e. 148) having an input coupled (i.e. electrically coupled) to the output of the transconductance amplifier circuit (i.e. 142) to receive an input signal (i.e. signal to 148) from the transconductance amplifier circuit (i.e. 142) ; a switch (i.e. 146) coupled (i.e. electrically coupled) between the input of the comparator (i.e. 148) and the output of the current limiting circuit (i.e. 145, 144) ; and a controller configurable to control the switch (i.e. see Col. 6 through 7) . Regarding claim 12 : (i.e. figure 4) wherein the comparator (i.e. 148) is configurable to provide an output voltage (i.e. from 148) to a driver circuit (i.e. 116) responsive to the second output current (i.e. the difference of the current I1 and Igm) (i.e. see Col. 6 through 7) . Claim Rejections - 35 USC § 103 07-20-aia AIA 7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 8. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9991775) in view of Chen (US 20160079858). Regarding claim 2 : Lin et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the amplifier circuit is a transconductance amplifier circuit and comprises: a first transistor coupled between a first voltage terminal and a second voltage terminal, and having a first control terminal coupled to the first input; a second transistor coupled between the first transistor and the second voltage terminal, and having a second control terminal coupled to the second input; a third transistor coupled in parallel with the first transistor, and having a third control terminal; and a fourth transistor coupled between the first voltage terminal and the output of the transconductance amplifier circuit, and having a fourth control terminal coupled to the third control terminal. Chen discloses a power supply comprising the amplifier circuit (i.e. figure 2) is a transconductance amplifier circuit and comprises: a first transistor (i.e. M1) coupled (i.e. electrically coupled) between a first voltage terminal and a second voltage terminal (i.e. first and second terminals of figure 2) , and having a first control terminal (i.e. terminal for Vrefn) coupled (i.e. electrically coupled) to the first input; a second transistor (i.e. M3) coupled (i.e. electrically coupled) between the first transistor and the second voltage terminal, and having a second control terminal (i.e. control terminal of M3) coupled (i.e. electrically coupled) to the second input; a third transistor (i.e. M2) coupled (i.e. electrically coupled) in parallel with the first transistor (i.e. M1) , and having a third control terminal (i.e. terminal for Vfbn) ; and a fourth transistor (i.e. M4) coupled (i.e. electrically coupled) between the first voltage terminal and the output of the transconductance amplifier circuit (i.e. circuit of figure 2) , and having a fourth control terminal (i.e. control terminal of M4) coupled (i.e. electrically coupled) to the third control terminal. Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lin et al.’s invention with the power supply as disclose by Chen to provide a better control performance. 07-21-aia AIA 9. Claim s 9, 11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9991775) in view of Thiele et al. (US 20200099299) . Regarding claim 9 : Lin et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the power conversion circuit is in an integrated circuit package. Thiele et al. disclose (i.e. figures 1-4) the power conversion circuit is in an integrated circuit package (i.e. IC of 102) . Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lin et al.’s invention with the power supply as disclose by Thiele et al., because it is desirable to prevent the regulation voltage from exceeding a current limit clamp voltage; and when the DC-to-DC voltage converter is in a skip mode, it is desirable to prevent the regulation voltage from falling below a skip clamp voltage. Regarding claim 11 : Lin et al. disclose the transconductance amplifier circuit is a first transconductance amplifier circuit, but does not specifically disclose, comprises a second transconductance amplifier circuit configurable to provide the input current based on a differential between a third voltage and a fourth voltage. Thiele et al. disclose a power supply (i.e. figure 1) comprising comprises a second transconductance amplifier circuit (i.e. 200) configurable to provide the input current (i.e. current to the circuit includes 188,152,126,266) based on a differential between a third voltage (i.e. 216) and a fourth voltage (i.e. 202) . Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lin et al.’s invention with the power supply as disclose by Thiele et al., because it is desirable to prevent the regulation voltage from exceeding a current limit clamp voltage; and when the DC-to-DC voltage converter is in a skip mode, it is desirable to prevent the regulation voltage from falling below a skip clamp voltage. Regarding claim 13 : Lin et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose an integrator circuit coupled to the transconductance amplifier circuit and configurable to provide a third output current based on a reference voltage and a feedback voltage. Thiele et al. disclose a power supply (i.e. figure 1) comprising an integrator circuit (i.e. 126, 226) coupled to the transconductance amplifier circuit (i.e. 140) and configurable to provide a third output current (i.e. from 126 or 226) based on a reference voltage (i.e. 149) and a feedback voltage (i.e. from 138) . Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lin et al.’s invention with the power supply as disclose by Thiele et al., because it is desirable to prevent the regulation voltage from exceeding a current limit clamp voltage; and when the DC-to-DC voltage converter is in a skip mode, it is desirable to prevent the regulation voltage from falling below a skip clamp voltage. Regarding claim 14 : Lin et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the controller is configurable to enable the switch during a time period where the power conversion circuit transitions between an active mode and a skip mode. Thiele et al. disclose a power supply (i.e. figure 1) comprising the controller is configurable to enable the switch during a time period (i.e. switching time period of 100) where the power conversion circuit transitions between an active mode (i.e. normal or current limit condition) and a skip mode (i.e. skip mode) (i.e. ¶14) . Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lin et al.’s invention with the power supply as disclose by Thiele et al., because it is desirable to prevent the regulation voltage from exceeding a current limit clamp voltage; and when the DC-to-DC voltage converter is in a skip mode, it is desirable to prevent the regulation voltage from falling below a skip clamp voltage. Regarding claim 15 : Lin et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the transconductance amplifier circuit, the current limiting circuit, the comparator, the switch, and the controller are part of a power conversion circuit in an integrated circuit package. Thiele et al. disclose a power supply (i.e. figure 1) comprising the transconductance amplifier circuit (i.e. 200) , the current limiting circuit (i.e. 126) , the comparator (i.e. 162) , the switch and the controller (i.e. controller of 102) are part of a power conversion circuit in an integrated circuit package (i.e. IC of 102) . Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Lin et al.’s invention with the power supply as disclose by Thiele et al., because it is desirable to prevent the regulation voltage from exceeding a current limit clamp voltage; and when the DC-to-DC voltage converter is in a skip mode, it is desirable to prevent the regulation voltage from falling below a skip clamp voltage . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 10. Claim s 16 and 18-20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding to claim 16, the prior art fails to disclose a current limiting circuit having a third input coupled to a current source terminal, a fourth input coupled to the first output via a first switch, and a second output coupled to a reference current circuit terminal via a second switch, the current limiting circuit configured to provide a second output current at the second output that is an input current at the third input limited to no greater than the first output current. 12-151-08 AIA 07-43 12-51-08 11. Claim s 3-5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nguyen Tran/Primary Examiner, Art Unit 2838 Application/Control Number: 18/184,111 Page 2 Art Unit: 2838 Application/Control Number: 18/184,111 Page 3 Art Unit: 2838 Application/Control Number: 18/184,111 Page 4 Art Unit: 2838 Application/Control Number: 18/184,111 Page 5 Art Unit: 2838 Application/Control Number: 18/184,111 Page 6 Art Unit: 2838 Application/Control Number: 18/184,111 Page 7 Art Unit: 2838 Application/Control Number: 18/184,111 Page 8 Art Unit: 2838 Application/Control Number: 18/184,111 Page 9 Art Unit: 2838
Read full office action

Prosecution Timeline

Mar 15, 2023
Application Filed
Jun 18, 2025
Non-Final Rejection mailed — §102, §103
Nov 18, 2025
Response Filed
Jan 02, 2026
Final Rejection mailed — §102, §103
May 04, 2026
Request for Continued Examination
May 06, 2026
Response after Non-Final Action
Jun 03, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
91%
With Interview (+7.7%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1092 resolved cases by this examiner. Grant probability derived from career allowance rate.

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