DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Yu-Hsin, et al. "Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks." IEEE journal of solid-state circuits 52.1 (2016)(“Chen”) in view of Falcon et al. US 2016/0026912 Al(“Falcon”) and in view of Brothers et al. US 11,244,225 B2(“Brothers”).
Chen teaches an integrated circuit (IC) chip comprising:
a plurality of processing units to collectively perform a matrix multiplication operation with matrix data by performing matrix processing at least partially in parallel, each processing unit of the plurality of processing units to execute an instruction to process a portion of the matrix data to perform a corresponding partial matrix operation(Chen, pgs. 2-4, see also fig. 2 and 4, “Given the shape parameters in Table I, the computation
of a layer is defined as
O
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…where O, I, W, and B are the matrices of the ofmaps, ifmaps, filters, and biases, respectively[to collectively perform a matrix multiplication operation with matrix data]… [f]ig. 2 shows the top-level architecture and memory hierarchy of the Eyeriss system… [t]he core clock domain consists of a spatial array of 168 PEs organized as a 12 × 14 rectangle[a plurality of processing units]… each PE can either communicate with its neighbor PEs… A 2-D convolution is composed of many 1-D convolution primitives, and its computation:1) shares the same row of filter or ifmap across primitives and 2) accumulates the psums from multiple primitives together. Therefore, a PE Set, as shown in Fig. 4, is grouped to run a 2-D convolution… [i]n a set, each row of filter is reused horizontally, each row of ifmap is reused diagonally, and rows of psum are accumulated vertically[by performing matrix processing at least partially in parallel, each processing unit of the plurality of processing units to execute an instruction to process a portion of the matrix data to perform a corresponding partial matrix operation].”);
a plurality of memories, each memory to store the portion of the matrix data to be processed by a corresponding processing unit of the plurality of processing units(Chen, pgs. 6-7, see also figs. 2 and 13, “The Eyeriss accelerator has a GLB of 108 kB that can communicate with DRAM[a plurality of memories] through the asynchronous interface and with the PE array through the NoC. The GLB stores all the three types of data: ifmaps, filters, and psums/ofmaps[each memory to store the portion of the matrix data to be processed by a corresponding processing unit of the plurality of processing units].”);
a plurality of interconnects, a subset of the plurality of interconnects to couple each processing unit of the plurality of processing units to a plurality of neighboring processing units, at least one of the processing units to send partial matrix data to a first neighboring processing unit and to receive partial matrix data from a second neighboring processing unit over corresponding interconnects of the plurality of interconnects(Chen, pgs. 7-8, see also figs. 4, 5, 10, and 11, “The NoC manages data delivery between the GLB and the PE array as well as between different PEs[a plurality of interconnects, a subset of the plurality of interconnects to couple each processing unit of the plurality of processing units to a plurality of neighboring processing units]. The NoC architecture needs to meet the following goals. First, the NoC has to support the data delivery patterns used in the RS dataflow. While the data movement within a PE set is uniform (Fig. 4)[ at least one of the processing units to send partial matrix data to a first neighboring processing unit and to receive partial matrix data from a second neighboring processing unit over corresponding interconnects of the plurality of interconnects], there are three scenarios in the mapping of real CNNs that can break the uniformity and should be taken care of: 1) different convolution strides (U) result in the ifmap delivery, skipping certain rows in the array (AlexNet CONV1 in Fig. 5); 2) a set is divided into segments that are mapped onto different parts of the PE array (AlexNet CONV2 in Fig. 5); and 3) multiple sets are mapped onto the array simultaneously and different data is required for each set (AlexNet CONV4 and CONV5 in Fig. 5).”);
a first controller, wherein responsive to the first controller, the plurality of processing units are to collectively execute the matrix multiplication operation in accordance with at least one matrix multiplication command or instruction specifying a first input matrix, A, and a second input matrix, B, the plurality of processing units to produce an output matrix, C, by multiplying the first input matrix, A, and the second input matrix, B(Chen, pgs. 2-4, see also fig. 2 and 4, “Given the shape parameters in Table I, the computation of a layer is defined as
O
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…where O[the plurality of processing units to produce an output matrix, C, by multiplying the first input matrix, A, and the second input matrix, B], I[specifying a first input matrix, A,], W[and a second input matrix, B,], and B are the matrices of the ofmaps, ifmaps, filters, and biases, respectively…[t]he accelerator has two levels of control hierarchy. The top-level control coordinates: 1) traffic between the off-chip DRAM and the GLB through the asynchronous interface; 2) traffic between the GLB and the PE array through the NoC; and 3) operation of the RLC CODEC and ReLU module[a first controller]…[t]he accelerator runs the processing of a CNN layer-by-layer. For each layer, it first loads the configuration bits into a 1794 b scan chain serially to reconfigure the entire accelerator, which takes less than 100 μs. These bits configure the accelerator for the processing of filters and fmaps in a certain shape, which includes setting up the PE array computation mappings[wherein responsive to the first controller, the plurality of processing units are to collectively execute the matrix multiplication operation in accordance with at least one matrix multiplication command or instruction]…and NoC data delivery patterns…[t]hey are generated offline and are statically accessed at runtime.”);
and a plurality of second controllers, each second controller associated with a processing unit of the plurality of processing units, the second controller to retrieve the portion of the matrix data to be processed by a corresponding processing unit of the plurality of processing units from a system memory and to store the portion of the matrix data to a corresponding memory of the plurality of memories(Chen, pgs. 7-8, see also figs. 10,11 and 12, “[W]e implemented the GIN, as shown in Fig. 10, with two levels of hierarchy: Y-bus and X-bus. A vertical Y-bus consists of 12 horizontal X-buses, one at each row of the PE array, and each X-bus connects to 14 PEs in the row. Each X-bus has a row ID, and each PE
has a col ID…[e]ach data read from the GLB is augmented with a (row, col) tag by the top-level controller…[t]he tag-ID matching is done using the Multicast Controller (MC). There are 12 MCs on the Y-bus to compare the row tag with the row ID of each X-bus, and 14 MCs on each of the X-buses[and a plurality of second controllers, each second controller associated with a processing unit of the plurality of processing units,] to compare the col tag with the col ID of each PE… Eyeriss has separate GINs for each of the three data types (filter, ifmap, and psum) to provide sufficient bandwidth from the GLB to the PE array[the second controller to retrieve the portion of the matrix data to be processed by a corresponding processing unit of the plurality of processing units from a system memory and to store the portion of the matrix data to a corresponding memory of the plurality of memories]. All GINs have 4-b row IDs to address the 12 rows. The filter and psum GINs use 4-b col IDs to address the 14 columns, while ifmap GIN uses 5 b to support maximum 32 ifmap rows passing in diagonal. The filter and psum GINs have data bus width of 64 b (4b×16 b), while the ifmap GIN has the data bus width of 16 b.”).
While Chen teaches the output matrix C, Chen does not teach: and matrix-wide operation circuitry to perform a matrix-wide operation the matrix-wide operation comprising a max value operation, a min value operation, a sum operation, or a max absolute value operation.
However, Falcon teaches:
and matrix-wide operation circuitry to perform a matrix-wide operation [on the output matrix, C,] the matrix-wide operation comprising a max value operation, a min value operation, a sum operation, or a max absolute value operation(Falcon, para. 0080, see also fig. 9, “Pooling layer 904 may perform subsampling to reduce images 910 to a stack of
reduced images 914. Subsampling operations may be achieved through…maximum value computation[and matrix-wide operation circuitry to perform a matrix-wide operation, the matrix-wide operation comprising a max value operation].”).1, 2
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the teachings of Falcon the motivation to do so would be to incorporate reconfigurable logic for shifting and/or scaling cnn kernels to make certain computations such as pooling work(Falcon, para. 0082, “Moreover, embodiments of the present disclosure may include weight-shifting mechanisms for such circuits…such weight-shifting mechanisms may be used to shift low-precision weights up and, after results are determined, scale the results back to original precision. The reconfigurable aspects of the calculation circuits may include the precision of the computation and/or the manner of the computation…[this] include[s] modular, reconfigurable, and variable-precision calculation circuits to perform different layers of CNN.”).
Chen in view of Falcon do not teach: a plurality of pre-multiplication arithmetic engines, each pre-multiplication arithmetic engine positioned in a datapath preceding a multiplication unit within a corresponding processing unit, and each pre-multiplication arithmetic engine to perform a pre-multiplication addition operation with a corresponding portion of the matrix data to generate a new corresponding portion of the matrix data to be used for the matrix multiplication operation.
However, Brothers teaches:
a plurality of pre-multiplication arithmetic engines, each pre-multiplication arithmetic engine positioned in a datapath preceding a multiplication unit within a corresponding processing unit, and each pre-multiplication arithmetic engine to perform a pre-multiplication addition operation with a corresponding portion of the matrix data to generate a new corresponding portion of the matrix data to be used for the matrix multiplication operation(Brothers, cols. 16-20, see also figs. 7, 9 and 11, “FIG. 7 is a block diagram illustrating an example matrix multiply unit (MMU)[within a corresponding processing unit] 700…data storage unit 702 provides input feature map data to aligner/converters 710, 712[a plurality of pre-multiplication arithmetic engines]. The provided portions of the input feature map are vertically aligned based on the current (x, y) location and the y-offset associated with weights of the current matrix. Aligner/converters 710, 712 horizontally align the received portions of the input feature map and, in some embodiments, perform numerical format conversion. For example, aligner/converters 710, 712 may convert numbers from a linear format to a log or LNS format… [f]ig. 11 illustrates operation of an MMU as described with reference to FIG. 7…of this disclosure… [b]uffers 1104, 1106 pass their data to respective circuit blocks 1108, 1110[each pre-multiplication arithmetic engine] to horizontally align the data (using the x_offsets for the corresponding weights
w
0
,
w
1
) [and each pre-multiplication arithmetic engine to perform a pre-multiplication addition operation with a corresponding portion of the matrix data to generate a new corresponding portion of the matrix data to be used for the matrix multiplication operation ]and, in some embodiments, performs floating point format to fixed point conversion. The vertically and horizontally aligned data of circuit blocks 1108, 1110 are passed to the circuit blocks 1112, 1114… where linear numbers are used, the adders 1118, 1124 may be replaced with multipliers [positioned in a datapath preceding a multiplication unit].”).3
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen in view of Falcon with the teachings of Brothers the motivation to do so would be to implement a neural network processor that uses macro based instructions rather than calling a plurality of lower level instructions to efficiently execute various types of neural network operations(Brothers, col. 3, “A macro instruction, when executed by the NN processor, causes one or more of the processing units within the NN processor to perform a macro operation. A macro operation, for example, is a
plurality of lower level operations performed by one or more processing units of the NN processor over multiple clock cycles. A macro instruction can correspond to an instruction
that implements a category or portion of neural network processing. By executing a single macro instruction, the NN processor is capable of implementing complex operations that may occur over many cycles.”).
Regarding claim 2, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein the max value operation comprises a max pooling operation(Falcon, para. 0080, see also fig. 9, “Pooling layer 904 may perform subsampling to reduce images 910 to a stack of
reduced images 914. Subsampling operations may be achieved through…maximum value computation.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Falcon for the same rationale stated at Claim 1.
Regarding claim 3, Chen in view of Falcon and DiCecco teaches the IC chip of claim 2, wherein the matrix-wide operation is to process data among elements of the output matrix, C(Chen, pgs. 2-4, see also figs.1, 2 and 4, “Given the shape parameters in Table I, the computation of a layer is defined as
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…where O, I, W, and B are the matrices of the ofmaps, ifmaps, filters, and biases, respectively.”).
Regarding claim 4, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein the matrix-wide operation is to process data among elements of the output matrix, C(Chen, pgs. 2-4, see also figs.1, 2 and 4, “Given the shape parameters in Table I, the computation of a layer is defined as
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…where O, I, W, and B are the matrices of the ofmaps, ifmaps, filters, and biases, respectively.”).
Regarding claim 5, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein each pre-multiplication arithmetic engine of the plurality of pre-multiplication arithmetic engines is associated with one of the processing units of the plurality of processing units(Falcon, paras. 0087-0094, see also figs. 11 and 12, “When calculation circuits 1118 work collaboratively, they may achieve a convolution layer, or a pooling layer, or a fully-connected layer of a CNN system… FIG. 12 illustrates an example embodiment of a calculation circuit 1200 that may be used to implement fully or in part calculation circuit 1118… calculation circuit 1200 may include a 16-bit arithmetic left shifter 1240 to scale up inputs for computations of calculation circuit 1200…calculation circuit 1200 may include a right shifter and truncate logic 1232 to scale down resulting calculations of calculation circuit 1200.”).4
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Falcon for the same rationale stated at Claim 1.
Regarding claim 6, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein the first controller comprises a microprocessor(Chen, pg., 9, As fig. 14 details below:
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The XilinxVC707 [a microprocessor] interfaces with the Eyeriss accelerator chip and acts as the first controller).
Regarding claim 7, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein the processing units comprise processing clusters(Chen, pgs. 2-4, see also fig. 2 and 4, “Fig. 2 shows the top-level architecture and memory hierarchy of the Eyeriss system… [t]he core clock domain consists of a spatial array of 168 PEs organized as a 12 × 14 rectangle… each PE can either communicate with its neighbor PEs or the GLB through an NoC, or access a memory space that is local to the PE called spads.”).
Regarding claim 8, Chen in view of Falcon and Brothers teaches the IC chip of claim 7, further comprising: a plurality of local controllers, each local controller to control matrix multiplication operations within a corresponding processing cluster(Chen, pgs. 7-8, see also figs. 10,11 and 12, “[W]e implemented the GIN, as shown in Fig. 10, with two levels of hierarchy: Y-bus and X-bus. A vertical Y-bus consists of 12 horizontal X-buses, one at each row of the PE array, and each X-bus connects to 14 PEs in the row. Each X-bus has a row ID, and each PE has a col ID…[e]ach data read from the GLB is augmented with a (row, col) tag by the top-level controller…[t]he tag-ID matching is done using the Multicast Controller (MC). There are 12 MCs on the Y-bus to compare the row tag with the row ID of each X-bus, and 14 MCs on each of the X-buses to compare the col tag with the col ID of each PE… Eyeriss has separate GINs for each of the three data types (filter, ifmap, and psum) to provide sufficient bandwidth from the GLB to the PE array. All GINs have 4-b row IDs to address the 12 rows. The filter and psum GINs use 4-b col IDs to address the 14 columns, while ifmap GIN uses 5 b to support maximum 32 ifmap rows passing in diagonal. The filter and psum GINs have data bus width of 64 b (4b×16 b), while the ifmap GIN has the data bus width of 16 b.”).
Regarding claim 9, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, further comprising: a memory interface to couple the plurality of memories to a high bandwidth memory (HBM)(Falcon, para. 0041, “System logic chip 116 may include a memory controller hub (MCH). Processor 102 may communicate with MCH 116 via a processor bus 110. MCH 116 may provide a high bandwidth memory path 118 to memory 120 for instruction and data storage and for storage of graphics commands, data and textures.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Falcon for the same rationale stated at Claim 1.
Regarding claim 10, Chen in view of Falcon and Brothers teaches the IC chip of claim 9, wherein a matrix routine performed by one or more of the plurality of the processing units comprises a distributed matrix multiplication routine, the distributed matrix multiplication routine to be executed by multiple of the plurality of processing units(Falcon, paras. 0085-0087, see also fig. 11, “Execution cluster 1114 may include a number of calculation circuits 1118, distribution logics 1116, 1122, and delay elements 1120. Distribution logic 1116 may receive input signal
x
i
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i=l, ... , N, where the input signal may be image pixel values…[b]esides input signal
x
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distribution logic 1116 may also assign weight coefficients
w
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, 1, ... , N to different calculation circuits… [w]hen calculation circuits 1118 work collaboratively, they may achieve a convolution layer…or a fully-connected layer of a CNN system.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Falcon for the same rationale stated at Claim 1.
Regarding claim 11, Chen in view of Falcon and Brothers teaches the IC chip of claim 10, wherein a plurality of instructions of the matrix routine are to be executed to perform one or more convolution operations(Falcon, paras. 0085-0087, see also fig. 11, “Execution cluster 1114 may include a number of calculation circuits 1118, distribution logics 1116, 1122, and delay elements 1120. Distribution logic 1116 may receive input signal
x
i
,
i=l, ... , N, where the input signal may be image pixel values…[b]esides input signal
x
i
,
distribution logic 1116 may also assign weight coefficients
w
i
, 1, ... , N to different calculation circuits… [w]hen calculation circuits 1118 work collaboratively, they may achieve a convolution layer…or a fully-connected layer of a CNN system.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Falcon for the same rationale stated at Claim 1.
Regarding claim 12, Chen in view of Falcon and Brothers teaches the IC chip of claim 11, wherein the matrix routine is associated with an operation in a neural network(Falcon, paras. 0085-0087, see also fig. 11, “Execution cluster 1114 may include a number of calculation circuits 1118, distribution logics 1116, 1122, and delay elements 1120. Distribution logic 1116 may receive input signal
x
i
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i=l, ... , N, where the input signal may be image pixel values…[b]esides input signal
x
i
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distribution logic 1116 may also assign weight coefficients
w
i
, 1, ... , N to different calculation circuits… [w]hen calculation circuits 1118 work collaboratively, they may achieve a convolution layer…or a fully-connected layer of a CNN system.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen with the above teachings of Falcon for the same rationale stated at Claim 1.
Regarding claim 13, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein the matrix multiplication command or instruction is one of a plurality of instructions of a matrix routine, the matrix routine to be performed by one or more of the plurality of the processing units(Chen, pg., 9, As fig. 14 details below:
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The customized Caffe runs on the NVIDIA Jetson TK1 development board, and offloads the processing of a CNN layer to Eyeriss[wherein the matrix multiplication command or instruction is one of a plurality of instructions of a matrix routine, the matrix routine to be performed by one or more of the plurality of the processing units] through the PCIe interface.).
Regarding claim 14, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, further comprising: a host interface to couple the plurality of processing units to the first controller(Chen, pg., 9, As fig. 14 details below:
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The customized Caffe runs on the NVIDIA Jetson TK1 development board[a host interface], and connects to the Xilinx VC707 which communicates with the Eyeriss accelerator[to couple the plurality of processing units to the first controller].).
Regarding claim 15, Chen in view of Falcon and Brothers teaches the IC chip of claim 1, wherein each pre-multiplication arithmetic engine is integrated within a corresponding processing unit and operating on operands stored in the memory associated with that processing unit(Brothers, cols. 16-20, see also figs. 7, 9 and 11, “FIG. 7 is a block diagram illustrating an example matrix multiply unit (MMU)[within a corresponding processing unit] 700…data storage unit 702 provides input feature map data to aligner/converters 710, 712[wherein each pre-multiplication arithmetic engine is integrated]. The provided portions of the input feature map are vertically aligned based on the current (x, y) location and the y-offset associated with weights of the current matrix. Aligner/converters 710, 712 horizontally align the received portions of the input feature map and, in some embodiments, perform numerical format conversion. For example, aligner/converters 710, 712 may convert numbers from a linear format to a log or LNS format… [f]ig. 11 illustrates operation of an MMU[with that processing unit] as described with reference to FIG. 7…of this disclosure… [b]uffers 1104, 1106 pass their data to respective circuit blocks 1108, 1110 to horizontally align the data (using the x_offsets for the corresponding weights
w
0
,
w
1
) [and operating on operands stored in the memory associated]and, in some embodiments, performs floating point format to fixed point conversion. The vertically and horizontally aligned data of circuit blocks 1108, 1110 are passed to the circuit blocks 1112, 1114… where linear numbers are used, the adders 1118, 1124 may be replaced with multipliers.”).5
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chen in view of Falcon with the above teachings of Brothers for the same rationale stated at Claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM C STANDKE whose telephone number is (571)270-1806. The examiner can normally be reached Gen. M-F 9-9PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael J Huntley can be reached at (303) 297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam C Standke/
Primary Examiner
Art Unit 2129
1 Examiner Remarks: The claim limitations that are not in bold and contained within square brackets are taught by the prior art of Chen.
2 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
3 Examiner Remarks: One of ordinary skill in the art would interpret element 1110 of fig. 11 as representing element 1112 of fig. 11.
4 Examiner Remarks: Para 0065 of Applicant’s Specification details that the arithmetic engine maps to reference numerals 910a-c of drawing 9.
5 Examiner Remarks: One of ordinary skill in the art would interpret element 1110 of fig. 11 as representing element 1112 of fig. 11.
Prosecution Insights