DETAILED ACTION
This office action is in response to Application No. 18/184,902, filed on 16 March 2023. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities: claims 1, 9, 11, 12, 16, and 19 recite “a same”, which should be “the same”. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract mental processes without significantly more. The claim(s) recite(s) generating layout graphics by generating a temporary layout having a pattern, modifying the temporary layout, designating modification regions on the temporary layout, comprising pattern groups, designating transform regions on a background layer, generating a pattern layer by extracting the pattern group, and generating the layout graphic by placing the pattern layer on the transform regions of the background layer. A designer thinking about or drawing a temporary layout, thinking about or drawing a modified temporary layout, thinking about the region to be modified, and thinking about removing or otherwise erasing a pattern from the region, and thinking about or drawing the pattern into the region, performs the claimed method.
Claims 2 and 6 further specify that the patterns are ‘scripted in indenting’ or ‘scripted in embossing’, which is, at best, merely a characteristic of the pattern in the layout, so a designer thinking about or otherwise indicating that the patterns are ‘scripted in indenting’ or ‘scripted in embossing’ satisfies those limitations. The claims further recite generating the pattern layer by generating a temporary pattern layer and then generating the pattern layer, that the background layer is simply the temporary layout with the patterns removed, and placing the patterns back in the background layer, which, like the steps recited in claim 1, could be performed by a designer thinking about, erasing, or drawing patterns.
Claims 3 and 7 recite copy/pasting patterns, which a designer could do by hand. Claims 4 and 8 recite coordinate information, which does not change the abstract nature of the method and could be satisfied by a designer thinking about or marking coordinates, grids, measurements etc. Claims 5 and 9 equate sizes of the temporary pattern layer, pattern layer, and modification region, which naturally follows from the fact that the pattern layer is the pattern in the modification region and the temporary pattern layer is the pattern layer but scripted in embossing instead of indented, and so is satisfied by a designer thinking about or copying the pattern in the modification region and thinking about or indicating the pattern as being ‘scripted in embossing’. Claim 10 recites that the patterns include multiple shapes, which does not change the abstract nature of the method. Claims 11-18 recite limitations analogous to those of claims 1-10.
This judicial exception is not integrated into a practical application because aside from the abstract idea itself, the claims merely recite generic computer implementation of the abstract idea, which does not qualify as integration into a practical application. Similarly, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because generic computer implementation does not qualify as ‘significantly more’.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-9, 13, 14, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite “scripted in indenting” and/or “scripted in embossing”; it is not clear what either phrase requires. First, it is not clear what is meant by a pattern being “scripted in” indenting/embossing. Second, neither embossing nor indenting are conventional techniques used in integrated circuit layouts or integrated circuit fabrication, which is the context the invention is directed to. Neither the Specification nor the Drawings provide any clarification on these phrases, and there are no described techniques for embossing or indenting integrated circuits, and no specific differences explained between patterns “scripted in indenting” and “scripted in embossing”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 7, 10-12, and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder (US 2011/0219352) in view of Liu (CN 105631118).
Regarding claim 1, Majumder discloses a layout design tool configured to generate a layout graphic based on a first input and a modification input (¶4), the layout design tool comprising: processing circuitry configured to execute machine-readable instructions that, when executed by the processing circuitry, cause the processing circuitry (¶34),
to generate a temporary layout in which a pattern is scripted based on the first input (¶¶36-38; any of the ‘before’ layouts),
to modify the temporary layout based on the modification input to generate the layout graphic (¶¶36-38; any of the ‘after’ layouts),
to designate a plurality of modification regions to be modified on the temporary layout based on the modification input (¶¶40, 43, 46), and to designate a plurality of transform regions on a background layer (¶¶35, 38, 40; where the replacement is made on the existing layout),
the plurality of modification regions of the temporary layout include pattern groups having a same shape (¶46),
to generate a pattern layer by extracting the pattern group included in any one of the plurality of modification regions (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), and
to generate the layout graphic by placing the pattern layer on the plurality of transform regions of the background layer (¶35).
If Majumder is found to be unclear regarding the background layer and placing the pattern layer on the background layer, Liu discloses the same (Figs. 11.3-11.4 and related text). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder and Liu, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the routine combination of known elements according to known techniques, to achieve the predictable results of allowing easier layout modifications by deleting and adding object layers. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Majumder discloses search-and-replace for layout patterns, where an existing pattern is removed and a modified pattern is added. Persons having ordinary skill in the art, reading Majumder, would understand that removing an existing pattern would necessarily leave a background layer, into which the modified pattern would be added; this is also the conventional way in which modern graphical editors work. Nevertheless, Liu teaches that layout patterns are on corresponding layers, and pattern replacements such as Majumder’s are performed by removing the corresponding layer, leaving a background layer into which a pattern layer is added. The teachings of Liu are directly applicable to Majumder in the same way, so that Majumder would similarly replace patterns by removing and adding layers in order to allow easier layout modification.
Regarding claim 6, Majumder discloses that the processing circuitry is configured to script the pattern groups in embossing on the modification regions (¶4; as discussed above, ‘script in embossing’ is unclear, but known layout features such as transistor gates are above other features), to receive the temporary layout and the modification input and to generate the pattern layer in which the pattern group is scripted in embossing (¶¶36-38), to receive the temporary layout and the modification input and to generate the background layer by removing the pattern groups of the modification regions in the temporary layout (¶¶35, 38, 40; background layer are layout portions not replaced), to receive the pattern layer and the background layer, and to perform a placing operation of placing the pattern layer on the transform regions of the background layer (¶35).
As discussed above with regard to claim 1, if Majumder is found to be unclear regarding the background and pattern layers, Liu discloses the same (Figs. 11.3-11.4 and related text). Motivation to combine remains consistent with claim 1.
Regarding claim 7, Majumder discloses that the processing circuitry is configured to copy the pattern layer and paste the copied pattern layer onto the transform regions to perform the placing operation (¶¶35, 40).
Regarding claim 10, Majumder discloses that each of the pattern groups includes a plurality of shapes (Figs. 4A-6A examples each replace multiple shapes; ¶¶36-38 and 40 describe edits of all kinds with no limits on number of shapes in the pattern).
Regarding claim 11, Majumder discloses a method of modifying a layout, the method comprising: designating a plurality of modification regions, which include pattern groups having a same shape, to be modified on a temporary layout (¶¶40, 43, 46);
generating a pattern layer by extracting the pattern group from any one of the plurality of modification regions (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns);
generating a background layer by removing the pattern groups within the plurality of modification regions in the temporary layout (¶¶35, 38, 40; background layer are layout portions not replaced);
designating transform regions on the background layer (¶¶35, 38, 40; where the replacement is made on the existing layout); and
placing the pattern layer on the transform regions of the background layer to generate a final layout graphic (¶35).
Regarding claim 12, Majumder discloses that, each of the pattern groups includes a plurality of shapes, a shape of the plurality of shapes that are included in the pattern groups included in the modification regions are a same as each other, and an arrangement of the plurality of shapes that are included in the pattern groups included in the modification regions are a same as each other (¶46).
Regarding claim 15, Majumder discloses that the placing of the pattern layer on the transform regions includes: performing operations of copying the pattern layer and pasting the copied pattern layer onto the transform regions (¶¶35, 40).
Regarding claim 16, Majumder discloses that a size of the pattern layer is a same as a size of the modification region, and a size of the transform region is a same as a size of the pattern layer (¶35; this limitation is met by definition, since the pattern layer is the pattern from the modification region, and the transform region is where the pattern is deleted from)
Regarding claim 17, Majumder discloses that the pattern groups are scripted in indenting on the modification regions, and the pattern layer includes the pattern group scripted in indenting (¶¶35, 36; as discussed above, ‘script in indenting is unclear, but known layout features such as active regions or via holes are below other features).
Regarding claim 18, Majumder discloses that the pattern groups are scripted in embossing on the modification regions, and the pattern layer includes the pattern group scripted in embossing (¶¶4, 35; as discussed above, ‘script in embossing’ is unclear, but known layout features such as transistor gates are above other features).
Claim(s) 8, 9, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder in view of Liu and Marple (US 2003/0009728).
Regarding claim 8, Majumder discloses the pattern group scripted in embossing (¶4; as discussed above, ‘script in embossing’ is unclear, but known layout features such as transistor gates are above other features) and, generating the pattern layer (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), but does not appear to explicitly disclose that the processing circuitry is configured to obtain coordinate information associated with the pattern group, and to generate the pattern layer in which the pattern group is scripted in embossing by using the obtained coordinate information. However, layout patterns such as those disclosed by Majumder are conventionally defined by coordinate information, as taught by Marple (¶¶27-28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, Liu, and Marple, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the combination of known elements according to known techniques, to achieve the predictable results of accurately defining layout patterns. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Majumder discloses pattern groups and pattern layers, which would conventionally be specified by coordinates, as taught by Marple. The teachings of Marple are directly applicable to Majumder, so that Majumder’s pattern groups and pattern layers would similarly be specified by coordinates, in order to accurately define the patterns.
Regarding claim 9, Majumder discloses that a size of the pattern layer is a same as a size of the modification region (¶35; this limitation is met by definition, since the pattern layer is the pattern from the modification region).
Regarding claim 13, Majumder discloses the pattern group scripted in embossing (¶4; as discussed above, ‘script in embossing’ is unclear, but known layout features such as transistor gates are above other features) and, generating the pattern layer (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), but does not appear to explicitly disclose that the generating of the pattern layer includes: obtaining coordinate information associated with the plurality of shapes included in the pattern groups, and generating the pattern layer in which the pattern group is scripted in embossing by using the obtained coordinate information. However, layout patterns such as those disclosed by Majumder are conventionally defined by coordinate information, as taught by Marple (¶¶27-28). Motivation to combine remains consistent with claim 8.
Regarding claim 14, Majumder does not appear to explicitly disclose that the obtaining of the coordinate information associated with the plurality of shapes includes obtaining coordinate information of a plurality of points on edges of the plurality of shapes; Marple discloses these limitations (Figs. 2a-4). Motivation to combine remains consistent with claim 8.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder in view of Liu and Katase (US 2006/0214119).
Regarding claim 19, Majumder discloses a semiconductor fabrication system for fabricating a semiconductor device by generating a layout graphic based on a first input and a modification input (¶4), the semiconductor fabrication system comprising: a layout design tool configured to generate the layout graphic based on the first input and the modification input; wherein the layout tool design is configured to execute machine-readable instructions that, when executed, cause the layout generating tool (¶¶34),
to generate a temporary layout in which a pattern is scripted based on the first input (¶¶36-38; any of the ‘before’ layouts),
to modify the temporary layout based on the modification input to generate the layout graphic (¶¶36-38; any of the ‘after’ layouts),
to designate a plurality of modification regions to be modified on the temporary layout based on the modification input (¶¶40, 43, 46), and to designate a plurality of transform regions on a background layer (¶¶35, 38, 40; where the replacement is made on the existing layout),
the plurality of modification regions of the temporary layout include pattern groups having a same shape (¶46),
to generate a pattern layer by extracting the pattern group included in any one of the plurality of modification regions (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), and
to generate the layout graphic by placing the pattern layer on the plurality of transform regions of the background layer (¶35).
If Majumder is found to be unclear regarding the background layer and placing the pattern layer on the background layer, Liu discloses the same (Figs. 11.3-11.4 and related text). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder and Liu, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the routine combination of known elements according to known techniques, to achieve the predictable results of allowing easier layout modifications by deleting and adding object layers. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Majumder discloses search-and-replace for layout patterns, where an existing pattern is removed and a modified pattern is added. Persons having ordinary skill in the art, reading Majumder, would understand that removing an existing pattern would necessarily leave a background layer, into which the modified pattern would be added; this is also the conventional way in which modern graphical editors work. Nevertheless, Liu teaches that layout patterns are on corresponding layers, and pattern replacements such as Majumder’s are performed by removing the corresponding layer, leaving a background layer into which a pattern layer is added. The teachings of Liu are directly applicable to Majumder in the same way, so that Majumder would similarly replace patterns by removing and adding layers in order to allow easier layout modification.
Majumder does not appear to explicitly disclose a semiconductor fabrication device configured to fabricate the semiconductor device based on the layout graphic; however fabrication of semiconductor devices based on generated layout graphics is conventional, and persons having ordinary skill in the art, reading Majumder, would understand that Majumder’s layout graphics would be fabricated. Nevertheless, Katase teaches discloses a semiconductor fabrication system for fabricating a semiconductor device by generating a layout graphic based on a first input and a modification input, the semiconductor fabrication system comprising: a layout design tool configured to generate the layout graphic based on the first input and the modification input; and a semiconductor fabrication device configured to fabricate the semiconductor device based on the layout graphic wherein the layout tool design is configured to execute machine-readable instructions that, when executed, cause the layout generating tool (¶¶8, 9, 19).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, Liu, and Katase, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of manufacturing designed circuits. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Majumder discloses circuit layouts, which persons having ordinary skill in the art would recognize are used to fabricate circuits, as taught by Katase. The teachings of Katase are directly applicable to Majumder in the same way, so that Majumder would similarly fabricate designed circuits.
Regarding claim 20, Majumder discloses that the layout design tool is configured to copy the pattern layer and paste the copied pattern layer onto the transform regions to generate the layout graphic (¶¶35, 40).
Conclusion
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8 January 2026
/ARIC LIN/ Examiner, Art Unit 2851