DETAILED ACTION
This office action addresses Applicant’s response filed on 15 April 2026. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 7, 10-12, 15, 16, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder (US 2011/0219352) in view of dwgExplore (“Find and Replace Objects in AutoCAD with dwgExplore”), Cheng (“RepFinder: Finding Approximately Repeated Scene Elements for Image Editing”), and Katase (US 2006/0214119).
Regarding claims 1 and 11, Majumder discloses a layout design tool configured to generate a layout graphic (¶4), the layout design tool comprising: processing circuitry configured to execute machine-readable instructions that cause the layout design tool (¶34) to:
obtain a first input including information for designing a semiconductor circuit (¶35),
generate a temporary layout having a pattern based on the first input (¶¶36-38; any of the ‘before’ layouts),
obtain a modification input including information for modifying the temporary layout, generate first transform information and second transform information based on the modification input (¶¶35-38, 40, 43-45, 47, 98),
modify the temporary layout based on the first transform information and the second transform information to generate the layout graphic (¶¶36-38; any of the ‘after’ layouts), by:
based on the first transformation information, designating a plurality of modification regions to be modified on the temporary layout (¶¶40, 43, 46), each of the plurality of modification regions of the temporary layout including a pattern group having the same shape as a pattern group of other modification regions of the plurality of modification regions (¶46),
extracting the pattern group from one of the plurality of modification regions on the temporary layout (¶¶36-38, the ‘before’ patterns are modified/moved to obtain the ‘after’ patterns; ¶¶40, 43, 46),
generating a pattern layer based on the extracted pattern group from the one of the plurality of modification regions (¶¶36-38, 40; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns),
generating a background layer by removing the pattern group from each of the plurality of modification regions (¶¶35-38, 40; search patterns are replaced on the existing layout),
designating a plurality of transform regions on the background layer based on the second transform information (¶¶37, 38, 40, 98),
placing the pattern layer on each of the plurality of transform regions of the background layer, thereby generating the layout graphic (¶¶35, 37, 38, 40, 98; where the replacement is made on the existing layout).
If Majumder is found to be unclear regarding generating a background layer by removing the pattern group from each of the plurality of modification regions and placing the pattern layer on each of the plurality of transform regions of the background layer, dwgExplore (screen 3, ‘Replace/Change Options’ – ‘Replace mode’ – ‘delete found pattern and put replacement pattern instead of’) and Cheng (p. 1, Fig. 1; p. 3, Fig. 3; p. 6, ‘Instance Replacement’ and Fig. 8) also disclose the same. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, dwgExplore, and/or Cheng, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the routine combination of known elements according to known techniques, to achieve the predictable results of allowing easier layout modifications by deleting and adding object layers. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Majumder discloses search-and-replace for layout patterns, where an existing pattern is removed and a modified pattern is added. Persons having ordinary skill in the art, reading Majumder, would understand that removing an existing pattern would necessarily leave a background layer, into which the modified pattern would be added; this is also the conventional way in which modern graphical editors work. Nevertheless, dwgExplore and/or Cheng teach that layout patterns are on corresponding layers, and pattern replacements such as Majumder’s are performed by removing the corresponding layer, leaving a background layer into which a pattern layer is added. The teachings of dwgExplore and/or Cheng are directly applicable to Majumder in the same way, so that Majumder would similarly replace patterns by removing and adding layers in order to allow easier layout modification.
Majumder does not appear to explicitly disclose that a semiconductor device is fabricated based on the layout graphic; however fabrication of semiconductor devices based on generated layout graphics is conventional, and persons having ordinary skill in the art, reading Majumder, would understand that Majumder’s layout graphics would be fabricated. Nevertheless, Katase that a semiconductor device is fabricated based on the layout graphic (¶¶8, 9, 19).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, dwgExplore, Cheng, and Katase, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of manufacturing designed circuits. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Majumder discloses circuit layouts, which persons having ordinary skill in the art would recognize are used to fabricate circuits, as taught by Katase. The teachings of Katase are directly applicable to Majumder in the same way, so that Majumder would similarly fabricate designed circuits.
Regarding claim 6, Majumder discloses that the processing circuitry is configured to define the pattern group to include a raised pattern on each of the plurality of modification regions (¶4), to receive the temporary layout and the modification input and to generate the pattern layer in which the pattern group of each of the plurality of modification regions includes the raised pattern (¶¶36-38), to receive the temporary layout and the modification input and to generate the background layer by removing the pattern group of each of the plurality of modification regions in the temporary layout (¶¶35, 38, 40; background layer are layout portions not replaced), to receive the pattern layer and the background layer, and to perform a placing operation of placing the pattern layer on the plurality of transform regions of the background layer (¶35).
As discussed above with regard to claim 1, if Majumder is found to be unclear regarding the background and pattern layers, dwgExplore (screen 3, ‘Replace/Change Options’ – ‘Replace mode’ – ‘delete found pattern and put replacement pattern instead of’) and Cheng (p. 1, Fig. 1; p. 3, Fig. 3; p. 6, ‘Instance Replacement’ and Fig. 8) also disclose the same. Motivation to combine remains consistent with claim 1.
Regarding claim 7, Majumder discloses that the processing circuitry is configured to copy the pattern layer and paste the copied pattern layer onto the plurality of transform regions to perform the placing operation (¶¶35, 40).
Regarding claim 10, Majumder discloses that the pattern group includes a plurality of shapes (Figs. 4A-6A examples each replace multiple shapes; ¶¶36-38 and 40 describe edits of all kinds with no limits on number of shapes in the pattern).
Regarding claim 12, Majumder discloses that, the pattern group includes a plurality of shapes, a collective shape of the plurality of shapes in the pattern groups is the same as a collective shape of the plurality of shapes in the pattern group of the other modification regions, and an arrangement of the plurality of shapes in the pattern group is the same as an arrangement of the plurality of shapes in the pattern group of the other modification regions (¶¶35, 46).
Regarding claim 15, Majumder discloses that the placing of the pattern layer on the plurality of transform regions includes: performing operations of copying the pattern layer and pasting the copied pattern layer onto the plurality of transform regions (¶¶35, 40).
Regarding claim 16, Majumder discloses that a size of the pattern layer is the same as a size of each of the plurality of modification regions, and a size of each of the plurality of transform regions is the same as a size of the pattern layer (¶35, the transform region is the same size as the pattern layer by definition because the transform region is where the pattern layer is placed; Figs. 4A-B, 6A-B, or 7A-B).
Regarding claim 18, Majumder discloses that the pattern group includes a second pattern on each of the plurality of modification regions, the second pattern representing a raised pattern in the semiconductor device, and the pattern layer includes the pattern group having the second pattern (¶¶4, 35).
Regarding claim 19, Majumder discloses a semiconductor fabrication system (¶4) comprising: a layout design tool configured to generate a layout graphic based on a first input and a modification input; wherein the layout design tool design is configured to (¶¶34):
generate a temporary layout having a pattern based on the first input (¶¶36-38; any of the ‘before’ layouts)
obtain a modification input including information for modifying the temporary layout, generate first transform information and second transform information based on the modification input (¶¶35-38, 40, 43-45, 47, 98),
modify the temporary layout based on the first transform information and the second transform information to generate the layout graphic (¶¶36-38; any of the ‘after’ layouts), by:
based on the first transformation information, designating a plurality of modification regions to be modified on the temporary layout (¶¶40, 43, 46), each of the plurality of modification regions of the temporary layout including a pattern group having the same shape as a pattern group of other modification regions of the plurality of modification regions (¶46),
extracting the pattern group from one of the plurality of modification regions on the temporary layout (¶¶36-38, the ‘before’ patterns are modified/moved to obtain the ‘after’ patterns; ¶¶40, 43, 46),
generating a pattern layer based on the extracted pattern group from the one of the plurality of modification regions (¶¶36-38, 40; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns),
generating a background layer by removing the pattern group from each of the plurality of modification regions (¶¶35-38, 40; search patterns are replaced on the existing layout),
designating a plurality of transform regions on the background layer based on the second transform information (¶¶37, 38, 40, 98),
placing the pattern layer on each of the plurality of transform regions of the background layer, thereby generating the layout graphic (¶¶35, 37, 38, 40, 98; where the replacement is made on the existing layout).
If Majumder is found to be unclear regarding generating a background layer by removing the pattern group from each of the plurality of modification regions and placing the pattern layer on each of the plurality of transform regions of the background layer, dwgExplore (screen 3, ‘Replace/Change Options’ – ‘Replace mode’ – ‘delete found pattern and put replacement pattern instead of’) and Cheng (p. 1, Fig. 1; p. 3, Fig. 3; p. 6, ‘Instance Replacement’ and Fig. 8) also disclose the same. Motivation to combine remains consistent with claim 1.
Majumder does not appear to explicitly disclose a semiconductor fabrication device configured to fabricate a semiconductor device based on the layout graphic; however fabrication of semiconductor devices based on generated layout graphics is conventional, and persons having ordinary skill in the art, reading Majumder, would understand that Majumder’s layout graphics would be fabricated. Nevertheless, Katase teaches discloses a semiconductor fabrication system for fabricating a semiconductor device by generating a layout graphic based on a first input and a modification input, the semiconductor fabrication system comprising: a layout design tool configured to generate the layout graphic based on the first input and the modification input; and a semiconductor fabrication device configured to fabricate the semiconductor device based on the layout graphic wherein the layout tool design is configured to execute machine-readable instructions that, when executed, cause the layout generating tool (¶¶8, 9, 19). Motivation to combine remains consistent with claim 1.
Regarding claim 20, Majumder discloses that the layout design tool is configured to copy the pattern layer and paste the copied pattern layer onto the plurality of transform regions to generate the layout graphic (¶¶35, 40).
Claim(s) 2, 3, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder in view of dwgExplore, Cheng, Katase, and Pang (US 2018/0074393).
Regarding claim 2, Majumder that the pattern group of each of the plurality of modification regions includes a first pattern, the first pattern representing a recessed pattern in the semiconductor device (¶36, Fig. 1A active region),
and the processing circuitry is configured to receive the temporary layout and the modification input and to generate a temporary pattern layer in which the pattern group of each of the plurality of modification regions includes a second pattern representing a raised pattern in the semiconductor device, to receive the temporary layout and the modification input (¶¶35-38, 40, 45-46, 47, 98; ¶36, Fig. 1B gate),
to generate the background layer by removing the pattern group of each of the plurality of modification regions in the temporary layout (¶¶35, 38, 40; background layer layout portions not replaced),
to receive the temporary pattern layer and to generate the pattern layer in which the pattern group of each of the plurality of modification regions includes a third pattern that represents a recessed pattern in the semiconductor device, to receive the pattern layer and the background layer, and to perform a placing operation of placing the pattern layer on the plurality of transform regions of the background layer (¶¶35, 37, 38, 40, 98, where the replacement is made on the existing layout; ¶36, Fig. 1B active region).
If Majumder is found to be unclear regarding generating the background layer by removing the pattern group from each of the plurality of modification regions and placing the pattern layer on each of the plurality of transform regions of the background layer, dwgExplore (screen 3, ‘Replace/Change Options’ – ‘Replace mode’ – ‘delete found pattern and put replacement pattern instead of’) and Cheng (p. 1, Fig. 1; p. 3, Fig. 3; p. 6, ‘Instance Replacement’ and Fig. 8) also disclose the same. Motivation to combine remains consistent with claim 1.
If Majumder is found to be unclear regarding that the first pattern represents a recessed pattern, the second pattern represents a raised pattern, and the third pattern represents a recessed pattern. Pang discloses these limitations (¶51). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, dwgExplore, Cheng, Katase, and Pang, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing search and replace of positive and negative assist features to improve dimensional control of fabricated patterns. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Majumder teaches search-and-replace of arbitrary layout patterns. Pang teaches layout patterns including positive and negative assist features that improve dimensional control of fabricated patterns. The teachings of Pang are directly applicable to Majumder in the same way, so that Majumder’s process would also allow search-and-replace operations on patterns with positive and negative assist features to improve dimensional control of fabricated patterns.
Regarding claim 3, Majumder discloses that the processing circuitry is configured to copy the pattern layer and paste the copied pattern layer onto the plurality of transform regions to perform the placing operation (¶¶35, 40).
Regarding claim 17, Majumder discloses that the pattern group includes a first pattern on each of the plurality of modification regions, the first pattern representing a recessed pattern in the semiconductor device and the pattern layer includes the pattern group having the first pattern (¶¶35, 36; layout features such as active regions or via holes are below other features). If Majumder is found to be unclear regarding the recessed pattern, Pang discloses the same (¶51). Motivation to combine remains consistent with claim 2.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder in view of dwgExplore, Cheng, Katase, Pang, and Marple (US 2003/0009728).
Regarding claim 4, Majumder discloses the pattern group (¶¶35-38) and, generating the temporary pattern layer (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), but does not appear to explicitly disclose that the processing circuitry is configured to obtain coordinate information associated with the pattern group, and to generate the temporary pattern layer in which the pattern group by using the obtained coordinate information. However, layout patterns such as those disclosed by Majumder are conventionally defined by coordinate information, as taught by Marple (¶¶27-28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, dwgExplore, Cheng, Katase, Pang, and Marple, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the combination of known elements according to known techniques, to achieve the predictable results of accurately defining layout patterns. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Majumder discloses pattern groups and pattern layers, which would conventionally be specified by coordinates, as taught by Marple. The teachings of Marple are directly applicable to Majumder, so that Majumder’s pattern groups and pattern layers would similarly be specified by coordinates, in order to accurately define the patterns.
Regarding claim 5, Majumder discloses that a size of the temporary pattern layer is the same as a size of the modification region, and a size of the pattern layer is the same as a size of the temporary pattern layer (¶35, the modification region has the same size as the temporary pattern layer by definition, since the temporary pattern layer is the pattern from the modification region; Figs. 4A-B, 6A-B, or 7A-B).
Claim(s) 8, 9, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumder in view of dwgExplore, Cheng, Katase, and Marple.
Regarding claim 8, Majumder discloses the pattern group (¶¶35-38) and, generating the pattern layer (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), but does not appear to explicitly disclose that the processing circuitry is configured to obtain coordinate information associated with the pattern group, and to generate the pattern layer in which the pattern group by using the obtained coordinate information. However, layout patterns such as those disclosed by Majumder are conventionally defined by coordinate information, as taught by Marple (¶¶27-28). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Majumder, dwgExplore, Cheng, Katase, and Marple, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the combination of known elements according to known techniques, to achieve the predictable results of accurately defining layout patterns. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Majumder discloses pattern groups and pattern layers, which would conventionally be specified by coordinates, as taught by Marple. The teachings of Marple are directly applicable to Majumder, so that Majumder’s pattern groups and pattern layers would similarly be specified by coordinates, in order to accurately define the patterns.
Regarding claim 9, Majumder discloses that a size of the pattern layer is the same as a size of each of the plurality of modification regions (¶35; Figs. 4A-B, 6A-B, or 7A-B).
Regarding claim 13, Majumder discloses the pattern group (¶¶35-38), and generating the pattern layer (¶¶36-38; any of the ‘after’ patterns obtained from modifying the ‘before’ patterns), but does not appear to explicitly disclose that the generating of the pattern layer includes: obtaining coordinate information associated with the plurality of shapes included in the pattern groups, and generating the pattern layer in which the pattern group by using the obtained coordinate information. However, layout patterns such as those disclosed by Majumder are conventionally defined by coordinate information, as taught by Marple (¶¶27-28). Motivation to combine remains consistent with claim 8.
Regarding claim 14, Majumder does not appear to explicitly disclose that the obtaining of the coordinate information associated with the plurality of shapes includes obtaining coordinate information of a plurality of points on edges of the plurality of shapes; Marple discloses these limitations (Figs. 2a-4). Motivation to combine remains consistent with claim 8.
Response to Arguments
Applicant's arguments filed 15 April 2026 have been fully considered but they are not persuasive.
As an initial matter, new/edited limitations are addressed above in the rejections of the claims.
Applicant asserts that “Majumder describes that a specific pattern included in a cell does not include the plurality of patterns, unlike the claimed subject matter of the present application”. Remarks 11. The examiner disagrees. Majumder teaches arbitrary modifications to patterns (¶40, “add, delete, move, copy, or otherwise manipulate all devices or shapes in the schematic or layout design”), and includes many different example modifications, including those where the cell includes the plurality of patterns (e.g., Figs. 4A-B, 6A-B, or 7A-B). Furthermore, even assuming, arguendo, that Applicant’s assertion was correct, it is not clear how the claim requires the cell to ‘include the plurality of patterns’. Claim 1 recites a modification process where the pattern layer is generated based on the extracted pattern group from the modification regions and then places the pattern layer on transform regions of the background layer; in other words, a new pattern is generated to replace the original pattern. Nowhere does the claim require that the new pattern be the same as the old pattern, which Applicant appears to be arguing.
Applicant asserts that “Majumder merely discloses a method of moving a specific pattern based on coordinates. Majumder fails to disclose a method of arranging a pattern layer by additionally designating a separate region based on a plurality of transformation information.” Remarks 11. The examiner disagrees. Majumder discloses a variety of possible pattern changes, based on a corresponding variety of different information (¶¶36-38, 40, 43-45, 47, 98). The examiner also fundamentally disagrees with Applicant’s alleged distinction between ‘moving a specific pattern based on coordinates’ and ‘designating a separate region based on a plurality of transformation information’. Moving a pattern to a new location necessarily designates the location the pattern is moved to; the ‘separate region’ is the region that is occupied by the pattern in the new location, and is designated by the information used to perform the move, however specified. There is no practical distinction between ‘merely moving a pattern based on coordinates’ and ‘designating a separate region based on a plurality of transformation information’.
Applicant asserts that “according to Liu’s method, it is not possible to separately designate a region to be modified or a region where a pattern is to be newly arranged” and “Liu does not disclose a configuration in which a layer, which is the object being modified, includes a plurality of patterns”. Remarks 12. Applicant’s argument relies on improper piecemeal analysis of the references. Majumder already teaches the designation of regions to be modified and regions where a pattern is to be newly arranged, as well as layers including a plurality of patterns; there is no need for Liu to further disclose those features in order for the claims to be obvious in view of the combination of Majumder and Liu. Liu was relied upon merely for disclosure of the separate background layer, which Applicant does not dispute.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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14 August 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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