Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Authorization for Internet Communications in a Patent Application
Applicant is encouraged to file an Authorization for Internet Communications in a Patent Application form (http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) along with the response to this office action to facilitate and expedite future communication between Applicant and the examiner. If the form is submitted then Applicant is requested to provide a contact email address in the signature block at the conclusion of the official reply.
Request for Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/14/2026 has been entered.
Allowable Subject Matter
Claims 11-13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable over the prior art of record if rewritten to overcome the applicable rejections and/or objections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the examiner found neither prior art cited in its entirety, nor based on the prior art, found any motivation to combine any of the said prior art.
Applicant’s Reply Not Fully Responsive
The reply filed on 07/14/2026 is not fully responsive to the prior Office action (see Advisory Action dated 06/23/2026) because of the following omission(s) or matter(s): Applicant fails to interact with or address any of the examiner’s limitation-by-limitation 35 U.S.C. 101 abstract idea analysis of the claims (especially the dependent claims) provided in the rejection above. Even if an independent claim is deemed eligible then it does not necessarily mean that all of the dependent claims are also eligible. The examiner highly encourages Applicant to review MPEP 2106 prior to submitting any subsequent response. Also, Applicant failed to amend claims 2 and 15-16 (see 35 U.S.C. 112(d)) rejection below). See 37 CFR 1.111. The response appears to be bona fide, but through an apparent oversight or inadvertence, consideration of some matter or compliance with some requirement has been omitted. Applicant is required to supply the omission or correction to thereby provide a full subsequent response to the instant Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-17 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
As per claims 1-17, they contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. The amendment filed on 07/14/2026 introduces new matter into the claims. The added material which is not supported by the original disclosure is as follows: (i.e., "during the compilation of the program" recited in claim 1, ll. 9-10 and “during compilation of an assembly language program” recited in claim 14, ll. 3-4). Dependent claims 2-13 and 15-17 are rejected using the same rationale as above by virtue of being dependent upon one of the above rejected independent claims 1 and 14. Applicant is required to cancel the new matter in the reply to this Office action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As per claim 1, Applicant is requested to clarify whether or not the second portion is to be scheduled for execution according to the schedule of the first portion or according to a different schedule. For the purposes of examination, the examiner interprets that the second portion is be scheduled according to any schedule. Appropriate correction is required.
As per claim 14, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per the remaining dependent claims not specifically mentioned above, they are also rejected using the same rationale as above by virtue of being dependent upon one of the above rejected independent claims.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2 and 15-16 are rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
As per claims 2 and 15-16, they do not each reference a previously set forth claim. Applicant should cancel claim 2 and rewrite it as new claim 21 to depend on claim 13, cancel claim 15 and rewrite it as new claim 22 to depend on claim 17, and cancel claim 16 and rewrite it as new claim 23 to depend on claim 17. Applicant should then amend the dependencies of all dependent claims affected by the required changes. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (an abstract idea) without significantly more.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 1. A method, comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
wherein a second portion of the instructions of the program is to be scheduled during the compilation of the program for execution in the device (abstract idea mental process);
selecting, by the computing apparatus during the compilation of the program using a first artificial neural network, a placement of the next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device (abstract idea mental process), wherein the next instruction is in the second portion of the instructions of the program, and the placement is selected to comply with the execution dependency conditions in view of the schedule of the first portion of the instructions of the program represented by the second data (abstract idea mental process).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
receiving, in a computing apparatus (generic computing components) configured to compile computer programs for execution on computing devices, first data representative of execution dependency conditions of instructions of a program (generic computing components performing extra-solution activity of receiving data/information);
receiving, in the computing apparatus during compilation of the program, second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuit units operable in parallel (generic computing components performing extra-solution activity of receiving data/information).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
receiving, in a computing apparatus configured to compile computer programs for execution on computing devices, first data representative of execution dependency conditions of instructions of a program (extra-solution activity of receiving data/information);
receiving, in the computing apparatus during compilation of the program. second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuit units operable in parallel (extra-solution activity of receiving data/information).
Claim 2. The method of claim 13, further comprising:
receiving third data identifying the next instruction selected from the second portion of the instructions of the program, the second portion to be scheduled for execution in the device (extra-solution activity of receiving data/information); and
applying the first data, the second data and the third data as input to the first artificial neural network (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea);
wherein the program is an assembly language program identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 3. The method of claim 2, wherein the device comprises a coarse grained reconfigurable array having a plurality of tiles operable in parallel as the plurality of circuit units respectively (generic computing components); wherein each of the tiles has a plurality of instruction slots for pipelined execution (generic computing components); and wherein the placement of the next instruction includes identification of a tile among the tiles, and a slot among instruction slots in the tile for execution of the next instruction (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 4. The method of claim 3, wherein the first data identifies dependency of execution of first instructions in receiving, as input, outputs generated from execution of second instructions (extra-solution activity of receiving data/information).
Claim 5. The method of claim 4, wherein the first data further identifies dependency of third instructions, scheduled to be executed in a respective tile, in accessing data at memory locations represented by memory variables implemented in the respective tile (extra-solution activity of retrieving data/information).
Claim 6. The method of claim 1, further comprising: generating, using a second artificial neural network, a performance measure of the selecting the placement of the next instruction from the plurality of possible placements (extra-solution activity of generating data/information).
Claim 7. The method of claim 4, further comprising: generating the plurality of samples, each respective sample among the samples specifying: a respective input to the first artificial neural network, the respective input identifying: a respective schedule of a respective portion of the instructions of the program; and a respective instruction to be scheduled in addition to the respective schedule; a respective placement of the respective instruction; and a respective performance measure for the respective placement (extra-solution activity of generating data/information).
Claim 8. The method of claim 7, further comprising: determining a count of cycles to complete execution, according to the respective schedule and the respective placement, of the respective portion of the instructions of the program and the respective instruction (abstract idea mental process); and calculating the respective performance measure based on the count of cycles (abstract idea mental process).
Claim 9. The method of claim 6, further comprising: training, using a plurality samples and a technique of proximal policy optimization (PPO) of reinforcement learning to minimize a loss function, the first artificial neural network and the second artificial neural network (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 10. The method of claim 9, wherein the loss function is based on evaluating a first loss representing a reduction in performance measure resulting from the first artificial neural network selecting placements different from corresponding placements in the samples, and a second loss resulting from the second artificial neural network generating performance measures different from corresponding performance measures in the samples (abstract idea mental process).
Claim 11. The method of claim 10, wherein the second loss is based on a mean square error between performance measures generated by the second artificial neural network responsive to inputs specified in the samples and corresponding performance measures specified in the samples; and the first loss is based on a difference between a performance measure generated by the second artificial neural network and a corresponding performance measure in the samples, weighted by an exponential function of a logarithm function of a probability ratio that is equal to a ratio between: a probability of placements selected by the first artificial neural network responsive to inputs specified in the samples; and a probability of corresponding placements specified in the samples (abstract idea mental process).
Claim 12. The method of claim 11, further comprising: testing placement options to search for a valid schedule for at least portions of the instructions of the program (abstract idea mental process); wherein the plurality of samples are generated from the placement options being tested to search for the valid schedule (extra-solution activity of generating data/information).
Claim 13. The method of claim 12, wherein at least one of the placement options being tested is selected by the first artificial neural network before the training of the first artificial neural network and the second artificial neural network using the samples and the technique of proximal policy optimization (PPO) of reinforcement learning (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
As per claim 14, it has similar limitations as claims 1-3 and is therefore rejected using the same rationale.
As per claim 15, it has similar limitations as claims 4-5 and is therefore rejected using the same rationale.
As per claim 16, it has similar limitations as claims 7 and 9-10 and is therefore rejected using the same rationale.
As per claim 17, it has similar limitations as claims 12-13 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 14 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 16 and is therefore rejected using the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Beardslee et al. (US 2007/0226686) (hereinafter Beardslee) in view of Folliot et al. (US 2021/0342265) (hereinafter Folliot as previously cited).
As per claim 1, Beardslee primarily teaches the invention as claimed including:
receiving, in a computing apparatus configured to compile computer programs for execution on computing devices ([0064]-[0065] and [0089] compilation process for assembly language), first data representative of execution dependency conditions of instructions of a program ([0018] and [0075] dependencies and dependency graph);
receiving, in the computing apparatus during compilation of the program, second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuit units operable in parallel, wherein a second portion of the instructions of the program is to be scheduled during the compilation of the program for execution in the device ([0077] create an execution order during compile time so that a task is scheduled to be executed only when all its prerequisite data is available. The scheduling process serializes parallel tasks for execution by a single processor without deadlocks. Deadlocks are detected by augmenting the task graph with the dependencies introduced by the clustering and scheduling process. Cycles in the task graph correspond to potential deadlock conditions, which are removed by changing the clustering or scheduling scheme); and
selecting, by the computing apparatus during the compilation of the program, a placement of a next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device, wherein the next instruction is in the second portion of the instructions of the program, and the placement is selected to comply with the execution dependency conditions in view of the schedule of the first portion of the instructions of the program represented by the second data ([0077] create an execution order during compile time so that a task is scheduled to be executed only when all its prerequisite data is available. The scheduling process serializes parallel tasks for execution by a single processor without deadlocks. Deadlocks are detected by augmenting the task graph with the dependencies introduced by the clustering and scheduling process. Cycles in the task graph correspond to potential deadlock conditions, which are removed by changing the clustering or scheduling scheme).
Beardslee does not explicitly teach:
selecting, using a first artificial neural network, a placement of a next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device.
However, Folliot teaches selecting, using a first artificial neural network (title and [0017] artificial neural network), a placement of a next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device ([0031] placements of intermediate data blocks of the subsequent i.e., next layers of the modified sequence are selected from the possible placements for these intermediate data blocks).
Folliot and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of Folliot because it would provide for an order of priority which is advantageously established between various possible placements of each intermediate data block. The highest order of priority is given to the placement that is arbitrarily considered to be the most optimized. For example, it may be advantageous to consider the interposition placement as the most optimized over the superposition placement and the forced allocation placement. This placement is considered to be the most optimized for a data block taken in isolation.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale et al. (US 2021/0072901) (hereinafter Kale as previously cited) in view of Mola (US 2024/0220397) (as previously cited).
As per claim 2, Beardslee in view of Folliot do not explicitly teach:
receiving third data identifying the next instruction selected from the second portion of the instructions of the program, the second portion to be scheduled for execution in the device; and
applying the first data, the second data and the third data as input to the first artificial neural network;
wherein the program is an assembly language program identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows.
However, Kale teaches:
receiving third data identifying the next instruction selected from the second portion of the instructions of the program, the second portion to be scheduled for execution in the device ([0216] schedule command for execution); and
applying the first data, the second data and the third data as input to the first artificial neural network ([0013] apply the inputs to the ANN).
Kale and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale because it would provide a way for computations configured in a data storage device to be used to reduce the amount of data to be transmitted to processors to use or apply the ANN and/or reduce the computation tasks of the processors in evaluating the outputs of the ANN and/or in training the ANN. Such an arrangement can result in faster output from the data storage device and/or lower energy usage, since the data would not have to be moved in and out of the memory to a dedicated, standalone neural network accelerator. The computation capability of the data storage device in processing data related to the ANN enables the computer system to monitor the health of system components with reduced impact, or no impact, on the processing of mission critical tasks. Further, the computation capability of the data storage device can be used to accelerate the processing of the sensor data and thus improve the processing of mission critical tasks.
Beardslee in view of Folliot in view of Kale do not explicitly teach wherein the program is an assembly language program identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows.
However, Mola teaches wherein the program is an assembly language program ([0034] assembly language) identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows ([0056]-[0057] identifying inputs/outputs for execution trace to generate a data flow dependency graph that links inputs/outputs through transforming activities).
Mola and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale in view of Mola because it would provide a way for data flow dependency graph generation, topological sorting, and input/output pairing which can reduce an amount of data that a computer processor analyzes/processes when determining which inputs are causal to outputs that differed between execution traces. In particular, they resulting system may only traverse the branches of data flow dependency graphs that are relevant to those outputs. This achieves a technical effect of efficiently identifying a root cause of at least one difference in the execution result of an entity in a manner that efficiently devotes computing resources to only a fraction of execution trace that is actually relevant to those differences. Additionally, by automatically identifying the root cause (i.e., inputs) that led to outputs differing between execution traces, this can efficiently pinpoint software faults, such as code bugs or invalid inputs while being more precise in pointing input differences that are causing the output differences (i.e., behavioral changes) than conventional analysis techniques.
Claims 3-4, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet et al. (US 2012/0303933) (hereinafter Manet as previously cited).
As per claim 3, Beardslee in view of Folliot in view of Kale in view of Mola do not explicitly teach wherein the device comprises a coarse grained reconfigurable array having a plurality of tiles operable in parallel as the plurality of circuit units respectively; wherein each of the tiles has a plurality of instruction slots for pipelined execution; and wherein the placement of the next instruction includes identification of a tile among the tiles, and a slot among instruction slots in the tile for execution of the next instruction.
However, Manet teaches wherein the device comprises a coarse grained reconfigurable array ([0016] coarse grain reconfigurable processing arrays) having a plurality of tiles operable in parallel as the plurality of circuit units respectively ([0124] tiles of a cluster execute a same thread in parallel); wherein each of the tiles has a plurality of instruction slots for pipelined execution ([0111] sub-execution blocks are executed in parallel on tiles via tile execution pipelines and [0144] pipelining between tiles); and wherein the placement of the next instruction includes identification of a tile among the tiles, and a slot among instruction slots in the tile for execution of the next instruction ([0101] an instruction slot per tile).
Manet and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet because it would provide advantages for when a local instruction memory captures a loop. In this case, the fetch power consumption is dominated by the local memory access power, which is far less than a cache access. Second, local branches in local code allow to capture loops embodying complex control paths which increases the number of reused loops. Third, executing a conditional branch in the local buffer using immediate address allows a very short pipeline which causes branches to have a very limited penalty. This allows to execute branch intensive code without incurring important performance loss or without using power-hungry mitigation techniques.
As per claim 4, Mola teaches wherein the first data identifies dependency of execution of first instructions in receiving, as input, outputs generated from execution of second instructions ([0066] input and output pairs associated with data flow dependency graphs are generated).
As per claim 14, it has similar limitations as claims 1-3 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 14 and is therefore rejected using the same rationale.
Claims 5, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming et al. (US 2019/0205284) (hereinafter Fleming as previously cited).
As per claim 5, Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet do not explicitly teach wherein the first data further identifies dependency of third instructions, scheduled to be executed in a respective tile, in accessing data at memory locations represented by memory variables implemented in the respective tile.
However, Fleming teaches wherein the first data further identifies dependency of third instructions, scheduled to be executed in a respective tile, in accessing data at memory locations represented by memory variables implemented in the respective tile ([0285] second access request may thus be marked in the scheduler to require receipt of a memory dependency token caused by first access request before issuance of the second access request and the first and second access requests are to access the same address i.e., memory location in tile level memory).
Fleming and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming because it would provide for performance increases from parallel execution within a dense spatial array of processing elements where each processing element and/or network dataflow endpoint circuit utilized may perform its operations simultaneously, e.g., if input data is available. Efficiency increases may result from the efficiency of each processing element and/or network dataflow endpoint circuit, e.g., where each processing element 's operation (e.g., behavior) is fixed once per configuration (e.g., mapping) step and execution occurs on local data arrival at the processing element, e.g., without considering other fabric activity, and/or where each network dataflow endpoint circuit's operation (e.g., behavior) is variable (e.g., not fixed) when configured (e.g., mapped).
As per claim 15, it has similar limitations as claims 4-5 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby et al. (US 2021/0072921) (hereinafter Bielby as previously cited).
As per claim 6, Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming do not explicitly teach generating, using a second artificial neural network, a performance measure of the selecting the placement of the next instruction from the plurality of possible placements.
However, Bielby teaches generating, using a second artificial neural network, a performance measure of the selecting the placement of the next instruction from the plurality of possible placements ([0227] ANN can self-organize to find optimization for data placement and [0249] generate training data by trying different data placement schemes for data objects recognized by the ANN for a data access pattern based on performances of the data placement schemes).
Bielby and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby because it would provide for intelligent wear-leveling with reduced write-amplification for data storage devices. For example, a data storage device can include an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized operation for wear leveling among memory cells in the data storage device. A controller can then be configured to perform the optimized operation for wear leveling based on the prediction.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne et al. (US 12,314,385) (hereinafter Beauchesne as previously cited) in view of Oswal et al. (US 2023/0297573) (hereinafter Oswal as previously cited).
As per claim 7, Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby do not explicitly teach generating the plurality of samples, each respective sample among the samples specifying: a respective input to the first artificial neural network, the respective input identifying: a respective schedule of a respective portion of the instructions of the program; and a respective instruction to be scheduled in addition to the respective schedule; a respective placement of the respective instruction; and a respective performance measure for the respective placement.
However, Beauchesne teaches generating the plurality of samples (col. 16, ll. 12-13 points may be sampled to generate synthetic data points and col. 44, ll. 52-54 generating synthetic data that preferentially sample points), each respective sample among the samples specifying: a respective input to the first artificial neural network (col. 6, ll. 38-40 process record including features of a process are used to construct an input feature vector for consumption by machine learning models), the respective input identifying: a respective schedule of a respective portion of the instructions of the program (col. 38, ll. 5-7 configuration input specifies a schedule of code execution); and a respective instruction to be scheduled in addition to the respective schedule (col. 57, ll. 22-23 scheduling different jobs according to pipeline configurations).
Beauchesne and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne because it would provide for a machine learning pipeline system to detect outlier events in collected data of computer networks. The resulting system can improve upon conventional systems by using machine learning techniques to improve the speed and efficiency of processing large amounts of data and prioritizing investigations analysts should perform. The system can allow security analysts to better utilize their time and expertise to focus on the suspicious outlier events detected by the system, and drastically reduces the amount of time it takes to detect an attack or compromise, thus minimizing the chances of potentially crippling outcomes.
Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne do not explicitly teach a respective placement of the respective instruction; and a respective performance measure for the respective placement.
However, Oswal teaches a respective placement of the respective instruction; and a respective performance measure for the respective placement ([0056] performance benefit threshold that represents a minimum performance benefit value that the performance benefit of the data placement candidate must exceed in order to generate the one or more data placement commands).
Oswal and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal because it would provide a prediction-driven, rather than a trial-driven, approach to automatic data placement recommendations. Based at least in part on workload-specific features, dataset specific features, and a plurality of candidate keys, a set of candidate key combinations for partitioning data is generated. Using a machine learning model can determine a particular candidate key combination that optimizes query execution performance benefit based on the workload-specific features and the dataset specific features.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari et al. (US 2020/0160159) (hereinafter Azari as previously cited).
As per claim 8, Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal do not explicitly teach determining a count of cycles to complete execution, according to the respective schedule and the respective placement, of the respective portion of the instructions of the program and the respective instruction; and calculating the respective performance measure based on the count of cycles.
However, Azari teaches determining a count of cycles to complete execution, according to the respective schedule and the respective placement, of the respective portion of the instructions of the program and the respective instruction; and calculating the respective performance measure based on the count of cycles ([0033] the performance of a low-power approximate multiplier is significantly improved and incorporated in the compute-intensive units while its execution time is data-dependent, and the number of clock cycles required to finish a single instruction depends on the magnitude of the instruction).
Azari and Beardslee are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari because it would provide for neural network circuitry having a first plurality of logic cells that is interconnected to form neural network computation units that are configured to perform approximate computations. The neural network circuitry further includes a second plurality of logic cells that is interconnected to form a controller hierarchy that is interfaced with the neural network computation units to control pipelining of the approximate computations performed by the neural network computational units. The neural network computation units include approximate multipliers that are configured to perform approximate multiplications that comprise the approximate computations. The approximate multipliers include preprocessing units that reduce latency while maintaining accuracy.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He et al. (US 2022/0164657) (hereinafter He as previously cited).
As per claim 9, Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari do not explicitly teach training, using a plurality of samples and a technique of proximal policy optimization (PPO) of reinforcement learning to minimize a loss function, the first artificial neural network and the second artificial neural network.
However, He teaches training, using a plurality of samples and a technique of proximal policy optimization (PPO) of reinforcement learning to minimize a loss function, the first artificial neural network and the second artificial neural network ([0044] training a neural network by minimizing a loss function based on a proximal policy optimization).
He and Beardslee are both concerned with neural networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He because it would provide for a robustness and improvement of optimization algorithms such as Stochastic gradient descent (SGD) for training deep neural networks. In SGD, instead of taking one step along the computed gradient of the loss on all training samples, multiple steps are taken by computing the gradient of the loss of different random subsets of the training samples. SGD substantially lowers the computational cost for each update and also alleviates the impact of local optima and saddle points. In addition, numerous improvements to SGD, such as momentum, root-mean-squared prop, and adaptive momentum estimation, have been proposed and shown to be effective in resolving oscillation of gradient by smoothing it using different moving average formulas.
Claims 10, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He in view of O et al. (US 2021/0168195) (hereinafter O as previously cited).
As per claim 10, Beardslee in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He do not explicitly teach wherein the loss function is based on evaluating a first loss representing a reduction in performance measure resulting from the first artificial neural network selecting placements different from corresponding placements in the samples, and a second loss resulting from the second artificial neural network generating performance measures different from corresponding performance measures in the samples.
However, O teaches wherein the loss function is based on evaluating a first loss representing a reduction in performance measure resulting from the first artificial neural network selecting placements different from corresponding placements in the samples, and a second loss resulting from the second artificial neural network generating performance measures different from corresponding performance measures in the samples ([0139] and [0154] compare accuracy and loss values of neural network models to determine which model results in improved performance).
O and Beardslee are both concerned with neural networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Beardslee in view of in view of Folliot in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He in view of O because it would provide a way to deploy an updated neural network model in such a way that the amount of the file transmitted by deploying only the information about the changed layer is reduced, thereby shortening the time required for deployment and training of the neural network model, and thus, an overload to the server may be prevented.
As per claim 16, it has similar limitations as claims 7 and 9-10 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 16 and is therefore rejected using the same rationale.
Response to Arguments
All of Applicant's arguments have been considered.
In the Remarks on pg. 1-2, Applicant argues that “during the compilation of the program” does not recite new matter. The examiner respectfully disagrees. Applicant cites to [0115], [0117], and [0242] of the instant disclosure for support. However, none of the aforementioned portions provide adequate support for the recited new matter in the claims. More specifically, [0115] does not support the claim limitation “wherein a second portion of the instructions of the program is to be scheduled during the compilation of the program for execution in the device” because [0115] does not recite any scheduling, but rather recites mapping data flows in the assembly language program which is not the same as scheduling. [0117] says that the schedule can be generated from the assembly language program using a scheduler, but it does not support “wherein a second portion of the instructions of the program is to be scheduled during the compilation of the program for execution in the device”. That the schedule can be generated from the assembly program using a scheduler does not require that the instructions are “scheduled during the compilation”. Finally, [0242] recites a scheduler implemented via software. However, the software or software tool is not necessarily the compiler and/or a compilation/programming tool as asserted by Applicant. In fact, [0038] of the instant specification specifically states that a software tool is a “lowering program” which is not the same as a compiler. Even assuming arguendo, that the software tool is the same as the compiler would still not provide support for the recited new matter in the claims “wherein a second portion of the instructions of the program is to be scheduled during the compilation of the program for execution in the device” because there is simply no language in the instant specification that mentions or even implies that any of the claimed recited steps are performed “during compilation”. Applicant attempts to unsuccessfully provide support for the new matter added to the claims by citing several disparate and unrelated portions of the instant specification. Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
Applicant's arguments on pg. 2-4 of the Remarks regarding the 35 U.S.C. 103 rejections are moot in view of the new grounds of rejection necessitated by Applicant’s amendments because the new grounds of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to the 35 U.S.C. 101 rejections have been fully considered but they are not persuasive. In the Remarks on pg. 4, Applicant argues an improved compilation technique for a particular type of devices. The examiner respectfully traverses. Applicant is reminded of In re Buchner, 929 F.2d 660, 661, 18 USPQ2d 1331, 1332 (Fed. Cir. 1991) (“expert’s opinion on the ultimate legal conclusion must be supported by something more than a conclusory statement”). It appears that Applicant is merely making a conclusory statement. Attorney argument is not evidence unless it is an admission, in which case, an examiner may use the admission in making a rejection (see MPEP § 2129 and § 2144.03 for a discussion of admissions as prior art). The arguments of counsel cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997) ("An assertion of what seems to follow from common experience is just attorney argument and not the kind of factual evidence that is required to rebut a prima facie case of obviousness."). See MPEP § 716.01(c) for examples of attorney statements which are not evidence and which must be supported by an appropriate affidavit or declaration.
If it is asserted that the invention improves upon conventional functioning of a computer, or upon conventional technology or technological processes, a technical explanation as to how to implement the invention should be present in the specification (see MPEP 2106.05(a)). That is, the disclosure must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement and the claim itself must reflect the improvement in technology (emphasis added by the examiner). An indication that the claimed invention provides an improvement can include a discussion in the specification that identifies a technical problem and explains the details of an unconventional technical solution expressed in the claim, or identifies technical improvements realized by the claim over the prior art. The claim must be evaluated to ensure the claim itself reflects the improvement in technology (emphasis added by the examiner). An important consideration in determining whether a claim is directed to an improvement in technology is the extent to which the claim covers a particular solution to a problem or a particular way to achieve a desired outcome, as opposed to merely claiming the idea of a solution or outcome. It is important to note that in order for a method claim to improve computer functionality, the broadest reasonable interpretation of the claim must be limited to computer implementation. That is, a claim whose entire scope can be performed mentally, cannot be said to improve computer technology. Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 120 USPQ2d 1473 (Fed. Cir. 2016) (a method of translating a logic circuit into a hardware component description of a logic circuit was found to be ineligible because the method did not employ a computer and a skilled artisan could perform all the steps mentally). Similarly, a claimed process covering embodiments that can be performed on a computer, as well as embodiments that can be practiced verbally or with a telephone, cannot improve computer technology. See RecogniCorp, LLC v. Nintendo Co., 855 F.3d 1322, 1328, 122 USPQ2d 1377, 1381 (Fed. Cir. 2017) (process for encoding/decoding facial data using image codes assigned to particular facial features held ineligible because the process did not require a computer). To show that the involvement of a computer assists in improving the technology, the claims must recite the details regarding how a computer aids the method, the extent to which the computer aids the method, or the significance of a computer to the performance of the method.
Applicant fails to describe how the claims provide "an improved compilation technique". Moreover, the disclosure is silent regarding support for any supposed "improved compilation technique". That the claims recite the language “by a compiler and/or a compilation/programming tool” does nothing to make the claims eligible because the compiler is recited in a high-level generic manner which can be interpreted as merely generic computing components/software and is not significantly more than the recited abstract idea itself. Furthermore, the claims do not recite any “type of device” as argued by Applicant.
Finally, Applicant’s arguments fail to comply with 37 CFR 1.111(b)-(c) because they amount to a general allegation that the claims are eligible without specifically pointing out how the language of the claims makes the claims eligible in view of the rejections made. Further, they do not show how the amendments avoid such rejections. Applicant’s Remarks are only directed to the independent claims and fail to address any of the abstract idea rejections to the dependent claims. Even if an independent claim is deemed eligible then it does not necessarily mean that all of the dependent claims are also eligible. Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Nudelman et al. (US 2022/0188147) in at least the abstract disclose processing circuitry configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.
DeWitt, Jr. et al. (US 2003/0135719) in at least [0089] disclose that predication allows a compiler to convert control dependencies into data dependencies, thereby allowing the compiler to optimize instruction scheduling during compilation. For example, predicate registers are generally used in pairs, with one predicate register having the complement of the value of the other predicate register of the pair. Predication allows a processor to execute two execution paths in parallel in which a first predicate register "switches off" a first instruction branch while a second predicate register "switches on" a second instruction branch
Mody et al. (US 2015/0010052) disclose high throughput very large-scale integration architecture.
Lin (US 2020/0320392) disclose optimization processing for a neural network model.
Li et al. (US 2020/0293838) disclose scheduling computation graphs using neural networks.
Carroll et al. (US 2023/0031691) disclose training machine learning models.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner’s supervisor, Pierre Vital, can be reached at the following telephone number: (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated-interview-request-air-form.
/Adam Lee/Primary Examiner, Art Unit 2198 July 27, 2026
Prosecution Insights