Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
As per claim 1, Applicant is requested to clarify whether or not the second portion is to be scheduled for execution according to the schedule of the first portion or according to a different schedule. For the purposes of examination, the examiner interprets that the second portion is be scheduled according to any schedule. Appropriate correction is required.
Authorization for Internet Communications in a Patent Application
Applicant is encouraged to file an Authorization for Internet Communications in a Patent Application form (http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) along with the response to this office action to facilitate and expedite future communication between Applicant and the examiner. If the form is submitted then Applicant is requested to provide a contact email address in the signature block at the conclusion of the official reply.
Allowable Subject Matter
Claims 11-13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable over the prior art of record if rewritten to overcome the applicable rejection(s) and/or objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the examiner found neither prior art cited in its entirety, nor based on the prior art, found any motivation to combine any of the said prior art.
Applicant’s Reply Not Fully Responsive
The reply filed on 03/23/2026 is not fully responsive to the prior Office action because of the following omission(s) or matter(s): Applicant fails to interact with or address any of the examiner’s limitation-by-limitation analysis of the claims (especially the dependent claims) provided in the rejection above. Even if an independent claim is deemed eligible then it does not necessarily mean that all of the dependent claims are also eligible. The examiner highly encourages Applicant to review MPEP 2106 prior to submitting any subsequent response. See 37 CFR 1.111. The response appears to be bona fide, but through an apparent oversight or inadvertence, consideration of some matter or compliance with some requirement has been omitted. Applicant is required to supply the omission or correction to thereby provide a full subsequent response to the instant Office action.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (an abstract idea) without significantly more.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 1. A method, comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
wherein a second portion of the instructions of the program is to be scheduled for execution in the device (abstract idea mental process);
selecting, using a first artificial neural network, a placement of the next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device (abstract idea mental process), wherein the next instruction is in the second portion of the instructions of the program, and the placement is selected to comply with the execution dependency conditions in view of the schedule of the first portion of the instructions of the program represented by the second data (abstract idea mental process).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
receiving first data representative of execution dependency conditions of instructions of a program (generic computing components performing extra-solution activity of receiving data/information);
receiving second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuit units operable in parallel (generic computing components performing extra-solution activity of receiving data/information).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
receiving first data representative of execution dependency conditions of instructions of a program (extra-solution activity of receiving data/information);
receiving second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuits units operable in parallel (extra-solution activity of receiving data/information).
Claim 2. The method of claim 1, further comprising:
receiving third data identifying the next instruction selected from the second portion of the instructions of the program, the second portion to be scheduled for execution in the device (extra-solution activity of receiving data/information); and
applying the first data, the second data and the third data as input to the first artificial neural network (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea);
wherein the program is an assembly language program identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 3. The method of claim 2, wherein the device comprises a coarse grained reconfigurable array having a plurality of tiles operable in parallel as the plurality of circuit units respectively (generic computing components); wherein each of the tiles has a plurality of instruction slots for pipelined execution (generic computing components); and wherein the placement of the next instruction includes identification of a tile among the tiles, and a slot among instruction slots in the tile for execution of the next instruction (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 4. The method of claim 3, wherein the first data identifies dependency of execution of first instructions in receiving, as input, outputs generated from execution of second instructions (extra-solution activity of receiving data/information).
Claim 5. The method of claim 4, wherein the first data further identifies dependency of third instructions, scheduled to be executed in a respective tile, in accessing data at memory locations represented by memory variables implemented in the respective tile (extra-solution activity of retrieving data/information).
Claim 6. The method of claim 5, further comprising: generating, using a second artificial neural network, a performance measure of the selecting the placement of the next instruction from the plurality of possible placements (extra-solution activity of generating data/information).
Claim 7. The method of claim 6, further comprising: generating a plurality of samples, each respective sample among the samples specifying: a respective input to the first artificial neural network, the respective input identifying: a respective schedule of a respective portion of the instructions of the program; and a respective instruction to be scheduled in addition to the respective schedule; a respective placement of the respective instruction; and a respective performance measure for the respective placement (extra-solution activity of generating data/information).
Claim 8. The method of claim 7, further comprising: determining a count of cycles to complete execution, according to the respective schedule and the respective placement, of the respective portion of the instructions of the program and the respective instruction (abstract idea mental process); and calculating the respective performance measure based on the count of cycles (abstract idea mental process).
Claim 9. The method of claim 8, further comprising: training, using the samples and a technique of proximal policy optimization (PPO) of reinforcement learning to minimize a loss function, the first artificial neural network and the second artificial neural network (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 10. The method of claim 9, wherein the loss function is based on evaluating a first loss representing a reduction in performance measure resulting from the first artificial neural network selecting placements different from corresponding placements in the samples, and a second loss resulting from the second artificial neural network generating performance measures different from corresponding performance measures in the samples (abstract idea mental process).
Claim 11. The method of claim 10, wherein the second loss is based on a mean square error between performance measures generated by the second artificial neural network responsive to inputs specified in the samples and corresponding performance measures specified in the samples; and the first loss is based on a difference between a performance measure generated by the second artificial neural network and a corresponding performance measure in the samples, weighted by an exponential function of a logarithm function of a probability ratio that is equal to a ratio between: a probability of placements selected by the first artificial neural network responsive to inputs specified in the samples; and a probability of corresponding placements specified in the samples (abstract idea mental process).
Claim 12. The method of claim 11, further comprising: testing placement options to search for a valid schedule for at least portions of the instructions of the program (abstract idea mental process); wherein the plurality of samples are generated from the placement options being tested to search for the valid schedule (extra-solution activity of generating data/information).
Claim 13. The method of claim 12, wherein at least one of the placement options being tested is selected by the first artificial neural network before the training of the first artificial neural network and the second artificial neural network using the samples and the technique of proximal policy optimization (PPO) of reinforcement learning (merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
As per claim 14, it has similar limitations as claims 1-3 and is therefore rejected using the same rationale.
As per claim 15, it has similar limitations as claims 4-5 and is therefore rejected using the same rationale.
As per claim 16, it has similar limitations as claims 7 and 9-10 and is therefore rejected using the same rationale.
As per claim 17, it has similar limitations as claims 12-13 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 14 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 16 and is therefore rejected using the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over
Sideris et al. (US 11,276,137) (hereinafter Sideris as previously cited) in view of
Folliot et al. (US 2021/0342265) (hereinafter Folliot as previously cited) in view of
Nudelman et al. (US 2022/0188147) (hereinafter Nudelman).
As per claim 1, Sideris primarily teaches the invention as claimed including:
receiving first data representative of execution dependency conditions of instructions of a program (col. 4, ll. 9-19 and col. 5, ll. 15-29 execution dependency condition and col. 14, ll. 41-51 dependency conditions);
receiving second data representative of a schedule of a first portion of the instructions of the program for execution in a device (col. 6, ll. 6-19 thread groups to be scheduled for execution and col. 10, ll. 21-26 scheduling thread groups on execution unit for execution) having a plurality of circuit units operable in parallel (col. 16, ll. 49-54 functions can be carried out in parallel on a given processor and various processing stages may share processing circuits).
Sideris does not explicitly teach:
wherein a second portion of the instructions of the program is to be scheduled for execution in the device;
selecting, using a first artificial neural network, a placement of a next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device;
wherein the next instruction is in the second portion of the instructions of the program, and the placement is selected to comply with the execution dependency conditions in view of the schedule of the first portion of the instructions of the program represented by the second data.
However, Folliot teaches selecting, using a first artificial neural network (title and [0017] artificial neural network), a placement of a next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device ([0031] placements of intermediate data blocks of the subsequent i.e., next layers of the modified sequence are selected from the possible placements for these intermediate data blocks).
Folliot and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of Folliot because it would provide for an order of priority which is advantageously established between various possible placements of each intermediate data block. The highest order of priority is given to the placement that is arbitrarily considered to be the most optimized. For example, it may be advantageous to consider the interposition placement as the most optimized over the superposition placement and the forced allocation placement. This placement is considered to be the most optimized for a data block taken in isolation.
Sideris in view of Folliot do not explicitly teach:
wherein a second portion of the instructions of the program is to be scheduled for execution in the device;
wherein the next instruction is in the second portion of the instructions of the program, and the placement is selected to comply with the execution dependency conditions in view of the schedule of the first portion of the instructions of the program represented by the second data.
However, Nudelman teaches:
wherein a second portion of the instructions of the program is to be scheduled for execution in the device (claim 2 processing circuitry of network device configured to generate work requests based on the tasks, and to execute the work requests in accordance with the schedule);
wherein the next instruction is in the second portion of the instructions of the program ([0069] sequentially execute sequence of tasks and [0091]-[0096] sequence of following tasks), and the placement is selected to comply with the execution dependency conditions in view of the schedule of the first portion of the instructions of the program represented by the second data (abstract processing circuitry configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule and [0024]-[0025] determine a schedule for executing the tasks in compliance with the execution dependencies and determine a schedule that complies with the dependencies, e.g., to execute a work request in a one queue conditionally on execution of another work request in another queue).
Nudelman and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of Folliot in view of Nudelman because it would provide for a template specifying tasks and dependencies of the operation to be executed. Similar operations may be specified in a common template and selected using one or more parameters. Templates may be determined and stored, to be invoked multiple times as required. A stored template is reused without duplication thus saving storage space. By using parametrized templates, a given template can be used flexibly for specifying multiple similar operations. This results in an efficient interface between the host and network adapter, and reduces storage space required for storing the templates. Offloading the operations to the network adapter significantly reduces the overall execution latency of the operation, compared to implementation in software by the host CPU. The improvement is especially significant when the collective operation executed is dominated by communicating many small messages.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale et al. (US 2021/0072901) (hereinafter Kale as previously cited) in view of Mola (US 2024/0220397) (as previously cited).
As per claim 2, Sideris in view of Folliot in view of Nudelman do not explicitly teach:
receiving third data identifying the next instruction selected from the second portion of the instructions of the program, the second portion to be scheduled for execution in the device; and
applying the first data, the second data and the third data as input to the first artificial neural network;
wherein the program is an assembly language program identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows.
However, Kale teaches:
receiving third data identifying the next instruction selected from the second portion of the instructions of the program, the second portion to be scheduled for execution in the device ([0216] schedule command for execution); and
applying the first data, the second data and the third data as input to the first artificial neural network ([0013] apply the inputs to the ANN).
Kale and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale because it would provide a way for computations configured in a data storage device to be used to reduce the amount of data to be transmitted to processors to use or apply the ANN and/or reduce the computation tasks of the processors in evaluating the outputs of the ANN and/or in training the ANN. Such an arrangement can result in faster output from the data storage device and/or lower energy usage, since the data would not have to be moved in and out of the memory to a dedicated, standalone neural network accelerator. The computation capability of the data storage device in processing data related to the ANN enables the computer system to monitor the health of system components with reduced impact, or no impact, on the processing of mission critical tasks. Further, the computation capability of the data storage device can be used to accelerate the processing of the sensor data and thus improve the processing of mission critical tasks.
Sideris in view of Folliot in view of Nudelman in view of Kale do not explicitly teach wherein the program is an assembly language program identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows.
However, Mola teaches wherein the program is an assembly language program ([0034] assembly language) identifying data flows through memory locations represented by memory variables and identifying the instructions configured to transform data in the data flows ([0056]-[0057] identifying inputs/outputs for execution trace to generate a data flow dependency graph that links inputs/outputs through transforming activities).
Mola and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola because it would provide a way for data flow dependency graph generation, topological sorting, and input/output pairing which can reduce an amount of data that a computer processor analyzes/processes when determining which inputs are causal to outputs that differed between execution traces. In particular, they resulting system may only traverse the branches of data flow dependency graphs that are relevant to those outputs. This achieves a technical effect of efficiently identifying a root cause of at least one difference in the execution result of an entity in a manner that efficiently devotes computing resources to only a fraction of execution trace that is actually relevant to those differences. Additionally, by automatically identifying the root cause (i.e., inputs) that led to outputs differing between execution traces, this can efficiently pinpoint software faults, such as code bugs or invalid inputs while being more precise in pointing input differences that are causing the output differences (i.e., behavioral changes) than conventional analysis techniques.
Claims 3-4, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet et al. (US 2012/0303933) (hereinafter Manet as previously cited).
As per claim 3, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola do not explicitly teach wherein the device comprises a coarse grained reconfigurable array having a plurality of tiles operable in parallel as the plurality of circuit units respectively; wherein each of the tiles has a plurality of instruction slots for pipelined execution; and wherein the placement of the next instruction includes identification of a tile among the tiles, and a slot among instruction slots in the tile for execution of the next instruction.
However, Manet teaches wherein the device comprises a coarse grained reconfigurable array ([0016] coarse grain reconfigurable processing arrays) having a plurality of tiles operable in parallel as the plurality of circuit units respectively ([0124] tiles of a cluster execute a same thread in parallel); wherein each of the tiles has a plurality of instruction slots for pipelined execution ([0111] sub-execution blocks are executed in parallel on tiles via tile execution pipelines and [0144] pipelining between tiles); and wherein the placement of the next instruction includes identification of a tile among the tiles, and a slot among instruction slots in the tile for execution of the next instruction ([0101] an instruction slot per tile).
Manet and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet because it would provide advantages for when a local instruction memory captures a loop. In this case, the fetch power consumption is dominated by the local memory access power, which is far less than a cache access. Second, local branches in local code allow to capture loops embodying complex control paths which increases the number of reused loops. Third, executing a conditional branch in the local buffer using immediate address allows a very short pipeline which causes branches to have a very limited penalty. This allows to execute branch intensive code without incurring important performance loss or without using power-hungry mitigation techniques.
As per claim 4, Mola teaches wherein the first data identifies dependency of execution of first instructions in receiving, as input, outputs generated from execution of second instructions ([0066] input and output pairs associated with data flow dependency graphs are generated).
As per claim 14, it has similar limitations as claims 1-3 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 14 and is therefore rejected using the same rationale.
Claims 5, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming et al. (US 2019/0205284) (hereinafter Fleming as previously cited).
As per claim 5, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet do not explicitly teach wherein the first data further identifies dependency of third instructions, scheduled to be executed in a respective tile, in accessing data at memory locations represented by memory variables implemented in the respective tile.
However, Fleming teaches wherein the first data further identifies dependency of third instructions, scheduled to be executed in a respective tile, in accessing data at memory locations represented by memory variables implemented in the respective tile ([0285] second access request may thus be marked in the scheduler to require receipt of a memory dependency token caused by first access request before issuance of the second access request and the first and second access requests are to access the same address i.e., memory location in tile level memory).
Fleming and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming because it would provide for performance increases from parallel execution within a dense spatial array of processing elements where each processing element and/or network dataflow endpoint circuit utilized may perform its operations simultaneously, e.g., if input data is available. Efficiency increases may result from the efficiency of each processing element and/or network dataflow endpoint circuit, e.g., where each processing element 's operation (e.g., behavior) is fixed once per configuration (e.g., mapping) step and execution occurs on local data arrival at the processing element, e.g., without considering other fabric activity, and/or where each network dataflow endpoint circuit's operation (e.g., behavior) is variable (e.g., not fixed) when configured (e.g., mapped).
As per claim 15, it has similar limitations as claims 4-5 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby et al. (US 2021/0072921) (hereinafter Bielby as previously cited).
As per claim 6, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming do not explicitly teach generating, using a second artificial neural network, a performance measure of the selecting the placement of the next instruction from the plurality of possible placements.
However, Bielby teaches generating, using a second artificial neural network, a performance measure of the selecting the placement of the next instruction from the plurality of possible placements ([0227] ANN can self-organize to find optimization for data placement and [0249] generate training data by trying different data placement schemes for data objects recognized by the ANN for a data access pattern based on performances of the data placement schemes).
Bielby and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby because it would provide for intelligent wear-leveling with reduced write-amplification for data storage devices. For example, a data storage device can include an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized operation for wear leveling among memory cells in the data storage device. A controller can then be configured to perform the optimized operation for wear leveling based on the prediction.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne et al. (US 12,314,385) (hereinafter Beauchesne as previously cited) in view of Oswal et al. (US 2023/0297573) (hereinafter Oswal as previously cited).
As per claim 7, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby do not explicitly teach generating a plurality of samples, each respective sample among the samples specifying: a respective input to the first artificial neural network, the respective input identifying: a respective schedule of a respective portion of the instructions of the program; and a respective instruction to be scheduled in addition to the respective schedule; a respective placement of the respective instruction; and a respective performance measure for the respective placement.
However, Beauchesne teaches generating a plurality of samples (col. 16, ll. 12-13 points may be sampled to generate synthetic data points and col. 44, ll. 52-54 generating synthetic data that preferentially sample points), each respective sample among the samples specifying: a respective input to the first artificial neural network (col. 6, ll. 38-40 process record including features of a process are used to construct an input feature vector for consumption by machine learning models), the respective input identifying: a respective schedule of a respective portion of the instructions of the program (col. 38, ll. 5-7 configuration input specifies a schedule of code execution); and a respective instruction to be scheduled in addition to the respective schedule (col. 57, ll. 22-23 scheduling different jobs according to pipeline configurations).
Beauchesne and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne because it would provide for a machine learning pipeline system to detect outlier events in collected data of computer networks. The resulting system can improve upon conventional systems by using machine learning techniques to improve the speed and efficiency of processing large amounts of data and prioritizing investigations analysts should perform. The system can allow security analysts to better utilize their time and expertise to focus on the suspicious outlier events detected by the system, and drastically reduces the amount of time it takes to detect an attack or compromise, thus minimizing the chances of potentially crippling outcomes.
Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne do not explicitly teach a respective placement of the respective instruction; and a respective performance measure for the respective placement.
However, Oswal teaches a respective placement of the respective instruction; and a respective performance measure for the respective placement ([0056] performance benefit threshold that represents a minimum performance benefit value that the performance benefit of the data placement candidate must exceed in order to generate the one or more data placement commands).
Oswal and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal because it would provide a prediction-driven, rather than a trial-driven, approach to automatic data placement recommendations. Based at least in part on workload-specific features, dataset specific features, and a plurality of candidate keys, a set of candidate key combinations for partitioning data is generated. Using a machine learning model can determine a particular candidate key combination that optimizes query execution performance benefit based on the workload-specific features and the dataset specific features.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari et al. (US 2020/0160159) (hereinafter Azari as previously cited).
As per claim 8, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal do not explicitly teach determining a count of cycles to complete execution, according to the respective schedule and the respective placement, of the respective portion of the instructions of the program and the respective instruction; and calculating the respective performance measure based on the count of cycles.
However, Azari teaches determining a count of cycles to complete execution, according to the respective schedule and the respective placement, of the respective portion of the instructions of the program and the respective instruction; and calculating the respective performance measure based on the count of cycles ([0033] the performance of a low-power approximate multiplier is significantly improved and incorporated in the compute-intensive units while its execution time is data-dependent, and the number of clock cycles required to finish a single instruction depends on the magnitude of the instruction).
Azari and Sideris are both concerned with computer memory and task execution in a computing environment and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari because it would provide for neural network circuitry having a first plurality of logic cells that is interconnected to form neural network computation units that are configured to perform approximate computations. The neural network circuitry further includes a second plurality of logic cells that is interconnected to form a controller hierarchy that is interfaced with the neural network computation units to control pipelining of the approximate computations performed by the neural network computational units. The neural network computation units include approximate multipliers that are configured to perform approximate multiplications that comprise the approximate computations. The approximate multipliers include preprocessing units that reduce latency while maintaining accuracy.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He et al. (US 2022/0164657) (hereinafter He as previously cited).
As per claim 9, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari do not explicitly teach training, using the samples and a technique of proximal policy optimization (PPO) of reinforcement learning to minimize a loss function, the first artificial neural network and the second artificial neural network.
However, He teaches training, using the samples and a technique of proximal policy optimization (PPO) of reinforcement learning to minimize a loss function, the first artificial neural network and the second artificial neural network ([0044] training a neural network by minimizing a loss function based on a proximal policy optimization).
He and Sideris are both concerned with neural networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He because it would provide for a robustness and improvement of optimization algorithms such as Stochastic gradient descent (SGD) for training deep neural networks. In SGD, instead of taking one step along the computed gradient of the loss on all training samples, multiple steps are taken by computing the gradient of the loss of different random subsets of the training samples. SGD substantially lowers the computational cost for each update and also alleviates the impact of local optima and saddle points. In addition, numerous improvements to SGD, such as momentum, root-mean-squared prop, and adaptive momentum estimation, have been proposed and shown to be effective in resolving oscillation of gradient by smoothing it using different moving average formulas.
Claims 10, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He in view of O et al. (US 2021/0168195) (hereinafter O as previously cited).
As per claim 10, Sideris in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He do not explicitly teach wherein the loss function is based on evaluating a first loss representing a reduction in performance measure resulting from the first artificial neural network selecting placements different from corresponding placements in the samples, and a second loss resulting from the second artificial neural network generating performance measures different from corresponding performance measures in the samples.
However, O teaches wherein the loss function is based on evaluating a first loss representing a reduction in performance measure resulting from the first artificial neural network selecting placements different from corresponding placements in the samples, and a second loss resulting from the second artificial neural network generating performance measures different from corresponding performance measures in the samples ([0139] and [0154] compare accuracy and loss values of neural network models to determine which model results in improved performance).
O and Sideris are both concerned with neural networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sideris in view of in view of Folliot in view of Nudelman in view of Kale in view of Mola in view of Manet in view of Fleming in view of Bielby in view of Beauchesne in view of Oswal in view of Azari in view of He in view of O because it would provide a way to deploy an updated neural network model in such a way that the amount of the file transmitted by deploying only the information about the changed layer is reduced, thereby shortening the time required for deployment and training of the neural network model, and thus, an overload to the server may be prevented.
As per claim 16, it has similar limitations as claims 7 and 9-10 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 16 and is therefore rejected using the same rationale.
Response to Arguments
All of Applicant's arguments have been considered.
Applicant's arguments regarding the 35 U.S.C. 103 rejections are moot in view of the new grounds of rejection necessitated by Applicant’s amendments because the new grounds of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to the 35 U.S.C. 101 rejections have been fully considered but they are not persuasive.
In the Remarks on pg. 3, Applicant argues that the placement of instructions as claimed improves the technologies in computing. The examiner respectfully traverses. Applicant is reminded of In re Buchner, 929 F.2d 660, 661, 18 USPQ2d 1331, 1332 (Fed. Cir. 1991) (“expert’s opinion on the ultimate legal conclusion must be supported by something more than a conclusory statement”). It appears that Applicant is merely making a conclusory statement. Attorney argument is not evidence unless it is an admission, in which case, an examiner may use the admission in making a rejection (see MPEP § 2129 and § 2144.03 for a discussion of admissions as prior art). The arguments of counsel cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997) ("An assertion of what seems to follow from common experience is just attorney argument and not the kind of factual evidence that is required to rebut a prima facie case of obviousness."). See MPEP § 716.01(c) for examples of attorney statements which are not evidence and which must be supported by an appropriate affidavit or declaration.
Applicant asserts that the supposed improvement is in the claimed step of selecting a placement of a next instruction from a plurality of possible placements. Hence, Applicant is alleging that the supposed improvement is directed to an abstract idea of making a selection. Applicant’s attempt to show that the recited abstract idea itself is the improvement is not persuasive. An “improved” abstract idea (i.e., an improved way of making a selection) is still an abstract idea nonetheless and is not eligible for patent protection without significantly more recited in the claim. The examiner respectfully submits that an improvement in computer functionality is a reason for supporting the significance of the additional elements in a claim (Step 2A Prong Two and Step 2B, and not Step 1 or Step 2A Prong One). In other words, the “improvement” rationale is reserved for evaluating whether the additional elements and not the abstract idea itself amount to significantly more than the abstract idea itself (see MPEP 2106.05). Applicant is reminded that the abstract idea itself cannot be directed to an improvement in computer functionality (Step 2A Prong One). Rather only the additional elements can qualify as significantly more (i.e., the improvement) than the abstract idea itself (Step 2A Prong Two and Step 2B). Contrary to Applicant’s assertion, the claims are not directed to a specific asserted improvement in computer capabilities because no capability of the computer is being improved in any way.
If it is asserted that the invention improves upon conventional functioning of a computer, or upon conventional technology or technological processes, a technical explanation as to how to implement the invention should be present in the specification (see MPEP 2106.05(a)). That is, the disclosure must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement and the claim itself must reflect the improvement in technology (emphasis added by the examiner). An indication that the claimed invention provides an improvement can include a discussion in the specification that identifies a technical problem and explains the details of an unconventional technical solution expressed in the claim, or identifies technical improvements realized by the claim over the prior art. The claim must be evaluated to ensure the claim itself reflects the improvement in technology (emphasis added by the examiner). An important consideration in determining whether a claim is directed to an improvement in technology is the extent to which the claim covers a particular solution to a problem or a particular way to achieve a desired outcome, as opposed to merely claiming the idea of a solution or outcome. It is important to note that in order for a method claim to improve computer functionality, the broadest reasonable interpretation of the claim must be limited to computer implementation. That is, a claim whose entire scope can be performed mentally, cannot be said to improve computer technology. Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 120 USPQ2d 1473 (Fed. Cir. 2016) (a method of translating a logic circuit into a hardware component description of a logic circuit was found to be ineligible because the method did not employ a computer and a skilled artisan could perform all the steps mentally). Similarly, a claimed process covering embodiments that can be performed on a computer, as well as embodiments that can be practiced verbally or with a telephone, cannot improve computer technology. See RecogniCorp, LLC v. Nintendo Co., 855 F.3d 1322, 1328, 122 USPQ2d 1377, 1381 (Fed. Cir. 2017) (process for encoding/decoding facial data using image codes assigned to particular facial features held ineligible because the process did not require a computer). To show that the involvement of a computer assists in improving the technology, the claims must recite the details regarding how a computer aids the method, the extent to which the computer aids the method, or the significance of a computer to the performance of the method.
Applicant is reminded that the lack of prior art (i.e. novelty) does not avoid the problem of abstractness. While § 101 subject matter eligibility is a threshold test that typically precedes the novelty or obviousness inquiry (Bilski v. Kappos, 561 U.S. 593, 602 (2010)), it is a requirement separate from those other patentability inquiries (see Return Mail, Inc. v. USPS, 123 USPQ2d 1813, 1827 (Fed. Cir. 2017) and Mayo Collaborative Servs v. Prometheus Labs, Inc., 566 U.S. 66, 90 (2012)). It is important to recognize that the 35 U.S.C. 101 inquiry and other patentability inquiries might sometimes overlap. However, shifting the 35 U.S.C. 101 patent-eligibility inquiry entirely to the 35 U.S.C. 102 and 103 sections risks creating significantly greater legal uncertainty, and assumes that those sections can do work that they are not equipped to do. While material may be relevant to a novelty and obviousness analysis it may be the case where the material is not relevant to a determination of eligible subject matter. Eligibility and novelty are separate inquiries (see Affinity Labs of Tex., v. DirecTV, LLC, 120 USPQ2d 1201, 1208 Fed. Cir. 2016 and Synopsys, Inc. v. Mentor Graphics Corp., 120 USPQ2d 1473, 1483 Fed. Cir. 2016). Even assuming that a particular claimed feature was novel does not avoid the problem of abstractness. The search for an inventive concept under 35 U.S.C. 101 is thus distinct from demonstrating 35 U.S.C. 102 novelty. The novelty and nonobviousness of the claims under 35 U.S.C. 102 and 103 does not bear on whether the claims are directed to patent-eligible subject matter under 35 U.S.C. 101 (see 2016 U.S. Dist. LEXIS 107478, [WL] and *4). As made clear by the courts, the "‘novelty’ of any element or steps in a process, or even of the process itself, is of no relevance in determining whether the subject matter of a claim falls within the § 101 categories of possibly patentable subject matter." Intellectual Ventures I v. Symantec Corp., 838 F.3d 1307, 1315, 120 USPQ2d 1353, 1358 (Fed. Cir. 2016) (quoting Diamond v. Diehr, 450 U.S. at 188–89, 209 USPQ at 9). See also Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 1151, 120 USPQ2d 1473, 1483 (Fed. Cir. 2016) ("a claim for a new abstract idea is still an abstract idea. The search for a § 101 inventive concept is thus distinct from demonstrating § 102 novelty."). In addition, the search for an inventive concept is different from an obviousness analysis under 35 U.S.C. 103. See, e.g., BASCOM Global Internet v. AT&T Mobility LLC, 827 F.3d 1341, 1350, 119 USPQ2d 1236, 1242 (Fed. Cir. 2016) ("The inventive concept inquiry requires more than recognizing that each claim element, by itself, was known in the art. . . . [A]n inventive concept can be found in the non-conventional and non-generic arrangement of known, conventional pieces."). Specifically, lack of novelty under 35 U.S.C. 102 or obviousness under 35 U.S.C. 103 of a claimed invention does not necessarily indicate that additional elements are well-understood, routine, conventional elements. Because they are separate and distinct requirements from eligibility, patentability of the claimed invention under 35 U.S.C. 102 and 103 with respect to the prior art is neither required for, nor a guarantee of, patent eligibility under 35 U.S.C. 101. The distinction between eligibility (under 35 U.S.C. 101) and patentability over the art (under 35 U.S.C. 102 and/or 103) is further discussed in MPEP § 2106.05(d). A prior art search should not be necessary to resolve the inquiry as to whether an additional element (or combination of additional elements) is well-understood, routine, conventional activity. The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions. The Supreme Court’s cited rationale for considering even "just discovered" judicial exceptions as exceptions stems from the concern that "without this exception, there would be considerable danger that the grant of patents would ‘tie up’ the use of such tools and thereby ‘inhibit future innovation premised upon them.’" Myriad, 133 S. Ct. at 2116, 106 USPQ2d at 1978-79 (quoting Mayo, 566 U.S. at 86, 101 USPQ2d at 1971). See also Myriad, 133 S. Ct. at 2117, 106 USPQ2d at 1979 ("Groundbreaking, innovative, or even brilliant discovery does not by itself satisfy the §101 inquiry.").
Finally, Applicant’s arguments fail to comply with 37 CFR 1.111(b)-(c) because they amount to a general allegation that the claims are eligible without specifically pointing out how the language of the claims makes the claims eligible in view of the rejections made. Further, they do not show how the amendments avoid such rejections. Applicant’s Remarks are only directed to the independent claims and fail to address any of the abstract idea rejections to the dependent claims. Even if an independent claims is deemed eligible then it does not necessarily mean that all of the dependent claims are also eligible.
Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Mody et al. (US 2015/0010052) disclose high throughput very large scale integration architecture.
Lin (US 2020/0320392) disclose optimization processing for a neural network model.
Li et al. (US 2020/0293838) disclose scheduling computation graphs using neural networks.
Carroll et al. (US 2023/0031691) disclose training machine learning models.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached on 571-272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 April 10, 2026
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