DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Response to Election/Restriction on 05/01/2026. Applicant elects Species 1 (Figure 4), without traverse (Claims 1, 2, 15 and 16).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 15 and 16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Akifumi (JP 2022/036558; rejection based on English translation).
Regarding claim 1, Akifumi discloses (see figures 1-13) an electronic circuitry (figure 2, part electronic circuitry generated by 60) comprising: an input terminal (figure 2, part input terminal at right side of D2); a detection terminal (figure 2, part detection terminal at M1); a diode (figure 2, part D2) having a cathode (figure 2, part D2; cathode) connected to the input terminal (figure 2, part input terminal at right side of D2) and an anode (figure 2, part D2; anode) connected to the detection terminal (figure 2, part detection terminal at M1); a resistor (figure 2, part R4) connected between the detection terminal (figure 2, part detection terminal at M1) and a first reference voltage (figure 2, part first reference voltage at 40); and a capacitor (figure 2, part C1) connected between the detection terminal (figure 2, part detection terminal at M1) and a second reference voltage (figure 2, part second reference voltage at lower terminal of C1), wherein a voltage (figure 2, part voltage in detection terminal at M1) equal to a minimum value of a voltage applied to the input terminal (figure 2, part voltage applied to the input terminal at right side of D2) is outputted from the detection terminal (figure 2, part detection terminal at M1) (paragraphs [0026]-[0031]).
Regarding claim 15, Akifumi discloses (see figures 1-13) a power conversion device (figure 1) comprising: a power conversion circuit (figure 1, part power conversion circuit at 20 that includes arm pair of two SW connected to U-W phases) including: two switching elements that constitute an arm pair (figure 1, part first arm pair of two SW connected to U phase), and two drive circuits (figure 1, parts two Dr that control the first arm pair of two SW connected to U phase) configured to supply drive currents to the two switching elements respectively (figure 1, part two SW connected to U phase); and an electronic circuitry (figure 2, part electronic circuitry generated by 60) including: an input terminal (figure 2, part input terminal at right side of D2) connected to a connection point between the two switching elements (figures 1 and 2, part connection point between two SW connected to U phase), a detection terminal (figure 2, part detection terminal at M1); a diode (figure 2, part D2) having a cathode (figure 2, part D2; cathode) connected to the input terminal (figure 2, part input terminal at right side of D2) and an anode (figure 2, part D2; anode) connected to the detection terminal (figure 2, part detection terminal at M1); a resistor (figure 2, part R4) connected between the detection terminal (figure 2, part detection terminal at M1) and a first reference voltage (figure 2, part first reference voltage at 40); and a capacitor (figure 2, part C1) connected between the detection terminal (figure 2, part detection terminal at M1) and a second reference voltage (figure 2, part second reference voltage at lower terminal of C1), wherein a voltage (figure 2, part voltage in detection terminal at M1) equal to a minimum value of a voltage applied to the input terminal (figure 2, part voltage applied to the input terminal at right side of D2) is outputted from the detection terminal (figure 2, part detection terminal at M1) of the electronic circuitry (figure 2, part electronic circuitry generated by 60) (paragraphs [0026]-[0031]).
Regarding claim 16, Akifumi discloses everything claimed as applied above (see claim 15). Further, Akifumi discloses (see figures 1-13) three power conversion circuits(figure 1, part three power conversion at 20), each being the power conversion circuit (figure 1, part power conversion circuit at 20 that includes arm pair of two SW connected to U-W phases).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Akifumi (JP 2022/036558; rejection based on English translation), in view of Hakala (US 5,163,172).
Regarding claim 2, Akifumi discloses everything claimed as applied above (see claim 1). Further, Akifumi discloses (see figures 1-13) the second reference voltage (figure 2, part second reference voltage at lower terminal of C1) and the first reference voltage (figure 2, part first reference voltage at 40). However, Akifumi does not expressly disclose the second reference voltage is equal to the first reference voltage or higher than the first reference voltage.
Hakala teaches (see figures 1-3) the second reference voltage (figure 3, part second reference voltage at lower terminal of Cn) is equal to the first reference voltage (figure 3, part first reference voltage at lower terminal of Rn).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the first and second reference voltages at Akifumi with the reference voltages features as taught by Hakala and obtain the second reference voltage is equal to the first reference voltage or higher than the first reference voltage, because it provides more accurate measurement with a simple and reliable operation (column 2; lines 1-3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838