Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/20/2026 has been entered.
Response to Amendments / Arguments
Regarding the rejection(s) of claims under 35 USC 103:
Applicant’s arguments, field 03/20/2026, in view of the amended claims, have been fully considered and are partially persuasive.
Applicant first argues that "The cited Tamir on the other hand discusses counters for processes that are associated with memory addresses and looking at the counters for addresses associated with processes to determine behavior of the processes that are associated with memory addresses. The processes tracked in Tamir comprise code executing at an address that produces events… Thus, the processes in Tamir are not processing elements on a SOC that connect to a network-on-chip." In response, it is noted that Tamir is not limited to monitoring software processes via instruction memory addresses. Specifically, Tamir [0062] discloses a computer system comprising "multiple CPUs (420, 430, etc.) communicatively coupled to Converged Security Management Engine (CSME) 450… which may in turn be connected to a Network Interface Card… (NIC) 470," which constitutes multiple hardware processing elements. Further, Tamir [0049] explicitly discloses "uncore counters to characterize malware (outside the core)," including "Ratio of MMIO and PCI to memory bandwidth to detect additional IO" and "Average sleeping patterns in C states," which measure activity at hardware subsystems independent of any software process attribution. Therefore, Tamir's disclosure is not limited to process-address-attributed counters as Applicant contends.
Secondly, Applicant argues that "This discussion of counters associated with interrupts that correspond to different types of events does not teach the amended requirement of counters for different processing elements connected to a network-on-chip that measure different types of processing activities for different processing elements connected to the network-on-chip." In response, it is noted that Tamir [0029]-[0049] discloses a counter taxonomy that spans multiple physically distinct hardware blocks, including CPU core PMU counters, cache hierarchy counters, TLB unit counters, power management counters, and uncore/IO counters. These counters are physically located at different hardware processing elements and measure different types of processing activities at those elements. Applicant's argument conflates the physical location of the counters with the method used to attribute events to software processes; the claim recites the former, and Tamir discloses counters located at different hardware blocks measuring different activity types regardless of any additional process-attribution layer. Applicant argues that "The cited Amram discusses the use of an AI processor to detect hardware anomalies in the operations of a separate stylus pen and touch screen. Thus, the anomaly detector of Amram is separate from the component that is being analyzed, a stylus pen and touch screen. The cited Amram does not teach or mention deploying its anomaly detector in a SoC to process counter values from counters for processing elements, in a network-on-chip, in the same SOC." In response, it is noted that Amram explicitly contemplates deployment of the anomaly detector within an SoC of the host device that performs the monitoring. Specifically, Amram at paragraph [0060] states that "The signal cleaner 23, the anomaly detector 24, the anomaly analyzer 240... may be implemented in an application specific integrated circuit (ASIC), a system on chip (SOC), a field programmable gate array (FPGA), a micro-processing unit, etc.," and paragraph [0026] further states that "the at least one AI processor may be a single processor (e.g. a (main) CPU of the host device where the AI algorithm is run on the host device." Accordingly, Amram teaches deployment of the anomaly detector within the same SoC that processes the monitored signals.
Additionally, Applicant attacks Amram individually rather than the Amram-Tamir combination as set forth in the rejection. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. However, applicants argument that neither Amram or Tamir teach “wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip” is persuasive therefore the rejection is withdrawn however the rejection is further upheld in view of Charles et al. (“Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs”.)
DETAILED ACTION
This is a reply to the arguments filed on 03/20/2026, in which, claims 1-4, 6-13 and 15-23 are pending. Claims 1, 12, and 17 are independent. Claims 5 and 14 are cancelled.
When making claim amendments, the applicant is encouraged to consider the references in their entireties, including those portions that have not been cited by the examiner and their equivalents as they may most broadly and appropriately apply to any particular anticipated claim amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 12-13 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Amram et al. (US 20230359307 A1, referred to as Amram), in view of Tamir et al. (US 20160328561 A1, referred to as Tamir) in further view of Charles et al. (“Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs”, referred to as Charles).
In reference to claim 1, A computer program product for detecting an anomaly in system-on-chip, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein that is executable to perform operations, the operations comprising (Amram: [0099]-[0102] Provides for a computer program embodied on computer-readable storage with code that performs anomaly detection methods.)
Training an anomaly detector to classify determined values during measurement periods occurring during the test workload as non-anomalous activity (Amram: [0035]-[0041] Provides for training an anomaly detector through both supervised and unsupervised learning approaches. It explicitly mentions providing "desired input signals without anomalies" during a learning phase.)
Deploying the trained anomaly detector within the system-on-chip to process values for the processing elements on the system-on-chip to classify the values as anomalous or non-anomalous (Amram: [0025]-[0032] Provides for deploying the trained AI anomaly detector within a processor/system to process signals and classify them as valid (non-anomalous) or anomalous.)
Performing a mitigation action in response to the deployed trained anomaly detector detecting the anomalous activity within the system-on-chip (Amram: [0031] and [0044]-[0046] Provides for performing mitigation actions in response to detecting anomalies, including dropping bad signals, applying correction algorithms, and implementing estimation or interpolation processes.)
Amran doesn't explicitly disclose that the determined values are counter values and determines counter values from counters for processing elements in the system-on-chip during a test workload, wherein a counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period. However, Tamir teaches:
Determining counter values from counters for processing elements in the system-on-chip during a test workload, wherein a counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period (Tamir: [0029]-[0030], [0062] and [0049] Provides for determining counter values from hardware counters that indicate activity of processing elements during measurement periods. It details numerous counters that measure various activities at processing elements. For the sake of completeness Tamir also teaches [0050]-[0051] Provides for using machine learning to define normal or expected (non-anomalous) behavior based on counter values. Tamir [0053]-[0054] Provides for deploying a behavioral model (fingerprint) to detect anomalies by comparing runtime behavior with established patterns. Tamir [0071]-[0073] Provides for performing mitigation actions in response to detecting anomalous activity.)
Wherein the counters for at least two of the processing elements measure different types of processing activities (Tamir: [0030] and [0078] Provides for multiple different types of hardware counters measuring different processing activities (cache events, branch events, memory events, etc.).)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram, which provides a method for anomaly detection in system-on-chip environments using trained anomaly detectors that classify signals and perform mitigation actions, with the teachings of Tamir, which introduces the use of hardware performance counters that measure processing element activity during measurement periods. One of ordinary skill in the art would recognize the ability to incorporate Tamir's counter-based measurement data into Amram's anomaly detection system to provide more concrete and quantifiable metrics for anomaly detection. One of ordinary skill in the art would be motivated to make this modification in order to enhance anomaly detection precision by using objective activity measurements from hardware counters.
Amram in view of Tamir do not explicitly disclose Wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip. However, Charles discloses: Wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip (Charles: p. 4510, Fig. 1; p. 4517, Fig. 13; p. 4520–4521, Section VI and Fig. 21 Provides for processing elements (IP cores) interconnected by a NoC within an SoC, each IP connected to a router on the NoC.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure different types of processing element activity, with the teachings of Charles, which introduces interconnecting processing elements through a network-on-chip architecture within a system-on-chip where each processing element connects to a router on the network-on-chip. One of ordinary skill in the art would recognize the ability to incorporate Charles's network-on-chip interconnect architecture into the combined anomaly detection system to enable comprehensive monitoring of both processing element activity and inter-element communication. One of ordinary skill in the art would be motivated to make this modification in order to provide a more complete view of system-on-chip behavior by monitoring activity across the entire interconnect.
In reference to claim 2, The computer program product of claim 1, wherein the anomaly detector implements an unsupervised or semi-supervised machine learning model, wherein the operations further comprise: repeatedly retraining the anomaly detector while deployed within the system-on-chip to classify as non-anomalous counter values resulting from known non-anomalous activity and counter values whose classification by the anomaly detector as anomalous comprises a false positive classification (Amram: [0040]-[0043] Provides for using unsupervised learning for the anomaly detector. It also describes reinforcement learning with penalties for false positives (erroneously qualifying valid signals as anomalies) and active learning where the detector requests more data when experiencing excessive detections.)
In reference to claim 3, The computer program product of claim 1, wherein the mitigation action comprises: determining a process, executing in the system-on-chip, producing activity in the system-on-chip that results in the counter values in the counters being classified as anomalous; determining whether the determined process is an authorized process; and
quarantining the determined process in response to determining the determined process is not authorized (Amram: [0044]-[0051] and [0067]-[0070] Provides for determining the cause of an anomaly by analyzing patterns across devices and taking specific mitigation actions based on the type of anomaly detected.)
In reference to claim 4, The computer program product of claim 1, wherein the operations further comprise: determining counter values classified as anomalous activity that is a false positive; and training the anomaly detector to classify the determined counter values as non-anomalous activity (Amram: [0040]-[0043] Provides for false positives and describes specific learning approaches to address them. The reinforcement learning method explicitly penalizes the anomaly detector when it "erroneously qualifies a valid position signal as an anomaly signal" (i.e., a false positive), which would train the detector not to make similar errors in the future.)
In reference to claim 12, A system-on-chip for detecting an anomaly, comprising: a plurality of processing elements; an anomaly defense tile executing code to perform operations (Amram: [0099]-[0102] Provides for a computer program embodied on computer-readable storage with code that performs anomaly detection methods.)
Training an anomaly detector to classify determined values during measurement periods occurring during the test workload as non-anomalous activity (Amram: [0035]-[0041] Provides for training an anomaly detector through both supervised and unsupervised learning approaches. It explicitly mentions providing "desired input signals without anomalies" during a learning phase.)
Deploying the trained anomaly detector within the system-on-chip to process values for the processing elements on the system-on-chip to classify the values as anomalous or non-anomalous (Amram: [0025]-[0032] Provides for deploying the trained AI anomaly detector within a processor/system to process signals and classify them as valid (non-anomalous) or anomalous.)
Performing a mitigation action in response to the deployed trained anomaly detector detecting the anomalous activity within the system-on-chip (Amram: [0031] and [0044]-[0046] Provides for performing mitigation actions in response to detecting anomalies, including dropping bad signals, applying correction algorithms, and implementing estimation or interpolation processes.)
Amran doesn't explicitly disclose that the determined values are counter values and determines counter values from counters for processing elements in the system-on-chip during a test workload, wherein a counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period. However, Tamir teaches:
Determining counter values from counters for processing elements in the system-on-chip during a test workload, wherein a counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period (Tamir: [0029]-[0030], [0062] and [0049] Provides for determining counter values from hardware counters that indicate activity of processing elements during measurement periods. It details numerous counters that measure various activities at processing elements. For the sake of completeness Tamir also teaches [0050]-[0051] Provides for using machine learning to define normal or expected (non-anomalous) behavior based on counter values. Tamir [0053]-[0054] Provides for deploying a behavioral model (fingerprint) to detect anomalies by comparing runtime behavior with established patterns. Tamir [0071]-[0073] Provides for performing mitigation actions in response to detecting anomalous activity.)
Wherein the counters for at least two of the processing elements measure different types of processing activities (Tamir: [0030] and [0078] Provides for multiple different types of hardware counters measuring different processing activities (cache events, branch events, memory events, etc.).)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram, which provides a method for anomaly detection in system-on-chip environments using trained anomaly detectors that classify signals and perform mitigation actions, with the teachings of Tamir, which introduces the use of hardware performance counters that measure processing element activity during measurement periods. One of ordinary skill in the art would recognize the ability to incorporate Tamir's counter-based measurement data into Amram's anomaly detection system to provide more concrete and quantifiable metrics for anomaly detection. One of ordinary skill in the art would be motivated to make this modification in order to enhance anomaly detection precision by using objective activity measurements from hardware counters.
Amram in view of Tamir do not explicitly disclose Wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip. However, Charles discloses: Wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip (Charles: p. 4510, Fig. 1; p. 4517, Fig. 13; p. 4520–4521, Section VI and Fig. 21 Provides for processing elements (IP cores) interconnected by a NoC within an SoC, each IP connected to a router on the NoC.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure different types of processing element activity, with the teachings of Charles, which introduces interconnecting processing elements through a network-on-chip architecture within a system-on-chip where each processing element connects to a router on the network-on-chip. One of ordinary skill in the art would recognize the ability to incorporate Charles's network-on-chip interconnect architecture into the combined anomaly detection system to enable comprehensive monitoring of both processing element activity and inter-element communication. One of ordinary skill in the art would be motivated to make this modification in order to provide a more complete view of system-on-chip behavior by monitoring activity across the entire interconnect.
In reference to claim 13, The system-on-chip of claim 12, wherein the operations further comprise: determining counter values classified as anomalous activity that is a false positive; and training the anomaly detector to classify the determined counter values as non-anomalous activity (Amram: [0040]-[0043] Provides for false positives and describes specific learning approaches to address them. The reinforcement learning method explicitly penalizes the anomaly detector when it "erroneously qualifies a valid position signal as an anomaly signal" (i.e., a false positive), which would train the detector not to make similar errors in the future.)
In reference to claim 17, A method for detecting an anomaly in system-on-chip (Amram: [0099]-[0102] Provides for a computer program embodied on computer-readable storage with code that performs anomaly detection methods.)
Training an anomaly detector to classify determined values during measurement periods occurring during the test workload as non-anomalous activity (Amram: [0035]-[0041] Provides for training an anomaly detector through both supervised and unsupervised learning approaches. It explicitly mentions providing "desired input signals without anomalies" during a learning phase.)
Deploying the trained anomaly detector within the system-on-chip to process values for the processing elements on the system-on-chip to classify the values as anomalous or non-anomalous (Amram: [0025]-[0032] Provides for deploying the trained AI anomaly detector within a processor/system to process signals and classify them as valid (non-anomalous) or anomalous.)
Performing a mitigation action in response to the deployed trained anomaly detector detecting the anomalous activity within the system-on-chip (Amram: [0031] and [0044]-[0046] Provides for performing mitigation actions in response to detecting anomalies, including dropping bad signals, applying correction algorithms, and implementing estimation or interpolation processes.)
Amran doesn't explicitly disclose that the determined values are counter values and determines counter values from counters for processing elements in the system-on-chip during a test workload, wherein a counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period. However, Tamir teaches:
Determining counter values from counters for processing elements in the system-on-chip during a test workload, wherein a counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period (Tamir: [0029]-[0030], [0062] and [0049] Provides for determining counter values from hardware counters that indicate activity of processing elements during measurement periods. It details numerous counters that measure various activities at processing elements. For the sake of completeness Tamir also teaches [0050]-[0051] Provides for using machine learning to define normal or expected (non-anomalous) behavior based on counter values. Tamir [0053]-[0054] Provides for deploying a behavioral model (fingerprint) to detect anomalies by comparing runtime behavior with established patterns. Tamir [0071]-[0073] Provides for performing mitigation actions in response to detecting anomalous activity.)
Wherein the counters for at least two of the processing elements measure different types of processing activities (Tamir: [0030] and [0078] Provides for multiple different types of hardware counters measuring different processing activities (cache events, branch events, memory events, etc.).)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram, which provides a method for anomaly detection in system-on-chip environments using trained anomaly detectors that classify signals and perform mitigation actions, with the teachings of Tamir, which introduces the use of hardware performance counters that measure processing element activity during measurement periods. One of ordinary skill in the art would recognize the ability to incorporate Tamir's counter-based measurement data into Amram's anomaly detection system to provide more concrete and quantifiable metrics for anomaly detection. One of ordinary skill in the art would be motivated to make this modification in order to enhance anomaly detection precision by using objective activity measurements from hardware counters.
Amram in view of Tamir do not explicitly disclose Wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip. However, Charles discloses: Wherein the processing elements are interconnected via a network-on chip included in the system-on-chip, and wherein the processing elements are connected to the network-on-chip (Charles: p. 4510, Fig. 1; p. 4517, Fig. 13; p. 4520–4521, Section VI and Fig. 21 Provides for processing elements (IP cores) interconnected by a NoC within an SoC, each IP connected to a router on the NoC.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure different types of processing element activity, with the teachings of Charles, which introduces interconnecting processing elements through a network-on-chip architecture within a system-on-chip where each processing element connects to a router on the network-on-chip. One of ordinary skill in the art would recognize the ability to incorporate Charles's network-on-chip interconnect architecture into the combined anomaly detection system to enable comprehensive monitoring of both processing element activity and inter-element communication. One of ordinary skill in the art would be motivated to make this modification in order to provide a more complete view of system-on-chip behavior by monitoring activity across the entire interconnect.
In reference to claim 18, The method of claim 17, further comprising: determining counter values classified as anomalous activity that is a false positive; and training the anomaly detector to classify the determined counter values as non-anomalous activity (Amram: [0040]-[0043] Provides for false positives and describes specific learning approaches to address them. The reinforcement learning method explicitly penalizes the anomaly detector when it "erroneously qualifies a valid position signal as an anomaly signal" (i.e., a false positive), which would train the detector not to make similar errors in the future.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-11, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Amram et al. (US 20230359307 A1, referred to as Amram), in view of Tamir et al. (US 20160328561 A1, referred to as Tamir) in further view of Hoover et al. (US 20090282227 A1, referred at Hoover).
In reference to claim 6, The computer program product of claim 1, wherein the different counters comprise: a counter for an accelerator that measures processing cycles during a measurement period; a counter for a memory tile in the system-on-chip indicating a number of memory requests to the memory tile; a counter for an Input/Output tile that measures packets-in and packets-out of the Input/output tile; and a general purpose counter for tiles that measure network-on-chip packets-in and packets-out of the tiles (Hoover: [0075]-[0080] Provides for counters for various aspects of system operation, including processor activity, memory traffic, and packet transmission.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure processing element activity, with the teachings of Hoover, which introduces specialized counters for measuring different types of network-on-chip traffic activity at different processing elements. One of ordinary skill in the art would recognize the ability to incorporate Hoover's diverse counter types into the combined anomaly detection system to provide more granular and comprehensive monitoring of network-on-chip behavior. One of ordinary skill in the art would be motivated to make this modification in order to enable more sophisticated anomaly detection by monitoring multiple types of network traffic activity.
In reference to claim 7, The computer program product of claim 1,, wherein the network-on-chip includes routers comprising hardware on the network-on-chip to interconnect the processing elements, and wherein the counters are implemented in the routers for the processing elements (Hoover: [0026]-[0031], [0049] and [0077]-[0079] Provides for the NoC is implemented on a chip (system-on-chip), that the NoC includes routers as hardware interconnecting the processing elements (IP blocks), and that counters are specifically implemented in the routing logic of these routers.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure processing element activity, with the teachings of Hoover, which introduces implementing counters within network-on-chip routers that serve as hardware interconnects between processing elements. One of ordinary skill in the art would recognize the ability to incorporate Hoover's router-based counter implementation into the combined anomaly detection system to provide direct monitoring at the interconnection points. One of ordinary skill in the art would be motivated to make this modification in order to capture network traffic data at the optimal location where all communication between processing elements passes through
In reference to claim 8, The computer program product of claim 7, wherein the operations further comprise: reading, by the anomaly detector, the counter values for the processing elements from the routers for the processing elements (Hoover: [0071]-[0081] Provides for the process of reading counter values from routers for processing elements.)
In reference to claim 9, The computer program product of claim 7, wherein the routers form at least one first network plane and at least one second network plane separate from the at least one first network plane, wherein the processing elements use the at least one first network plane to communicate during workload operations, and wherein the at least one second network plane is used to read the counter values from the counters in the routers that are provided to the anomaly detector (Hoover: [0050]-[0053] and [0079] Provides for a network-on-chip with multiple virtual communication channels implemented by the routers, where each virtual channel is characterized by a communication type.)
In reference to claim 10, The computer program product of claim 1, wherein the computer readable program code is executed by a processing core tile dedicated to implementing the anomaly detector, and wherein a dedicated anomaly tile stores the anomaly detector loaded into the processing core tile and the determined counter values (Hoover: [0035] and [0071]-[0073] Provides for a dedicated processor for monitoring and analysis functions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure processing element activity, with the teachings of Hoover, which introduces dedicated processing tiles for monitoring and analysis functions. One of ordinary skill in the art would recognize the ability to incorporate Hoover's dedicated processor architecture into the combined anomaly detection system to isolate monitoring functions from operational processing elements. One of ordinary skill in the art would be motivated to make this modification in order to prevent anomaly detection overhead from impacting the performance of functional processing elements.
In reference to claim 11, The computer program product of claim 1, wherein the computer readable program code and the anomaly detector are implemented in a hardware accelerator tile of the system-on-chip having a dedicated memory tile to store the determined counter values (Hoover: [0019]-[0021] and [0030]-[0035] Provides for NOC coprocessors that are "optimized to accelerate particular data processing tasks,".)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure processing element activity, with the teachings of Hoover, which introduces hardware accelerator tiles with dedicated memory for specialized data processing tasks. One of ordinary skill in the art would recognize the ability to incorporate Hoover's hardware accelerator architecture into the combined anomaly detection system to optimize the performance of anomaly detection operations. One of ordinary skill in the art would be motivated to make this modification in order to accelerate anomaly detection processing through specialized hardware optimized for the computational patterns of machine learning inference
In reference to claim 15, The system-on-chip of claim 12, wherein the network-on-chip includes routers comprising hardware on the network-on-chip to interconnect the processing elements, and wherein the counters are implemented in the routers for the processing elements (Hoover: [0026]-[0031], [0049] and [0077]-[0079] Provides for the NoC is implemented on a chip (system-on-chip), that the NoC includes routers as hardware interconnecting the processing elements (IP blocks), and that counters are specifically implemented in the routing logic of these routers.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure processing element activity, with the teachings of Hoover, which introduces implementing counters within network-on-chip routers that serve as hardware interconnects between processing elements. One of ordinary skill in the art would recognize the ability to incorporate Hoover's router-based counter implementation into the combined anomaly detection system to provide direct monitoring at the interconnection points. One of ordinary skill in the art would be motivated to make this modification in order to capture network traffic data at the optimal location where all communication between processing elements passes through
In reference to claim 16, The system-on-chip of claim 15, wherein the routers form at least one first network plane and at least one second network plane separate from the at least one first network plane, wherein the processing elements use the at least one first network plane to communicate during workload operations, and wherein the at least one second network plane is used to read the counter values from the counters in the routers that are provided to the anomaly detector (Hoover: [0050]-[0053] and [0079] Provides for a network-on-chip with multiple virtual communication channels implemented by the routers, where each virtual channel is characterized by a communication type.)
In reference to claim 19, The method of claim 17, wherein the network-on-chip includes routers comprising hardware on the network-on-chip to interconnect the processing elements, and wherein the counters are implemented in the routers for the processing elements (Hoover: [0026]-[0031], [0049] and [0077]-[0079] Provides for the NoC is implemented on a chip (system-on-chip), that the NoC includes routers as hardware interconnecting the processing elements (IP blocks), and that counters are specifically implemented in the routing logic of these routers.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure processing element activity, with the teachings of Hoover, which introduces implementing counters within network-on-chip routers that serve as hardware interconnects between processing elements. One of ordinary skill in the art would recognize the ability to incorporate Hoover's router-based counter implementation into the combined anomaly detection system to provide direct monitoring at the interconnection points. One of ordinary skill in the art would be motivated to make this modification in order to capture network traffic data at the optimal location where all communication between processing elements passes through
In reference to claim 20, The method of claim 19, wherein the routers form at least one first network plane and at least one second network plane separate from the at least one first network plane, wherein the processing elements use the at least one first network plane to communicate during workload operations, and wherein the at least one second network plane is used to read the counter values from the counters in the routers that are provided to the anomaly detector (Hoover: [0050]-[0053] and [0079] Provides for a network-on-chip with multiple virtual communication channels implemented by the routers, where each virtual channel is characterized by a communication type.)
In reference to claim 21, The computer program product of claim 1, wherein the measured different types of processing activities measured by the counters are selected from the group consisting of processing cycles at one of the processing elements, number of memory requests to one of the processing elements, and packets-in and packets-out at one of the processing elements (Hoover: [0074]-[0080] Provides for three processing activity types: compute density measures processing cycles per processor cycle, cache miss monitoring provides for memory requests to processing elements, and packet transmission counters provide for packets-in and packets-out at processing elements.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure different types of processing element activities, with the teachings of Hoover, which introduces specific counter types for measuring processing cycles, memory requests, and packet transmission activities. One of ordinary skill in the art would recognize the ability to incorporate Hoover's specific counter implementations into the combined anomaly detection system to provide comprehensive monitoring of critical system-on-chip metrics. One of ordinary skill in the art would be motivated to make this modification in order to enable thorough anomaly detection by monitoring important performance indicators that reveal system behavior.
In reference to claim 22, The system-on-chip of claim 12, wherein the measured different types of processing activities measured by the counters are selected from the group consisting of processing cycles at one of the processing elements, number of memory requests to one of the processing elements, and packets-in and packets-out at one of the processing elements (Hoover: [0074]-[0080] Provides for three processing activity types: compute density measures processing cycles per processor cycle, cache miss monitoring provides for memory requests to processing elements, and packet transmission counters provide for packets-in and packets-out at processing elements.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure different types of processing element activities, with the teachings of Hoover, which introduces specific counter types for measuring processing cycles, memory requests, and packet transmission activities. One of ordinary skill in the art would recognize the ability to incorporate Hoover's specific counter implementations into the combined anomaly detection system to provide comprehensive monitoring of critical system-on-chip metrics. One of ordinary skill in the art would be motivated to make this modification in order to enable thorough anomaly detection by monitoring important performance indicators that reveal system behavior.
In reference to claim 23, The method of claim 17, wherein the measured different types of processing activities measured by the counters are selected from the group consisting of processing cycles at one of the processing elements, number of memory requests to one of the processing elements, and packets-in and packets-out at one of the processing elements (Hoover: [0074]-[0080] Provides for three processing activity types: compute density measures processing cycles per processor cycle, cache miss monitoring provides for memory requests to processing elements, and packet transmission counters provide for packets-in and packets-out at processing elements.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Amram in view of Tamir, which together provide a method for anomaly detection in system-on-chip environments using hardware performance counters to measure different types of processing element activities, with the teachings of Hoover, which introduces specific counter types for measuring processing cycles, memory requests, and packet transmission activities. One of ordinary skill in the art would recognize the ability to incorporate Hoover's specific counter implementations into the combined anomaly detection system to provide comprehensive monitoring of critical system-on-chip metrics. One of ordinary skill in the art would be motivated to make this modification in order to enable thorough anomaly detection by monitoring important performance indicators that reveal system behavior.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
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/A.E.S./Examiner, Art Unit 2432
/Jeffrey Nickerson/Supervisory Patent Examiner, Art Unit 2432
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