Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "load" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show "the load" as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0018 - recites "two terminals of the second switch element T2 are coupled to the power supply VDD and the second control transistor TB respectively". Regarding applicant's elected Fig. 4, the top terminal of T2 is directly coupled to TB, and coupled to VDD through TB and TD. Does the statement mean to say that T2 is coupled to the reference potential?
Paragraph 0032 (line 1) - there is a double "the" in the first sentence.
Paragraph 0032 (lines 5-6) - in describing Fig. 2B, it appears that the sentence "The first control transistor TA is also turned on", should be stating that TA should be turned off, as shown in Fig. 2B.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 11, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (line 14) recites "and a load, and configured to selectively charge or discharge the load". It is unclear where this load is shown in the Applicant's elected
Fig. 4.
Claims 2-10 inherit the defects of the associated parent claim and/or any intervening claims.
Claim 11 (line 11) recites " and a load, so as to selectively charge or discharge the load". It is unclear where this load is shown in the Applicant's elected Fig. 4.
Claims 12-18 inherit the defects of the associated parent claim and/or any intervening claims.
Claim 19 (lines 8-14) recites "a second inverter circuit comprising a second switch element and a second control transistor, wherein a first terminal of the second control transistor is coupled to the power supply through the second switch element, a second terminal of the second control transistor is coupled to the reference potential, so that a second control node between the second switch element and the second control transistor is charged by the power supply, or is discharged by the second control transistor". From the specification and the applicant's elected Fig. 4, a second inverter circuit (120) comprising a second switch element (T2) and a second control transistor (TB), wherein a first terminal of the second control transistor (TB) is coupled to the power supply (VDD) through the second switch element (T2), a second terminal of the second control transistor (TB) is coupled to the reference potential (ground), so that a second control node (N2) between the second switch element (T2) and the second control transistor (TB) is charged by the power supply (VDD), or is discharged by the second control transistor (TB). The specification defines power supply as VDD and defines reference potential as ground. It is unclear, per applicant's elected Fig. 4, how the top terminal of TB is coupled to VDD through T2 (a first terminal of the second control transistor is coupled to the power supply through the second switch element).
Claim 20 inherits the defects of the associated parent claim and/or any intervening claims.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sommer (US 20050156624 A1); hereinafter Sommer.
Regarding Claim 19, as best understood, Sommer discloses a charging/discharging control circuit [Fig. 5], comprising: a first inverter circuit [211/221/222/212] comprising a first switch element [211] and a first control transistor [222], wherein a first terminal of the first control transistor [top terminal of 222] is coupled to a power supply [VDD] through the first switch element, a second terminal of the first control transistor [bottom terminal of 222] is coupled to a reference potential [GND], so that a first control node [node between 221/222] between the first switch element and the first control transistor is charged by the power supply [pull-up by 211/221 to VDD], or is discharged by the first control transistor [pull-down by 212/222 to GND]; and a second inverter circuit [411/421/422/412] comprising a second switch [411] element and a second control transistor [422], wherein a first terminal of the second control transistor [top terminal of 422] is coupled to the power supply through the second switch element, a second terminal of the second control transistor [bottom terminal of 422] is coupled to the reference potential, so that a second control node [402] between the second switch element and the second control transistor is charged by the power supply [pull-up to VDD], or is discharged by the second control transistor [pull-down to GND].
Regarding Claim 20, as best understood, Sommer discloses the charging/discharging control circuit of claim 19, wherein the first inverter circuit is configured to generate a first control voltage on the first control node [output of first control node] according to a threshold voltage of the first control transistor [threshold voltage of 222]; and the second inverter circuit is configured to generate a second control voltage on the second control node [output of 402] according to a threshold voltage of the second control transistor [threshold voltage of 422].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Sommer, in view of Kuroda (US 20100013542 A1); hereinafter Sommer, in view of Kuroda.
Regarding Claim 1, as best understood, Sommer discloses a charging/discharging control circuit [Fig. 5], comprising: a first inverter circuit [211/221/222/212 (top 23) within bottom box] comprising a first switch element [211] and a first control transistor [222], wherein a first control node is between the first switch element and the first control transistor [node between 221/222], and the first inverter circuit is configured to generate a first control voltage [output of first control node] on the first control node according to a threshold voltage [threshold voltage of 222] of the first control transistor; a second inverter circuit [411/421/422/412] comprising a second switch element [411] and a second control transistor [422], wherein a second control node is between the second switch element and the second control transistor [402], and the second inverter circuit is configured to generate a second control voltage [output of 402] on the second control node according to a threshold voltage [threshold voltage of 422] of the second control transistor; and a driving circuit [31/32] coupled to the first inverter circuit and the second inverter circuit. Sommer does not explicitly disclose a driving circuit coupled to a load, and configured to selectively charge or discharge the load according to the first control voltage or the second control voltage.
However, Kuroda discloses a driving circuit [Fig. 7] coupled to a load [LOAD, 1], and configured to selectively charge or discharge the load according to the first control voltage or the second control voltage [paragraphs 0044-0045]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sommer, in view of Kuroda, by coupling the output of Sommer [Fig. 5, 202] with the driver circuit of Kuroda [Fig. 7], for the purpose of controlling the charge and discharge circuit.
Regarding Claim 8, as best understood, Sommer, in view of Kuroda, discloses the charging/discharging control circuit of claim 1, wherein when the first switch element is turned on according to an input signal [Sommer, 201], the first switch element charges the first control node [Sommer, pull-up by 211/221 to VDD] by a power supply [Sommer, VDD].
Regarding Claim 9, as best understood, Sommer, in view of Kuroda, discloses the charging/discharging control circuit of claim 1, wherein when the second switch element is turned on according to an input signal [Sommer, 401], the second switch element discharge the second control node [Sommer, pull-down to GND].
Claims 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sommer, in view of Kuroda, further in view of Smith et al. (US 7126391 B1); hereinafter Sommer, in view of Kuroda, further in view of Smith.
Regarding Claim 11, as best understood, a charging/discharging control circuit [Fig. 5], comprising: a first inverter circuit [211/221/222/212 (top 23) within bottom box] comprising a first switch element [211] and a first control transistor [222], wherein a first control node is between the first switch element and the first control transistor [node between 221/222]; a second inverter circuit [411/421/422/412] comprising a second switch element [412] and a second control transistor [421], wherein a second control node is between the second switch element and the second control transistor [402]; and a driving circuit [31/32] coupled to the first inverter circuit and the second inverter circuit. Sommer does not explicitly disclose the first control transistor is connected in a diode form; the second control transistor is connected in a diode form; and a driving circuit coupled to a load, so as to selectively charge or discharge the load according to a voltage on the first control node or the second control node.
However, Kuroda discloses a driving circuit [Fig. 7, 32H/32L] coupled to a load [LOAD, 1], so as to selectively charge or discharge the load according to the first control voltage or the second control voltage [paragraphs 0044-0045]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sommer, in view of Kuroda, by coupling the output of Sommer [Fig. 5, 202] with the driver circuit of Kuroda [Fig. 7], for the purpose of controlling the charge and discharge circuit. Sommer, in view of Kuroda, does not explicitly disclose wherein the control transistors of the inverter circuits are connected in a diode form.
However, Smith discloses an inverter [Fig. 7, 714] comprising a transistor connected in a diode form [M702; column 4, line 51 - column 5, line 12]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sommer, in view of Kuroda, further in view of Smith, by replacing the inverter of Sommer [Fig. 5] with the inverter including a transistor in diode form of Smith [Fig. 7], for the purpose of over-voltage protection.
Regarding Claim 12, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 11, wherein the first switch element and the second switch element are turned on or off according to different levels of an input signal [Sommer, 201/401], and the first switch element is coupled to a reference potential [Sommer, GND] through the first control transistor.
Regarding Claim 13, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 12, wherein the first inverter circuit further comprises a first auxiliary transistor [Sommer, 212], the first auxiliary transistor is configured to turn on or off according to the input signal, and is coupled between the first control node and the reference potential.
Regarding Claim 14, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 11, wherein the first switch element and the second switch element are turned on or off according to different levels of an input signal [Sommer, 201/401], and the second switch element is coupled to a power supply [Sommer, VDD] through the second control transistor.
Regarding Claim 15, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 14, wherein the second inverter circuit further comprises a second auxiliary transistor [Sommer, 411], the second auxiliary transistor is configured to turn on or off according to the input signal, and is coupled between the second control node and the power supply.
Regarding Claim 16, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 11, wherein the driving circuit comprises a first driving transistor [Kuroda, 2H], a control terminal of the first driving transistor [Kuroda, gate of 2H] is coupled to the first control node.
Regarding Claim 17, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 16, wherein the driving circuit comprises a second driving transistor [Kuroda, 2L], a control terminal of the second driving transistor [Kuroda, gate of 2L] is coupled to the second control node.
Regarding Claim 18, as best understood, Sommer, in view of Kuroda, further in view of Smith, discloses the charging/discharging control circuit of claim 16, wherein the driving circuit comprises a plurality of driving transistors [Kuroda, 2H/2L], the plurality of driving transistors are connected in series [Kuroda, Fig. 7 shows 2H and 2L connected in series] and coupled to the first control node or the second control node.
Allowable Subject Matter
Claims 2-7 and 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 2-7 and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2842
/REGIS J BETSCH/SPE, Art Unit 2844