DETAILED ACTION
1. Claims 1-33 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shaik et al (hereafter Shaik)(US Pat. 11176991).
Shaik was cited in the IDS filed 02/14/2024.
5. As to claim 1, Shaik discloses a memory device (abstract), comprising:
a multiplying cell (column 2, lines 25-54) comprising: a memory cell comprising a pair of inverters comprising a first inverter and a second inverter (fig. 3 inverters 318T and 318C), each inverter comprising an input and an output, wherein the input of the first inverter is connected to the output of the second inverter at a first end of the pair of inverters (fig. 3, 326C), and wherein the output of the first inverter is connected to the input of the second inverter at a second end of the pair of inverters (fig. 3 326T),
a first transistor connected to the first end of the pair of inverters, and
a second transistor connected to the second end of the pair of inverters, in which a value is stored (column 11, line 64-column 12, line 20 and fig 3, transistors 340C and 340T); and
a switching element connected to an output end of the memory cell, the switching element configured to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the stored value (fig. 3, 306 and 312).
6. As to claim 2, Shaik discloses wherein the switching element is configured to, when connected between a supply voltage and the output end of the memory cell: be turned off in response to a logic value of one being received as the input value; and be turned on in response to a logic value of zero being received as the input value (column 2, lines 25-54, logic level).
7. As to claim 3, Shaik discloses wherein the switching element is configured as a pull-up transistor configured to receive the input value at a gate terminal (column 10, line 39-column 11, line 3, pull up transistor).
8. As to claim 4, Shaik discloses wherein the first transistor and the second transistor are each an N-type metal-oxide-semiconductor (NMOS) transistor, and wherein the pull-up transistor is a P-type metal-oxide-semiconductor (PMOS) transistor (column 27, line 59-column 28, line 30, N-type and P-type).
9. As to claim 5, Shaik discloses configured to select one operation from between a first operation and a second operation and perform the selected operation, wherein the first operation comprises driving a voltage at an output end of the pull-up transistor to a supply voltage in response to a voltage less than the supply voltage being applied through a word line in some multiplication operations in a series of multiplication operations, and outputting each time a multiplication operation result according to an input supplied to the memory device, and the second operation comprises driving a voltage at the output end of the pull-up transistor to the supply voltage in a pre-charge phase for each multiplication operation, and performing a multiplication operation in an evaluation phase (column 2, line 55-column 3, line 30; and column 15, lines 35-64).
10. As to claim 6, Shaik discloses to select the one operation from between the first operation and the second operation based on either an operating frequency of the memory device or a leakage (column 12, line 61-column 13, line 7, amount of leakage).
11. As to claim 7, Shaik discloses an adder connected to an output end of the multiplying cell and configured to add an inverse value of a signal output from the multiplying cell (column 1, lines 40-61 summation).
12. As to claim 8, Shaik discloses a global bit line and switch for a read operation or a write operation on the weight of the memory cell through access to the memory cell of the multiplying cell (column 4, lines 20-64 global bit line and read and write operations).
13. As to claim 9, Shaik discloses memory cells connected to the same pull-up transistor (column 10, line 39-column 11, line 3).
14. As to claim 10, Shaik discloses an input/word line driver configured to select, from among the memory cells, a memory cell to be used for a target multiplication operation (column 11, line 64-column 12, line 20).
15. As to claim 11, Shaik discloses wherein the input/word line driver comprises: a decoding circuit configured to decode an input value provided to the multiplying cell from an input signal and from a signal designating the memory cell to be used for the target multiplication operation (column 4, lines 20-64).
16. As to claim 12, Shaik discloses further configured to activate a word line connected to a memory cell storing a value corresponding to a target operation among memory cells comprised in one multiplication cell, and deactivate a word line connected to a memory cell, among the memory cells, other than the memory cell of the activated word line (column 2, line 25-column 3, line 20).
17. As to claim 13, Shaik discloses further configured to: select a first memory cell from among the memory cells for a first operation among a plurality of operations and output a signal corresponding to a multiplication result through the same pull-up transistor; and select a second memory cell from among the memory cells for a second operation among the plurality of operations and output a signal corresponding to a multiplication result through the same pull-up transistor (column 10, line 39-column 11, line 3).
18. As to claim 14, Shaik discloses multiplying cells including the multiplying cell, and configured to: perform a multiplication operation in each of the multiplying cells in parallel with other multiplying cells; and add, in the same adder, outputs of multiplying cells connected to the same column line among the plurality of multiplying cells (column 2, lines 25-54).
19. As to claim 15, Shaik discloses wherein the multiplying cell is connected to a pair of local bit lines, wherein a first memory cell among memory cells comprised in the multiplying cell is connected to a first local bit line, and a second memory cell among the plurality of memory cells is connected to a second local bit line (column 2, line 55-column 3, line 64).
20. As to claim 16, Shaik discloses wherein the first memory cell connected to the first local bit line has a value corresponding to a weight of a neural network, and the second memory cell connected to the second local bit line has an inverse value of the weight (column 2, line 55-column 3, line 64).
21. As to claim 17, Shaik discloses an accumulator configured to store an output of an adder configured to add multiplication results of the multiplying cell, and accumulate results of the adding (column 2, lines 25-54 accumulate).
22. As to claim 18, Shaik discloses an output register configured to store a final multiplication operation result output from the accumulator (column 4, line 65-column 5, line 35).
23. As to claim 19, Shaik discloses when receiving an input signal corresponding to a last bit of a single bit or multiple bits, store an accumulator operation result for the input signal in an output register (column 4, line 65-column 5, line 35).
24. As to claim 20, Shaik discloses a memory controller configured to control the multiplying cell, an input/word line driver, a read/write circuit, an adder, an accumulator, and an output register (fig. 10, memory controller 1016).
25. As to claim 21, Shaik discloses in response to either a preset period having elapsed or a multiplication operation using another memory cell being performed in each multiplying cell, perform an operation for a pre-charge on an output end of a pull-up transistor (column 2, line 25-column 3, line 20, pre-charge).
26. As to claim 22, Shaik discloses a method of operating a memory device (abstract), the method comprising:
receiving an input value through a word line by a memory cell comprising two inverters connected to each other in opposite directions relative to each other (fig. 3 inverters 318T and 318C), and two transistors connected to both ends of the two inverters (column 11, line 64-column 12, line 20 and fig 3, transistors 340C and 340T); receiving the input value at a gate terminal by a pull-up transistor connected to an output end of the memory cell (column 10, line 39-column 11, line 3, pull up transistor); and outputting, from an output end of the pull-up transistor, a signal corresponding to a multiplication result between the input value and a weight stored in the memory cell (fig. 3, 306 and 312).
27. As to claim 23, Shaik discloses a memory device (abstract), comprising:
a pull-up transistor having a gate and connected to an output line (column 10, line 39-column 11, line 3, pull up transistor); and a memory cell comprising a pair of inverters connected to each other at their respective ends in opposite directions such that the pair of inverters has a first end and a second end, and a cell transistor having a gate and connected to the first end of the pair of inverters and to the output line (fig. 3 inverters 318T and 318C), and in response to an input having the same logic value being applied to the gate of the pull-up transistor and the gate of the cell transistor, configured to output, to the output line, a logic value corresponding to a binary multiplication result between the input and a binary value stored in the memory cell (column 2, lines 25-54, logic level).
28. As to claim 24, Shaik discloses wherein the logic value corresponding to the binary multiplication result is a NAND result (column 9, lines 53-column 10, line 6).
29. As to claim 25, Shaik discloses wherein the pull-up transistor is a P-type metal-oxide-semiconductor (PMOS) transistor, and the cell transistor is an N-type metal-oxide-semiconductor (NMOS) transistor (column 27, line 59-column 28, line 30, N-type and P-type).
30. As to claims 26 and 27, Shaik discloses wherein the multiplication result is output every clock cycle and wherein the multiplication result is output only every two clock cycles (column 2, line 25-54).
31. As to claim 28, Shaik discloses wherein the cell transistor is a first cell transistor, and the memory cell further comprises: a second cell transistor having a gate and connected to the second end of the pair of inverters, wherein an input having the same logic value is applied to the gate of the second cell transistor (fig. 4).
32. As to claim 29, Shaik discloses wherein the output line is a first output line further comprising a second output line (fig. 3 and 4).
33. As to claim 30, Shaik discloses wherein the cell transistor is a first cell transistor, and the memory cell further comprises a second cell transistor having a gate and connected to the other end of the pair of inverters and to the second output line (fig. 4).
34. As to claim 31, Shaik discloses wherein the pull-up transistor is a first pull-up transistor, and wherein the memory device further comprises a second pull-up transistor connected to the second output line (fig. 3).
35. As to claims 32 and 33, Shaik discloses wherein the memory cell is one of multiple memory cells connected to the first output line and the second output line and wherein the memory cell is one of multiple memory cells connected to the output line (column 11, line 64-column 12, line 20).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20220244916 - related to a compute-in-memory (CIM) device that has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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