DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 03/17/23 for application number 18/185,480. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, and Claims.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 objected to because of the following informalities:
Claim 19, line 11 reads, “switch the power from the power supply unit to the output voltage bus” and should instead read, “switch on the power from the power supply unit to the output voltage bus” (emphasis added). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5, 12, and 19 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 5 appear to simply repeat the limitations presented in Claims 2, 3, and 4, save for the counter corresponding to a hiccup time, and does not further limit Claim 4, on which it depends.
Claims 12 and 19 recite limitations similar to those of Claim 5, and are objected to accordingly. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6, 8, 13, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Guthrie et al., US 2012/0327688 A1, in view of Li et al., US 2012/0191988 A1.
Regarding Claim 1, Guthrie discloses a method for turning on a power supply unit, the method comprising:
monitoring, by a processor unit in the power supply unit, an output voltage bus, wherein the power supply unit is connected to the output voltage bus; and
switching on, by the processor unit in the power supply unit, the power from the power supply unit to the output voltage bus in response to the bus voltage being greater than the voltage threshold for a stable time period [start-up delay, as previously discussed, is activated if a pre-bias value of the output voltage is greater than a predefined threshold. Also the start-up delay may be selected to be equal to the ramp time plus an additional buffer time to insure that there is a stable output bus voltage at the end of the start-up delay period; i.e. monitoring the voltage bus in order to determine if the voltage is greater than a threshold, and delaying the startup by powering on if voltage is greater than a threshold, and waiting a preset time to ensure stable output, par 43].
However, Guthrie does not explicitly teach switching on, by the processor unit in the power supply unit, power from the power supply unit to the output voltage bus in response to a bus voltage on the output voltage bus not being greater than a voltage threshold for a safe time period.
Li teaches switching on, by the processor unit in the power supply unit, power from the power supply unit to the output voltage bus in response to a bus voltage on the output voltage bus not being greater than a voltage threshold for a safe time period [stopping output of voltage (determining there is 0 voltage, i.e. below a voltage threshold); after a recovering time t has passed, the power adapter restarts the output of voltage (i.e. switching on after being below a threshold for a safe time period), par 6].
It would have been obvious to one of ordinary skill in the art, having the teachings of Guthrie and Li before him before the effective filing date of the claimed invention, to incorporate the switching on of voltage after voltage being below a threshold for a safe period of time, as taught by Li, into the method as disclosed by Guthrie, to provide overcurrent protection [Li, par 6].
Regarding Claim 6, Guthrie and Li disclose the method of Claim 1. Guthrie further discloses wherein the voltage threshold indicates that the power is being supplied to the output voltage bus [start-up delay… is activated if a pre-bias value of the output voltage is greater than a predefined threshold, par 43].
Regarding Claim 8, Guthrie discloses a power supply system comprising: a power supply unit; and a processing unit [system of Fig. 1 comprising containing power converter 105 (power supply unit) and power controller 125 (processing unit) containing converter controller 126].
The remainder of Claim 8 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claim 13, Guthrie and Li disclose the power supply system of Claim 8. Claim 13 repeats the same limitations as recited in Claim 6, and is rejected accordingly.
Regarding Claim 15, Guthrie discloses a computer program product for turning on a power supply unit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor [power conversion units contain non-volatile memory, par 29; power conversion unit 100 contains power controller 125 (processing unit), Fig. 1].
The remainder of Claim 15 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claim 20, Guthrie and Li disclose the computer program product of Claim 15. Claim 20 repeats the same limitations as recited in Claim 6, and is rejected accordingly.
Claims 2-5, 9-12, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Guthrie and Li, in view of Banerjee et al., US 2018/0292875 A1, and further in view of Boveja et al., US 2006/0074450 A1.
Regarding Claim 2, Guthrie and Li disclose the method of Claim 1. However, while Guthrie further discloses monitoring an output voltage bus; determining, by the processor unit in the power supply unit, whether the bus voltage is greater than the voltage threshold [start-up delay, as previously discussed, is activated if a pre-bias value of the output voltage is greater than a predefined threshold. Also the start-up delay may be selected to be equal to the ramp time plus an additional buffer time to insure that there is a stable output bus voltage at the end of the start-up delay period; i.e. monitoring the voltage bus in order to determine if the voltage is greater than a threshold, and delaying the startup by powering on if voltage is greater than a threshold, and waiting a preset time to ensure stable output, par 43], and Li further teaches setting, by the processor unit in the power supply unit, a counter to a safe time in response to the bus voltage not being greater than the voltage threshold [stopping output of voltage (determining there is 0 voltage, i.e. below a voltage threshold); after a recovering time t has passed, the power adapter restarts the output of voltage (i.e. switching on after being below a threshold for a safe time period), par 6], the combination of references does not explicitly teach decrementing the counter and the counter being set; determining, whether the counter is zero in response to decrementing the counter; waiting for a delay period in response to the counter not being zero; repeating each prior step of the process until the counter reaches zero.
Bangerjee teaches decrementing the counter and the counter being set; determining, whether the counter is zero in response to decrementing the counter [decrementing a set time counter value until it reaches zero, par 26].
It would have been obvious to one of ordinary skill in the art, having the teachings of Guthrie, Li, and Bangerjee before him before the effective filing date of the claimed invention, to incorporate the decrementing counter in a preset duration, as taught by Bangerjee, into the method as disclosed by Guthrie and Li, to improve power consumption efficiencies and decrease latency for power state changes [Bangerjee, par 2].
However, the combination of references does not explicitly teach waiting for a delay period in response to the counter not being zero; and repeating each prior step of the process until the counter reaches zero.
Boveja teaches waiting for a delay period in response to the counter not being zero; and repeating each prior step of the process until the counter reaches zero [decrementing counter for a predetermined period of time; if counter is not at zero, then will decrement again after a delay until reaches 0 and power is transitioned (i.e. switches are opened), par 103].
It would have been obvious to one of ordinary skill in the art, having the teachings of Guthrie, Li, Bangerjee, and Boveja before him before the effective filing date of the claimed invention, to incorporate waiting after a decrement delay as taught by Boveja, into the method as disclosed by Guthrie, Li, and Bangerjee, to provide gradual stopping of power.
Regarding Claim 3, Guthrie, Li, Bangerjee, and Boveja disclose the method of Claim 2. Guthrie further discloses switching on, by the processor unit in the power supply unit, the power from the power supply unit to the output voltage bus in response to the bus voltage on the output voltage bus being greater than the voltage threshold and the counter not being zero [start-up delay, as previously discussed, is activated if a pre-bias value of the output voltage is greater than a predefined threshold. Also the start-up delay may be selected to be equal to the ramp time plus an additional buffer time to insure that there is a stable output bus voltage at the end of the start-up delay period; i.e. monitoring the voltage bus in order to determine if voltage is greater than a threshold, regardless of the counter, with the delay startup consisting of powering on if the voltage is greater than a threshold and waiting a preset time to ensure stable output, par 43].
Regarding Claim 4, Guthrie and Li disclose the method of Claim 1. However, while Guthrie further discloses setting, by the processor unit in the power supply unit, a counter to a stable time in response to the bus voltage being greater than the voltage threshold; and determining, by the processor unit in the power supply unit, whether the bus voltage is greater than the voltage threshold [start-up delay, as previously discussed, is activated if a pre-bias value of the output voltage is greater than a predefined threshold. Also the start-up delay may be selected to be equal to the ramp time plus an additional buffer time to insure that there is a stable output bus voltage at the end of the start-up delay period; i.e. monitoring the voltage bus in order to determine if the voltage is greater than a threshold, and delaying the startup by powering on if voltage is greater than a threshold, and waiting a preset time to ensure stable output, par 43]; and Li further teaches determining, by the processor unit in the power supply unit, whether the bus voltage is greater than the voltage threshold in response to the counter being set [stopping output of voltage (determining there is 0 voltage, i.e. below a voltage threshold); after a recovering time t has passed, the power adapter restarts the output of voltage (i.e. switching on after being below a threshold for a safe time period), par 6]; decrementing, by the processor unit in the power supply unit, the counter; determining, by the processor unit in the power supply unit, whether the counter is zero in response to decrementing the counter; waiting, by the processor unit in the power supply unit, for a delay period in response to decrementing the counter and the counter not being zero; repeating determining the voltage and decrementing the counter; determining whether the counter is zero in response to decrementing the counter; and waiting for the delay period in response to decrementing the counter and the counter not being zero, wherein the stable time period ends when the counter is zero.
Bangerjee teaches decrementing, by the processor unit in the power supply unit, the counter; and determining whether the counter is zero in response to decrementing the counter [decrementing a set time counter value until it reaches zero, par 26].
It would have been obvious to one of ordinary skill in the art, having the teachings of Guthrie, Li, and Bangerjee before him before the effective filing date of the claimed invention, to incorporate the decrementing counter in a preset duration, as taught by Bangerjee, into the method as disclosed by Guthrie and Li, to improve power consumption efficiencies and decrease latency for power state changes [Bangerjee, par 2].
However, the combination of references does not explicitly teach repeating determining the voltage and decrementing the counter; determining whether the counter is zero in response to decrementing the counter; and waiting for the delay period in response to decrementing the counter and the counter not being zero, wherein the stable time period ends when the counter is zero
Boveja teaches repeating determining the voltage and decrementing the counter; determining whether the counter is zero in response to decrementing the counter; and waiting for the delay period in response to decrementing the counter and the counter not being zero, wherein the stable time period ends when the counter is zero [decrementing counter for a predetermined period of time; if counter is not at zero, then will decrement again after a delay until reaches 0 and power is transitioned (i.e. switches are opened), par 103].
It would have been obvious to one of ordinary skill in the art, having the teachings of Guthrie, Li, Bangerjee, and Boveja before him before the effective filing date of the claimed invention, to incorporate waiting after a decrement delay as taught by Boveja, into the method as disclosed by Guthrie, Li, and Bangerjee, to provide gradual stopping of power.
Regarding Claim 5, Guthrie, Li, Bangerjee, and Boveja disclose the method of Claim 4. Claim 5 appears to recite limitations similar to the combination of Claims 2, 3, and 4, and is rejected accordingly.
Regarding Claims 9-12 and Claims 16-19, Guthrie and Li disclose the power supply system of Claim 8 and the computer program product of Claim 15, respectively. Claims 9-12 and Claims 16-19 repeat the same limitations as recited in Claims 2-5, and are rejected accordingly.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Guthrie and Li, and further in view of Xu, US 11,211,867 B2.
Regarding Claim 7, Guthrie and Li disclose the method of Claim 1. However, the combination of references does not explicitly teach wherein the power supply unit is part of a plurality of power supply units connected in parallel to each other and having outputs connected to the output voltage bus.
Xu teaches wherein the power supply unit is part of a plurality of power supply units connected in parallel to each other and having outputs connected to the output voltage bus [pre-stage circuit comprising a plurality of conversion circuits connected in parallel; pre-stage circuit output an intermediate bus voltage, Claim 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of Guthrie, Li, and Xu before him before the effective filing date of the claimed invention, to incorporate a plurality of parallel power supply units as taught by Xu, into the method as disclosed by Guthrie and Li, to provide converters with high efficiency and high dynamic characteristics [Xu, col. 1, ll. 42-44].
Regarding Claim 14, Guthrie and Li disclose the power supply system of Claim 8. Claim 14 repeats the same limitations as recited in Claim 7, and is rejected accordingly.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175
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