DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Instant application eligible to benefit from the foreign application as claimed by applicant on 09/18/2020 and effective filling date was considered as 09/18/2020.
Information Disclosure Statement
IDS has been submitted on 5/18/2023, 6/27/2023, 8/16/2024, 9/26/2024, 2/18/2025, and 12/05/2025 has been considered by the examiner.
Claim Status
Claim 1-33 are cancelled.
Claims 34-52 are pending and examined on the merits.
Claims 34-52 are rejected.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 36 and 52 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 36 recited “the detector” in line 1. The limitation lacks antecedent basis.
Regarding claim 52, the phrase “in accordance with a single order” is vague, ambiguous, and lacks reasonable certainty regarding its scope and boundaries. The term “in accordance” has no established meaning in the field of processor-level parallel processing. When read in light of the specification, the phrase fails to inform a person of ordinary skill in the art with reasonable certainty whether it refers to:
A single sequential order of execution;
A singular instruction; or
A specific multi-processor system architecture.
While the specification generally illustrates parallel processing configurations (paragraphs [0005], [0007], [0008]; FIG. 2), it fails to provide structural or operational details explaining how a second processor executes parallel processing “in accordance with a single order.” The absence of clear descriptive boundaries or definitions forces a person of ordinary skill in the art to speculation regarding the operational relationship between the processors and the claimed “single order” limitation.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 34-52 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 2A, Prong 1
In accordance with MPEP § 2106, the instant claims 34-52, are drawn to a system and therefore are found to recite statutory subject matter (Step 1: YES). The instant claims are then analyzed to determine if the claims recite any concepts that equate to an abstract idea, law of nature or natural phenomenon (Step 2A, Prong 1). The instant claims recite the following limitations that equate to an abstract idea:
Claim 34 recites
The first processor is configured to classify, based on a result of the parallel processing by the second processor, a cell type of each of the plurality of cells. (Mental process) Classifying data (such as cell types) falls under mental evaluations or judgments.
Claim 42 recites “generating an information that includes an identifier for identifying the cell type.” (Mental process)
Claim 43 recites “generating an information that includes a probability at which the cell belongs to each of a plurality of the cell types.” Generating information that includes a “probability” generally implicates mathematical concepts (e.g., statistical analysis or machine learning algorithms). (Mental process and Mathematical concept)
Claim 45 recites “transmitting an analysis result including a probability at which the cell belongs to each of a plurality of the cell types, to a processing unit which performs analysis of the analysis result.” (Mathematical concept and mental process) Calculating or generating numerical probabilities regarding cell types relies on mathematical calculations and analysis that can theoretically be performed in the human mind.
Claim 46 recites “the second processor is configured to execute, in parallel as the parallel processing, a plurality of arithmetic processes regarding analysis of the data.” (Mathematical concept) The specific limitation reciting a second processor executing a plurality of arithmetic processes in parallel combines elements of a mathematical concept (as arithmetic calculations)
Claim 49 recites” the artificial intelligence algorithm is a deep learning algorithm.” (Mathematical concept) Deep learning algorithms on complex, multidimensional matrix calculations.
Claim 51 recites “the second processor is configured to execute, in parallel as the parallel processing, a plurality of arithmetic processes in a convolution layer in the deep learning algorithm.” (mathematical concept) The underlying arithmetic and matrix operations (convolutions, multiplications, additions) are mathematical concepts, which form a sub-group of abstract ideas.
As such claims 34-52 recite an abstract idea (Step 2A, Prong 1: YES).
Step 2A, Prong 2
Claims found to recite a judicial exception under Step 2A, Prong 1 are then further analyzed to determine if the claims as a whole integrate the recited judicial exception into a practical application or not (Step 2A, Prong 2). Specifically, the claims recite the following additional elements:
Claim 34 recites
A cell analyzer comprising: a measurement unit configured to measure a plurality of cells contained in a specimen. the measurement unit comprising (i) a preparator configured to prepare a measurement sample by mixing the specimen and a reagent in a chamber and (ii) a flow cytometer configured to optically interrogate the cells in the measurement sample flowing in a flow cell.”
A second processor configured to perform a parallel processing, wherein the measurement unit is configured to obtain matrix data regarding each of the plurality of cells.
The second processor is configured to execute the parallel processing to process the matrix data according to an Al algorithm comprising a plurality of matrix operations.
The matrix data being obtainable by digitally converting an analog signal corresponding to intensity of light emitted from the cell optically interrogated by the flow cytometer, wherein the matrix data has. as elements of the matrix data, values digitally indicating the analog signal level at a plurality of time points.
Claim 35 recites “the cell analyzer according to claim 34, wherein the flow cytometer comprises a light source for applying light to the flow cell, and a detector for detecting the light emitted from each cell due to the applied light by the light source”
Claim 36 recites “The cell analyzer according to claim 34, wherein the detector is configured to detect a plurality of types of light emitted from each cell.”
Claim 37 recites “The cell analyzer according to claim 34, wherein the matrix data is transmitted to the second processor via a transmission line included in the cell analyzer.”
Claim 38 recites “The cell analyzer according to claim 34, wherein the matrix data is transmitted to the second processor via a transmission line different from an Internet or2 an intranet.”
Claim 39 recites “The cell analyzer according to claim 34, wherein the transmission line has a communication band of not less than I gigabit/second.”
Claim 40 recites “the cell analyzer according to claim 34, wherein the transmission line is a bus, and the data is transmitted to the second processor via the bus.”
Claim 41 recites “the cell analyzer according to claim 34, wherein the measurement unit comprises an A/D converter configured to convert the analog signal regarding each of the plurality of cells measured by the flow cytometer into a digital signal, wherein the A/D converter is configured to sample the respective analog signal at a predetermined sampling rate to thereby obtain as waveform data corresponding to the cell, the matrix data for the cell.”
Claim 44 recites “The cell analyzer according to claim 34, being further configured for transmitting an analysis result including an identifier for identifying the cell type, to a processing unit which performs analysis of the analysis result.”
Claim 47 recites “the second processor comprises a plurality of arithmetic units each operable to perform a calculation on an assigned subset of a matrix operation, and the second processor is configured to execute, in parallel as the parallel processing, the arithmetic processes by the respective arithmetic units.”
Claim 48 recites “the first processor is configured to execute an operation of dividing the matrix operation into subsets of calculations and assigning the subsets of calculations to at least some of the arithmetic units of the second processor for parallel processing of the matrix operation.”
Claim 50 recites “the second processor is configured to execute, in parallel as the parallel processing, a filtering process for extracting a feature of the data.”
Claim 51 recites “the artificial intelligence algorithm is a deep learning algorithm”
Claim 52 recites “the second processor is configured to execute the parallel processing in accordance with a single order.”
For claim 34, the components listed (a “measurement unit,” “preparator” for mixing specimens/reagents, and a “flow cytometer”) are standard, off-the-shelf laboratory tools. Because these mechanisms perform their basic functions in a customary way, they fail to provide an inventive concept that transforms the claim into patent-eligible subject matter. Under Step 2 of the Alice/Mayo framework, adding standard apparatus limitations to a claim does not make an otherwise ineligible abstract idea or natural phenomenon patentable. By claiming a “measurement unit” and “flow cytometer” that do exactly what such devices have always done, the claim preempts the use of these tools in all fields without offering a specific, unconventional technological improvement.
Also, to obtain matrix data by converting light intensity to an analog signal and digitally sampling it at multiple time points describes nothing more than basic mathematical data gathering and representation. (MPEP 2106)
Reciting a “second processor configured to perform parallel processing” invokes generic, well-known computing components without specifying an unconventional structural or architectural improvement to the processor itself as evidenced by Nunez in his review article(Flow Cytometry: Principles and Instrumentation, Flow Cytometry in Microbiology: Technology and Applications (2015)) where he describes about parallel processing electronics (Nunez et al., pg. 6) and in an another review article by Toner et al. (Annu. Rev. Biomed. Eng. 2005. 7:77–103) describes the parallel processing of a large number of cells in parallel (Toner et al., pg. 11)
Also, the additional element “wherein the measurement unit is configured to obtain matrix data" amounts to routine data collection, which does not transform an abstract mathematical or informational process into patent-eligible subject matter.
For claim 35, the additional elements require physical, tangible components (a light source and a detector) to interact with physical cells. These steps cannot be performed in the human mind. Because a flow cytometer is a physical machine, it does not fall into the categories of abstract ideas, laws of nature, or natural phenomena. However, using a light source to illuminate cells and detecting the resulting emitted light is merely observing a natural phenomenon or a fundamental scientific correlation. The element does not integrate this principle into a specific, non-monopolizable application.
The additional element in claim 36 merely recites a field of use, data-gathering step, or conventional use of existing technology without imposing any specific technological improvement or transformation. Merely adding a step to gather or output data without specifying how that data is used to achieve a tangible, real-world result—does not transform an abstract idea into a practical application.
For claim 37, the additional element merely transmitting data through a standard transmission line is an inherently well-understood, routine, and conventional activity in the field of electronics and computing. Under Alice Corp. v. CLS Bank, simply linking an abstract concept to standard, generic hardware components do not transform it into a patent-eligible invention.
The additional element in claim 38 fails to provide practical application or transform the claim into patent-eligible subject matter. It merely recites insignificant, extra-solution activity. Under the Supreme Court's Alice/Mayo framework, adding a generic data transmission step (using a physical transmission line) does not integrate an abstract idea into a practical application. It is merely data-gathering or data-moving, which is insufficient to confer patentability.
The additional element in claim 39 does not add a practical application under 35 U.S.C. 101 because it only states a generic data speed without requiring any specialized, unconventional machine modification or new analytical method that structurally integrates the communication band into the cell analyzer's function. Claiming transmission lines or communication components operating at 1 gigabit/second relies entirely on well-understood, routine, and conventional data-transfer technology.
For claim 40, using a bus to transmit data between processors is a universally known, standard computer hardware component. Merely reciting standard hardware to execute a generic data transmission does not transform an unpatentable abstract idea into a patent-eligible application.
The additional element in claim 41 merely recites conventional, routine data gathering and storage. It transforms an analog signal into a digital format using well-known, off-the-shelf components without improving the underlying measurement technology or generating a specific, unconventional physical output.
For claim 44, the additional elements constitute insignificant extra-solution activity. It does not practically apply, use, or tie the analysis result to a specific technological process or end-use, serving merely as a post-solution instruction to transmit abstract data for generic processing.
For claim 47, 48, and 50, it merely recites generic parallel hardware components functioning in a conventional manner without improving computer technology itself. The description of performing subsets of a matrix operation in parallel reflects generic computer implementation rather than a specific, unconventional architectural improvement. Simply instructing a processor to execute math calculations concurrently does not impose meaningful limits on the abstract mathematical concept itself. Allocating subsets of data to separate execution units amounts to routine data manipulation on standard hardware, which fails to transform an abstract idea into a patent-eligible application.
For Claim 51, the addition element “deep learning algorithm” is a generic implementation step that fails to add a practical application or inventive concept because it merely applies conventional mathematical and computational techniques to an abstract idea without improving the underlying technology.
For claim 52, the additional element “the second processor is configured to execute the parallel processing in accordance with a single order”, adding a generic second processor to execute parallel processing in a single order does not add a practical application under 35 U.S.C. 101 because it amounts to conventional computer implementation and generic data manipulation. The element uses standard processor hardware without reciting any specific, unconventional structural improvement to the computer itself.
The core of the claimed invention remains the algorithmic construction of a cell type analysis of the biological samples based on light scattered by cells. Because bioinformaticians and geneticists routinely rely on publicly available tools, utilizing these tools to determine cell type of biological samples is a routine, well-understood, and conventional process in the art.
These limitations describe mere data collection (gathering) and the application of abstract mathematical and mental processes, and lack the necessary integrative steps to transform them into a practical application per MPEP 2106.
The additional elements merely recite a conventional computer processor and a memory attached to a conventional flow cytometer used to execute the claimed instructions. Under Alice Corp. v. CLS Bank Int'l, simply implementing or analyzing data using a generic, general-purpose computer does not transform an unpatentable abstract idea into a patent-eligible application.
Under the MPEP 2106.05(g) guidelines regarding insignificant extra-solution activity, the mere act of crunching and gathering data on a conventional computing system is well-understood, routine, and conventional in the art of bioinformatics pipelines. The recited limitations serve solely as data-gathering or analyzing activities. Because these additional elements do not reflect any specific improvement to computer functioning or physical technology, the claim fails to integrate the judicial exception into a practical application, and instead amounts to insignificant, routine post-solution activity.
There are no limitations that indicate that the cell analyzer process requires anything other than a conventional computer attached to conventional flow cytometer to execute the instructions (a series of steps). As such, these limitations equate to mere instructions to implement the abstract idea on a generic computer that the courts have stated does not render an abstract idea eligible in Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984.
The above recited additional elements do not provide a practical application of the recited judicial exception. As such, claims 34-52 are directed to an abstract idea (Step 2A, Prong 2: NO).
Step 2B
Claims found to be directed to a judicial exception are then further evaluated to determine if the claims recite an inventive concept that provides significantly more than the judicial exception itself (Step 2B). The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the claims recite additional elements that equate to mere instructions to apply the recited exception in a generic computing environment or well-understood, routine and conventional activity.
As discussed above, there are no additional limitations to indicate that the claimed cell analyzer requires anything other than generic computer components attached with conventional flow cytometer in order to carry out the recited abstract idea in the claims. Claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984.
Furthermore, the additional elements recited in the claims amount to well-understood, routine and conventional activity as shown by Nunez in his review article where he describes about parallel processing electronics (Nunez et al., pg. 6) and in another review article by Toner et al. describes the parallel processing of a large number of cells in parallel (Toner et al., pg. 11). As such, the combination of additional elements recited in the claims is well-understood, routine and conventional.
The additional elements do not comprise an inventive concept when considered individually or as an ordered combination that transforms the claimed judicial exception into a patent-eligible application of the judicial exception. Therefore, the claims do not amount to significantly more than the judicial exception itself (Step 2B: No). As such, claims 33-52 are not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 34, 35, 36, 41-45, and 49-51 are rejected under 35 U.S.C. 103 as unpatentable over Diebold et al. (US 10,324019 B2) in view of Ortyn et al. (US 2010/0232675 A1) and further in view of Li et al. (Scientific RepoRtS | (2019) 9:11088)
Diebold et al. discloses:
A flow cytometry-based cell analysis system configured to measure a plurality of cells in a biological specimen (Col 3, line 20-45). The system is designed to analyzed cell populations in blood or other biological fluids suggesting the limitation of “a cell analyzer comprising a measurement …….. contained in a specimen.”
Sample preparation involving mixing of biological specimen with reagents prior to cytometric analysis (Col. 4, line 10-30) suggesting the limitation of “the measurement unit comprising (i) a preparator ….. in a chamber.”
A flow cytometer that optically interrogates cells passing through a flow cell using one or more laser light sources and photodetectors (Col. 3, line 50-65; Col. 5, line 1-20, Col. 7, line 20-45, Col. 33, 1-20) suggesting the limitation of “(ii) a flow cytometer configured ….. flowing in a flow cell”.
A central processor (CPU) that performs information processing for cell analysis, including organizing acquired data, managing workflows, and outputting classification results to the user (Col. 24, line 30-60) suggesting the limitation of “a first processor configured ….. plurality of cells.”
The use of a secondary processing unit (e.g., GPU processor) to perform computationally intensive machine learning inference in parallel (Col. 24, line 45-70) suggesting the limitation of “a second processor …. Parallel processing”
The digitization of per cell analog signals into structured data arrays for downstream ML processing (Col. 24, line 30-55, Figure 11B and 27). suggesting the limitation of “the measurement unit is configured to obtain matrix data ….. digitally converting an analog signal ….. by the flow cytometer”.
However, Diebold et al. does not explicitly disclose about a preparator subsystems that mixes specimen and reagent in a sample chamber, or explicitly disclose parallel processing for computation of the data.
Ortyn et al. discloses:
A preparator/fluidics subsystem that mixes specimen and reagent in a sample chamber before introducing cells to the flow cell (p. 21, c1, top) suggesting the limitation of “the measurement unit comprising (i) a preparator ….. in a chamber.”
A parallel processing system distinct from the main CPU (p. 3, c1, middle). The use of dedicated second processor for parallel computation was well within the ordinary skill in the art before the effective filing date suggesting the limitation of “a second processor …. Parallel processing”
Analog optical signals from each cell detected by the photodetector array are digitized on per-pixel basis by the time -delay-integration detector at a defined sampling rate, producing time-series waveform data (p. 6, c1, middle). This digitized time -series data is structured as a matrix where each element represents the digitized signal amplitude at a discrete time point-precisely the claimed “digitally converting an analog signal corresponding to intensity of light emitted from the cell optically interrogated by the flow cytometer … as elements of the matrix data”.
The combination of Diebold et al. and Ortyn et al. thus suggest the limitation of “the measurement unit is configured to obtain matrix data …. the matrix data being obtainable by digitally converting an analog signal corresponding to intensity of ….. at a plurality of time points”.
However, Diebold et al. and Ortyn et al. do not explicitly disclose about machine learning algorithm use for classification of cell type.
Li et al. discloses deep learning algorithms for cell classification consist of a plurality of matrix operations (e.g., convolution, matrix multiplication, activation) executed in parallel on GPU hardware (p. 2, bottom; Figure 2; p. 7, bottom; Figure 6)
The combination of these references by Diebold, Ortyn and Li makes the claimed “AI algorithm comprising a plurality of matrix operations” executed in parallel fully disclosed and/or obvious and suggesting the limitation of “the second processor is configured to execute the parallel processing to process the matrix data according to an Al algorithm comprising a plurality of matrix operations,”
A person having ordinary skill in the art (PHOSITA) at the time of the effective filing date would have been motivated to combine the teachings of Diebold et al., Ortyn et al. and Li et al. to arrive the claimed invention with a reasonable expectation of success, for the following reasons.
Both Diebold and Ortyn et al. are directed to analogous art, namely flow cytometry-based cell analysis systems that measure and classify cells in a biological specimen. A PHOSITA reviewing Diebold.s system, which already discloses mixing of specimen and reagent prior to cytometric analysis (Col. 4, lines 10-30) and a central processor that manages acquired data and classification output (Col. 24, lines 30-60), would have looked to Ortyn for a more granular teaching of how such sample preparation and parallel data processing are conventionally implemented. Because Ortyn discloses a preparator/fluidics subsystem that mixes specimen and reagent in a sample chamber before introducing to the flow cell (Ortyn, p. 21, c1, top)
Incorporating Ortyn’s preparator/fluidics subsystem into Diebold’s system amounts nothing more than the combination of prior art elements according to methods to yield predictable result of a properly mixed measurement sample delivered to the flow cells for optical interrogation. (MPEP 2142(A); KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
A PHOSITA would similarly have been motivated to incorporate Ortyn’s second, parallel processor into Diebold’s system. Diebold itself already discloses offloading computationally intensive machine learning inference to a secondary GPU processor operating in parallel with the main CPU (Col. 24, lines 45-70), demonstrating that Diebold recognized the benefit of parallelized computation for cell classification. Ortyn confirms that the use of a second processor, distinct from the main CPU, to perform parallel computation was well known within the ordinary skill in the art before the effective filing date (Ortyn, p. 3, c1, middle). Applying this known architecture to Diebold’s system would have yielded the predictable benefit of increased processing throughout and faster classification output, with no unexpected results. (MPEP 2143(C) (use of a known technique to improve a similar device in the same way)
A PHOSITA would further have been motivated to structure Diebold’s digitized per-cell signal data (Col. 24. Lines 30-55; Figs. 11B, 27) according to Ortyn’s specific teaching of digitizing analog optical signals on per-pixel, time resolved basis to produce time-series waveform data structured as a matrix, in which each element represents the digitized signal amplitude at a discrete time point (Ortyn, p. 6, c1, middle). Because Diebold already contemplates structured digital data arrays as the input to its downstream classification processing, but does not itself specify the precise time-indexed matrix structure, A PHOSITA would have recognized Ortyn’s matrix-formatted, time series digitization as a suitable, predictable substitute or refinement of Diebold’s own data structuring, obtainable with a reasonable expectation of success. (MPEP 2143 (B) (simple substitution of one known element for another to obtain predictable results).
Having arrived at a combined Diebold’s/Ortyn system processing (i) a parallel-processing hardware architecture and (ii) matrix-structured, time-indexed digitized signal data, A PHOSITA would have been motivated to apply Li’s deep learning algorithm to that matrix data. Li discloses that deep learning algorithms for cell classification consist of a plurality of matrix operation, such as convolution, matrix multiplication, and activation, executed in parallel on GPU hardware (Li, p. 2. Bottom; Figure 2; p. 7, bottom; Figure 6). Li’s teaching thus provides an art-organized, off the shelf algorithmic framework especially suited to operate on the type of matrix-formatted cell data already produced by the combined Diebold/Ortyn system.
Because Diedold already contemplates GPU-based machine learning inference for cell classification (Col. 24, lines 45-70) but does not itself specify the particular algorithmic architecture used to process the matrix data, and because Li teaches that deep learning matrix operations are amenable to parallelized GPU execution, a PHOSITA would have had a reasonable expectation of success in incorporating Li’s matrix-operation based deed learning algorithm into the second, parallel processor of the combined Diebold/Ortyn system to perform the claimed cell classification function.
This combination amounts to no more than the application of a known technique, namely Li’s matrix-operation-based deep learning classification algorithm, to a known device, namely the Diebold/Ortyn cell analyzer, that was ready for improvement, to yield the predictable result of automated, accurate cell type classification based on the digitized matrix data. (MPEP 2143(D)) (applying a known technique to a known device ready for improvement to yield predictable results) (KSR, 550, U.S. at 417.
Accordingly, a PHOSITA would have had ample motivation, supported by the teaching of Diebold, Ortyn, and Li themselves, and a reasonable expectation of success, to combine these references to arrive at the cell analyzer of claim 34, including a measurement unit with a preparator and flow cytometer, a first processor for classification, and a second processor configured to execute parallel processing of matrix-structured cell data according to an AI algorithm comprising a plurality of matrix operation.
Regarding claim 35 and 36:
Claim 35 requires a flow cytometer with a light source and a detector to measure light emitted from each cell.
Claim 36 requires the detector to measure multiple types (wavelengths) of light per cell.
Diebold et al. discloses one or more laser light sources applied to the flow cell and multiple photodetector (e.g., photomultiplier tubes, PMTs) arranged to detect different wavelengths of light emitted or scattered from each cell (Figure 1; Col. 1, lines 20-40, Col. 8, lines 25-35, Col. 9, lines 20-50; Figure 9B and Figure 10) suggesting the limitation of “the flow cytometer comprises a light source and a detector for detecting light emitted from each cell”
Ortyn et al. similarly discloses multi-channel detection of scattered and fluorescent light across a plurality of optical channels (p. 6, c2, middle; p. 8, c1, bottom; p. 11, c2, middle;) suggesting the limitation of “the detector detects a plurality of types of light from each cell.”
Multichannel, multi-wavelength detection was standard and well known in flow cytometry well before the effective filing date of the invention.
Under the framework set by the Supreme Court in KSR, modifying a base flow cytometer (such as the one outlined in Claim 34) to incorporate the multi-detector setups taught by Diebold and Ortyn is the simple application of known methods to known elements.
Regarding claim 41:
Claim 41 recites that the measurement unit comprises an A/D converter configured to convert the analog signal for each cell into a digital signal by sampling at a predetermined rate, thereby producing waveform data (matrix data) for each cell.
Ortyn et al. discloses an A/D converter that samples the analog optical signal from each cell at a fixed, predetermined sampling rate to produce digitized waveform data (p. 6, c1, middle). Because Ortyn et al. teaches the functional components and data output recited in Claim 41, the reference directly anticipates this specific data-conversion mechanism suggesting the limitation of claim 41.
Incorporating Ortyn’s conventional A/D converter into the Diebold system would have been an obvious modification to a person of ordinary skill in the art (PHOSITA). Digital conversion of analog optical signals represents a standard, ubiquitous component in digital flow cytometry systems and was well-known in the art prior to the effective filing date.
Regarding claim 42 and 44:
Claim 42 adds limitation of generating information including a cell type identifier and claim 44 adds limitation of transmitting analysis results including cell type identifier to a processing unit.
Li et al. discloses these elements. Specifically, Li teaches the output of cell type classification results designed for downstream processing and utilization (pg. 2, bottom; pg. 7, bottom; pg. 9, middle).
Because Li et al. already describes both generating a classification identifier and transmitting this categorized result for subsequent processing, a person of having ordinary skill in the art (PHOSITA) would find the claim limitations of claims 42 and 44 obvious to implement.
Regarding claim 43 and 45
Claim 43 adds limitation of generating information including a probability for each cell type and claim 45 adds limitation of transmitting analysis results including cell type probability to a processing unit.
Both limitations of claim 43 and 45 disclosed by Li et al., which outputs probability scores (dropout probability) for each possible cell type from a deep learning classifier and communicates such probabilistic outputs for further downstream analysis (pg. 5, bottom; Figure 5) suggesting the claim limitation of claim 43 and 45 recited above.
Outputting class probabilities in addition to or instead of hard labels was standard feature of deep learning classifiers well before the effective filing date of the invention. A PHOSITA would have been motivated to incorporate probability outputs from Li et al. into the Diebold system to provide clinically useful confidence scores alongside cell type classifications.
Regarding claim 49:
Claim 49 recites that the AI algorithm is a deep learning algorithm.
This limitation is fully disclosed by Li et al., which teaches the application of a deep learning algorithm (specifically, a conventional neural network) to classify cell types based on flow cytometry-derived data (Abstract) suggesting the limitation of AI algorithm which is a deep learning algorithm.
Incorporating a deep learning algorithm for cell classification would have been an obvious design choice to a person having ordinary skill in the art (PHOSITA) prior to the effective filing date because well before the effective filing date, deep learning was widely recognized for its superior ability to handle complex pattern recognition tasks compared to classical machine learning and substitution of a deep neural network for a traditional machine learning or rule-based classifier constitutes the mere application of a known technique to a known device or method.
Regarding claim 50:
Claim 50 recites that second processor executes, in parallel as the parallel processing, a filtering process for extracting a feature of the data.
Ortyn et al. discloses digital filtering operations applied in parallel to multichannel cytometric waveform data to extract cellular features (pg. 3, c1, middle; pg. 22, c2, middle; pg. 24, c1, bottom).
Li et al. further discloses that convolutional layers in deep learning function as learnable feature extraction filters applied in parallel to input data matrices (Li, col. 5, line 30-55)
The combined references above reads the claim limitation of “the second processor is configured to execute, in parallel as the parallel processing, a filtering process for extracting a feature of the data.”
Regarding claim 51:
Claim 51 recites AI algorithm is a deep learning algorithm; second processor executes in parallel a plurality of arithmetic processes in a convolution layer of the deep learning algorithm.
The above limitation of claim 51 is addressed by Li et al, which discloses parallel execution of convolution layer computations on GPU hardware as a fundamental aspect of deep learning inference (Abstract; pg. 2, middle; Figure 1, pg. 7, bottom; pg. 9, middle).
Parallel convolution computation on GPU was not merely known but was the dominant implementation paradigm for deep learning before effective filing date. A PHOSITA would have been motivated at the time of effective filing date to use parallel convolution computation to speed up the analysis of such complex dataset.
Claim 37-40, 46-48 and 52 are rejected under 35 U.S.C. 103 as unpatentable over Diebold et al. in view of Ortyn et al. and Li et al. as applied to claims 34, 35, 36, 41-45, and 49-51 above and further in view of Isozaki et al. (NATURE PROTOCOLS |VOL 14 |AUGUST 2019 | 2370–2415)
Diebold et al. in view of Ortyn et al. and Li et al. are applied to claims 34, 35, 36, 41-45, and 49-51.
Regarding claim 37 and 38:
Claim 37 recites “the matrix data is transmitted to the second processor via a transmission line included in the cell analyzer.” And claim 38 recites “the matrix data is transmitted to the second processor via a transmission line different from an Internet or an intranet.”
Diebold et al. in view of Ortyn et al. and Li et al. does not explicitly teach transmission of matrix data via transmission line and matrix data transmission via Internet or an intranet.
The prior art by Isozaki et al. teaches the use of internal high-speed data buses inside cytometry instruments to transfer digitized cell data to coprocessors (pg. 2, bottom; pg. 14, bottom; pg. 30, bottom). Furthermore, deploying direct, high-speed internal data transmission lines was the standard architecture in scientific instrumentation at the time.
A person having ordinary skill in the art at the time of the effective filing date would have been motivated to further combine the teachings of Isozaki et al. with the combined system of Diebold et al., Ortyn et al., and Li et al. to arrive at the claimed invention with a reasonable expectation of success, for the following reasons
Having arrived at combined Diebold/Ortyn/Li system in which a flow cytometer digitizes per-cell optical signals into matrix data (Diebold, Col. 24, lines 30-55, Figs 11B, 27; Ortyn, p.6, c1, middle) for processing by a second, parallel processor executing a matrix-operation-based AI algorithm (Li, p. 2, bottom; Fig. 2; p. 7, bottom; Fig. 6), a PHOSITA would have recognized the need to transfer that matrix data from the point of acquisition to the second processor. Isozaki teaches the use of internal high-speed data buses inside cytometry instruments to transfer digitized cell data to coprocessors (Isozaki, pg. 2, bottom; pg. 14, pg. 30 bottom)
A PHOSITA would have been motivated to adopt Isozaki’s internal high-speed data bus architecture as the specific transmission line connecting the flow cytometer/first processor to the second, parallel processor within the Diebold/Ortyin/Li cell analyzer, because Isozaki confirms that deploying direct, high speed internal data transmission lines was the standard architecture in scientific instrumentation at the time (Isozaki, pg. 2, bottom; pg. 14, bottom; pg. 30, bottom). Applying this known, standard architecture to transfer the already-taught matrix data within the combined system amounts to nothing more than the combination of prior art elements according to known methods to yield the predictable result of reliable, low-latency delivery of matrix data to the second processor. (MPEP 2143(A); KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Because internal high-speed data buses were the standard means of moving digitized instrument data to a processor housed within the same instrument, A PHOSITA would have known how and why to implement such a transmission line “included in the cell analyzer” as recited in claim 37, with a reasonable expectation of success. The claimed transmission line is therefore a predictable application of Isozaki’s known teaching to the combined Diebold/Ortyn/Li system, representing a routine design choice rather than patentable advance. (MPEP 2143 (C)
A PHOSITA would likewise have been motivated to implement the transmission line of claim 38 as a dedicated line different from an Intranet or an intranet. Isozaki’s teaching of internal high-speed data buses used to transfer digitized cell data to coprocessors within the cytometry instrument itself (Isozaki, pg. 2, bottom; pg. 14, bottom; pg. 30 bottom) is a direct, point-to-point instrument-internal connection rather than a networked connection routed over the Internet or an intranet.
A PHOSITA seeking to transfer matrix data from the flow cytometer/first processor to the second processor within the combined Diebold/Ortyn/Li cell analyzer would have recognized that using an internal high-speed bus of the type taught by Isozaki, rather than a general-purpose network connection such as Internet or an intranet, was the standard architecture for scientific instrumentation at the time (Isozaki, pg. 2. Bottom; pg. 14, bottom; pg. 30, bottom), and would have been motivated to select such a dedicated, non-network transmission line to achieve the predictable benefits of higher transfer speed, lower latency, and greater reliability associated with direct internal data buses as compared to networked transmission.
The combination amounts to no more than the application of a known technique, namely Isozaki’s internal high-speed, non-network data bus architecture, to a known device, namely the combined Diebold/Ortyn/Li cell analyzer that was ready for improvement, to yield the predictable result of fast and reliable matrix data transmission without reliance on an Internet or intranet connection. (MPEP 2143(D); KSR, 550 U.S. at 417.
Accordingly, a PHOSITA would have had ample motivation, supported by the teaching of Isozaki et al. and the combined teaching of Diebold, Ortyn, and Li, together with a reasonable expectation of success, to further combine these references to arrive at the cell analyzer of claim 37 and 38, in which the matrix data is transmitted to the second processor via a transmission line included in the cell analyzer and different from an Internet or an intranet.
Regarding claim 39:
Claim 39 recites “the transmission line has a communication band of not less than I gigabit/second.”
The Isozaki et al. reference teaches internal data links running at gigabit-per-second speeds to support the transfer of high-throughput cytometric data. Therefore, the concept of using a ≥ 1Gb/s transmission line in cytometry was already established and publicly available.
Well before the effective filing date (EFD), data interfaces like Gigabit Ethernet and PCIe buses were ubiquitous in computing hardware. Utilizing these widely adopted, standard technologies to achieve ≥ 1Gb/s data transfer rates was routine for any computer hardware developer.
To build a high-throughput flow cytometry system, managing massive volumes of data is essential. Using a standard, high-bandwidth transmission line is an obvious engineering solution to accommodate that data load. A PHOSITA designing such a system would predictably select a standard gigabit interface to ensure the system functioned reliably.
Regarding claim 40:
Claim 40 recites “the transmission line is a bus, and the data is transmitted to the second processor via the bus.”
Transmission line is a bus; data transmission via a bus is disclosed by Isozaki et al., which describes a high-speed data bus (e.g., PCIe) for transferring data between processor within the instruments (pg. 14, bottom) suggesting the claim limitation of “the transmission line is a bus, and the data is transmitted to the second processor via the bus.” Bus-based inter-processor communication was standard practice before the effective filing date with well understood, predictable results.
Regarding claim 46:
Claim 46 recites second processor executes a plurality of arithmetic processes in parallel processing, a plurality of arithmetic processes regarding analysis of the data.
The above limitation in claim 46 is disclosed by Isozaki et al., which describes and FPGA or GPU second processor comprising multiple parallel arithmetic processing elements executing arithmetic operations simultaneously on cytometry data (pg. 14, bottom, pg. 16, top, pg. 25, bottom, pg. 31). These hardware devices are built specifically for parallel processing. They contain many small processing units that perform math operations concurrently. Therefore, utilizing them to analyze data in parallel, as recited in Claim 46, applies standard computing principles.
Regarding claim 47:
Claim 47 recites second processor comprises a plurality of arithmetic units each performing a calculation on an assigned subset of a matrix operation; second processor executes arithmetic processes by respective arithmetic units in parallel.
The above limitation of claim 47 is disclosed by Isozaki et al. in combination with Li et al.
Isozaki et al. discloses multiple parallel arithmetic units (pg. 2, middle, pg. 13, bottom)
Li et al. discloses that GPU cores each execute assigned subsets of matrix multiplication operations in parallel within a deep learning system. (Abstract; Figure 1; pg. 7, bottom). The combination makes this claim obvious.
Regarding claim 48:
Claim 48 recites “first processor divides the matrix operation into subsets and assigns them to arithmetic units of the second processor.”
This method is standard and conventional in parallel computing, where multiple processors work together to solve a problem faster.
A person skilled in the art would find this obvious for the following reasons:
Efficiency: A matrix (a grid of numbers) requires heavy computer memory. Splitting it up allows the computer to process data while using less active memory at any given time.
Speed: Dividing large tasks and sending them to different processing units lets the computer work on many parts of the problem at the same time. This speeds up data analysis.
Routine optimization: Breaking complex math problems into smaller chunks and sending them to separate processors is a common, predictable technique in computer science to improve system performance.
Regarding claim 52:
Claim 52 recites that the second processor executes the parallel processing in accordance with a single order (i.e., a single instruction dispatched to multiple parallel execution units, consistent with SIMD-single Instruction, multiple data architecture.
Isozaki et al. discloses an FPGA/GPU parallel processing architecture in which a single instruction is broadcast to multiple arithmetic units that simultaneously execute the same operation on different data subsets- a classic single Instruction, multiple data paradigm (pg. 14, bottom; pg. 16, top) suggesting the limitation of claim 52.
Single Instruction, multiple data (SIMD) execution was a foundational and well-known feature of GPU and FPGA architectures before the effective filing date, and a PHOSITA implementing a parallel processing second processor for matrix operations would predictably employ single Instruction, multiple data execution as standard optimization.
Conclusion
No claims are allowed.
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/A.H.K./Examiner, Art Unit 1686
/LARRY D RIGGS II/Supervisory Patent Examiner, Art Unit 1686
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