DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of in the reply filed on 02/04/2026 is acknowledged. Claims 5, 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected method and species 1-5, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hurni et al. [US 2022/0231192 A1], “Hurni”.
Regarding claim 1, Hurni discloses a Light Emitting Diode (LED) structure (Fig. 11A, 1100), comprising:
a substrate structure (1110);
at least one LED light emitting unit (1105) located on the substrate structure (as shown), the LED light emitting unit comprising a first semiconductor layer (1130), a light emitting layer (1140) and a second semiconductor layer (1150) which are stacked (as shown); and
a first stress layer (¶[0143]) surrounding the LED light emitting unit and covering a side wall of the LED light emitting unit, wherein the first stress layer is configured to apply a compressive stress to the side wall of the LED light emitting unit in a direction perpendicular to the side wall of the LED light emitting unit, and apply a tensile stress to the side wall of the LED light emitting unit in a direction parallel to the side wall of the LED light emitting unit (¶[0007], ¶[0046] and ¶[0143] teaches a layer of a material (e.g., a dielectric, or semiconductor material) with a lattice constant different from the lattice constant of the quantum well material may be formed on the surfaces of the sidewalls to relax or change the stress to the opposite stress at the sidewall regions of the quantum well layers).
Regarding claim 2, Hurni discloses claim 1, Hurni discloses the first stress layer (¶[0143] teaches a layer of a material (e.g., a dielectric, or semiconductor material) is insulated from the LED light emitting unit (1105).
Regarding claim 10, Hurni discloses claim 1, Hurni discloses the LED structure further comprises: a first electrode (Fig. 11A, 1170) electrically connected to the first semiconductor layer (1130); and a second electrode (1160) electrically connected to the second semiconductor layer (1150).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hurni et al. [US 2022/0231192 A1], “Hurni” as applied to claim 1 above, and further in view of Yu et al. [US 2010/0001257 A1], “Yu”.
Regarding claim 3, Hurni discloses claim 1, Hurni disclose dielectric materials can be SiO2 or SiNX (¶[0110]). Hurni does not explicitly discloses a material of the first stress layer comprises one or more of SiN, SiO2 and diamond-like materials.
However, Yu discloses an LED (Fig. 1, 101) with stress-alleviation layer regions (104) may be comprised of SiO2, SiN, III-Nitrides, or combinations thereof (¶[0021]). Stress-alleviation islands may be of any shape and size and may be formed in LEDs to relieve residual stresses internal to LEDs (¶[0030]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a stress-alleviation material (SiO2 or SiN material) as taught in Yu in the device of Hurni such that the material of the first stress layer comprises one or more of SiN, SiO2 and diamond-like materials because selecting a suitable material will help relieve residual stresses internal to LEDs (¶[0030] of Yu). Further, the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (see MPEP 2144.07).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hurni et al. [US 2022/0231192 A1], “Hurni” as applied to claim 1 above, and further in view of Shur et al. [US 2018/0342649 A1], “Shur”.
Regarding claim 4, Hurni discloses claim 1, Hurni disclose discloses the tensile stress may also be increased by changing the thickness of the quantum well layers and/or the underlying layer, and/or by relaxing the underlying layer to increase the lattice constant of the underlying layer (¶[0131]). Hurni does not disclose the first stress layer has a trench, and the trench at least partially penetrates the first stress layer.
However, Shur disclose heterostructure (Fig. 1, 10) includes a semiconductor layer (14B) having modulated stresses. The stress modulation can occur due to a stress controlling layer (16). In particular, the stress controlling layer (16) has at least one attribute that varies laterally to create varying stresses in the semiconductor layer (14B). The stress controlling layer (16) has a variable thickness that creates variable stresses in different portions of the semiconductor layer (14B) (¶[0039]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create an opening in the stress controlling layer as taught in Shur in the device of Hurni such that the first stress layer has a trench, and the trench at least partially penetrates the first stress layer because such a modification of varying the thickness by creating openings can create various stress (tensile/compression) on different parts of the semiconductor layer (¶[0039] of Shur).
Allowable Subject Matter
Claims 6-9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al. [US 2010/0001257 A1] teaches the LED includes a stress-alleviation layer on a substrate.
Ahmed [US 2019/0355878 A1] teaches LED with the first and second dielectric layers are low-k dielectric layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897