Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action is sent in response to Applicant’s Communication received on 03/16/2026 for application number 18/185,918.
Response to Amendments
3. The Amendment filed 03/16/2026 has been entered. Claims 1, 4, 8, 10, 12, and 19 have been amended. Claims 1-19 remain pending in the application.
4. Applicant’s amendments to claims 1 and 8 have been fully considered and are persuasive. The amendments provided to overcome the 35 U.S.C §112(b) rejection issued in the last office action is sufficient. The 35 U.S.C §112(b) rejection of claims 1 and 8 is respectfully withdrawn.
5. Applicant’s amendment to claim 19 has been fully considered and is persuasive. The amendment provided to overcome the 35 U.S.C. § 101 rejection issued in the last office action is sufficient. The 35 U.S.C. § 101 rejection of claim 19 is respectfully withdrawn.
Response to Arguments
First, Applicant argues that McClatchey does not teach the neural cores being caused to perform a set of one or more tensor arithmetic operations to determine a value indicative of whether a branching condition for a conditional branching instruction is satisfied, and Applicant points to paragraph [0003] as allegedly teaching that this is performed by the controller rather than by the neural cores. Examiner respectfully disagrees, paragraph [0003] states that the controller is configured to concurrently compute a plurality of relational operators on a plurality of inputs, combine the plurality of results to determine an index, select an operation based on the index, and cause the at least one processing core to execute the selected operation. However, that disclosure does not require that the controller act alone or apart from the core computation hardware. McClatchey discloses that the global microengine and local core controller collaboratively direct operations, that each core includes a computation unit operative to perform vector computation, and that the neural computation unit performs computation as directed by the local core controller. McClatchey further teaches that the core microcode includes instructions to execute a full, single tensor operation, for example a convolution between a weight tensor and a data tensor. Thus, paragraph [0003] is reasonably read on the above argued features, rather than a controller operating in complete isolation from the neural cores.
Second, Applicant argues that the operation in paragraphs 70 to 78 is apparently performed by the controller (i.e. the "microengine 413"). Therefore, any values indicative of whether a branching condition is satisfied are taught to be evaluated by the controller, not by the neural cores. Examiner respectfully disagrees, paragarphs [0070]-[0078] disclose a conditional instruction mechanism in which conditions are referenced, their states are queried, and an operation or no-operation is performed depending on those condition states. Further, McClatchey makes clear that controller directed functionality operates in conjunction with tensor/vector execution hardware.
Third, Applicant argues that McClatchey does not teach any control unit that, in response to a conditional branching instruction, will cause an execution unit to perform tensor arithmetic operations to determine a value indicative of whether a branching condition for the conditional branching instruction is satisfied, or of the benefits that can be provided by having the same execution unit that executes 'normal' instructions to perform tensor arithmetic also determine such value. Examiner respectfully disagrees, the claim does not require any express statement of benefits, nor does it require McClatchey to separately emphasize that the same execution unit performs both “normal” tensor operations and conditional-related operations. McClatchey discloses controller/microengine circuitry processing instruction sequences and directing tensor/vector execution by the computation unit, while also disclosing conditional instructions/conditional Ops whose evaluated condition states to determine which operation is performed.
Fourth, Applicant argues that paragraphs 89, 110, 111, and accompanying Figure 14 only disclose example architecture including registers, counters and variables for calculating branching conditions in the controller. Examiner respectfully disagrees, McClatchey discloses an integrated condition evaluation and execution selection mechanism, not merely controller registers in isolation.
Fifth, Applicant argues that Paragraph 65 and accompanying Figure 8 only disclose a flowchart for evaluating an instruction, checking whether a branching condition is true or false, and jumping to different parts of the code for each verdict. None of these paragraphs disclose any execution circuit determining a value that the branching condition is satisfied, or therefore, the execution communicating such value back to the control circuit. Examiner respectfully disagrees, McClatchey discloses IPU architecture and the conditional Op implementation. Paragraph [0065] shows that McClatchey contemplates conditional evaluation and different execution paths based on the condition outcome. Thus, McClatchey teaches a processor in which condition indicative values are generated with the processor and used in the control selection path to determine which operation path is taken.
Sixth, Applicant argues that there is no discussion of here that this is done by an execution unit that would normally write its results to memory, or that the execution unit is prevented from writing the results of any calculations to determine the branching condition to memory. Examiner respectfully disagrees, McClatchey teaches that memory writeout is controller-directed rather than automatic,in that the microengine issues compute operations and separately issues write memory address operations when output data are to be written to memory, and further teaches that instructions may read or write activation memory and partial sum memory. Thus, McClatchey teaches that the condition result values used for conditional operation selection are consumed with the control selection path, i.e., the control circuit prevents writeout of the results used to determine the branching condition value to memory.
Finally, Applicant argues that there is no disclosure in these paragraphs of including into the conditional branching instruction a suitable indicator that memory write out should be selectively disabled. Examiner respectfully disagrees, McClatchey teaches that the encoded conditional instruction information serves as the claimed indicator for selectively disabling memory writeout for conditional evaluation path.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by McClatchey et al. (U.S. Patent Application Pub. No. US 20250028534 A1).
Claim 1: McClatchey teaches a method of operating a processor that is configured to perform neural network processing (i.e. An inference processing unit is a category of processors that perform neural network inference. A neural inference chip is a specific physical instance of an inference processing unit; para. [0040]),
the processor (i.e. An inference processing unit is a category of processors that perform neural network inference. A neural inference chip is a specific physical instance of an inference processing unit; para. [0040]) comprising:
an execution unit configured to perform tensor arithmetic operations (i.e. A neural core 100 is a tileable computational unit that computes one block of an output tensor. A neural core 100 has M inputs and N outputs. In various embodiments, M=N. To compute an output tensor block, a neural core multiplies an M×1 input tensor block 101 with an M×N weight tensor block 102 and accumulates the products into weighted sums that are stored in a 1×N intermediate tensor block 103; para. [0037, 0051]); and
a control circuit that is operable to process sequences of instructions for programs for execution by the processor to perform neural network processing (i.e. In various embodiments a microengine 204 is included in IPU 200. In such embodiments, all operations in the IPU are directed by the microengine. As set out below, central and/or distributed microengines may be provided in various embodiments. A global microengine may be referred to as a chip microengine, while a local microengine may be referred to as a core microengine or local controller; para. [0042]), wherein in response to processing instructions in a sequence of instructions the control circuit is operable to cause the execution unit to perform tensor arithmetic operations for the neural network processing (i.e. Accordingly, in operation, a core control microengine (e.g., 413) orchestrates the data movement and computation of the core. The microengine issues a read activation memory address operation to load an input activation block into the vector-matrix multiply unit. The microengine issues a read weight memory address operation to load a weight block into the vector-matrix multiply unit. The microengine issues the vector-matrix multiply unit a compute operation, causing the vector-matrix multiply unit to compute a partial sum block; para. [0053]);
the method comprising:
the control circuit processing a sequence of instructions for a program for execution by the processor to perform neural network processing (i.e. Accordingly, in operation, a core control microengine (e.g., 413) orchestrates the data movement and computation of the core. The microengine issues a read activation memory address operation to load an input activation block into the vector-matrix multiply unit. The microengine issues a read weight memory address operation to load a weight block into the vector-matrix multiply unit. The microengine issues the vector-matrix multiply unit a compute operation, causing the vector-matrix multiply unit to compute a partial sum block; para. [0053]), the sequence of instructions including a conditional branching instruction having an associated branching condition (i.e. Conditional computation allows for the selection of an action to perform based on one or more conditions. An exemplary code block is as follows: if (statement) then // perform an action else if (other statement) then // perform a different action else // perform a fallback action. The action that is taken when performing this operation is called a “branch”; para. [0063]) that when satisfied will cause the program execution to branch to a different part of the program when the conditional branching instruction is encountered (i.e. FIG. 8 depicts a flowchart of a conditional jump approach to conditional execution with two branches 802, 804. Upon evaluating the instruction at 803, if the condition is true, the process flows through branch 802 and advances, or “jumps” to the code for calculating the corresponding designated operation. If the condition is false, the process flows through branch 804 and advances, or “jumps” to the code for calculating the corresponding designated operation. These conditional jump approaches can be implemented in a variety of systems, some exemplary ones are depicted in FIG. 8; para. [0065]);
wherein the control circuit processing the sequence of instructions including the conditional branching instruction (i.e. FIG. 22, a method for conditional computation is illustrated according to embodiments of the present disclosure. At 2201, a plurality of relational operators is concurrently computed on a plurality of inputs, resulting in a plurality of results. At 2202, the plurality of results is combined to determine an index. At 2203, an operation is selected based on the index. At 2204, the selected operation is executed by at least one processing core; para. [0121]) includes the control circuit causing the execution unit to perform a set of one or more tensor arithmetic operations to determine a value indicative of whether the branching condition for the conditional branching instruction is satisfied (i.e. According to embodiments of the present disclosure, processor chips are provided. In various embodiments, a chip comprises at least one processing core; a controller operatively coupled to the at least one processing core; and an instruction memory in communication with the controller. The controller is configured to: concurrently compute a plurality of relational operators on a plurality of inputs, resulting in a plurality of results; combine the plurality of results to determine an index; select an operation based on the index; and cause the at least one processing core to execute the selected operation; para. [0003, 0070-0078]), the execution unit being further configured to communicate the value indicative of whether the branching condition for the conditional branching instruction is satisfied to the control unit (i.e. The conditional Op in the Conditional Op Buffer 1407 selects up to 4 singleton condition definitions, located in the Singleton Condition Op Buffer 1405. The current binary states of the singleton conditions are combined with an offset to construct a pointer into the truth table of a condition set, located in the Conditional Datapath Op Pointer Buffer 1409. The condition set in the Conditional Datapath Op Pointer Buffer 1409 is a list of pointers into the Datapath Op Buffer 1410 that specify which DATA_OP to execute for each entry in the truth table; para. [0089, 0110, 0111]);
the method further comprising:
when the branching condition is satisfied, the execution unit communicating to the control circuit a value indicating that the branching condition is satisfied (i.e. FIG. 8 depicts a flowchart of a conditional jump approach to conditional execution with two branches 802, 804. Upon evaluating the instruction at 803, if the condition is true, the process flows through branch 802 and advances, or “jumps” to the code for calculating the corresponding designated operation. If the condition is false, the process flows through branch 804 and advances, or “jumps” to the code for calculating the corresponding designated operation. These conditional jump approaches can be implemented in a variety of systems, some exemplary ones are depicted in FIG. 8; para. [0065]), such that when the conditional branching instruction is processed by the control circuit, the conditional branching instruction triggers a branch to a different part of the program execution (i.e. FIG. 8 depicts a flowchart of a conditional jump approach to conditional execution with two branches 802, 804. Upon evaluating the instruction at 803, if the condition is true, the process flows through branch 802 and advances, or “jumps” to the code for calculating the corresponding designated operation. If the condition is false, the process flows through branch 804 and advances, or “jumps” to the code for calculating the corresponding designated operation. These conditional jump approaches can be implemented in a variety of systems, some exemplary ones are depicted in FIG. 8; para. [0065]),
the control circuit then continuing processing instructions for the different part of the program (i.e. FIG. 8 depicts a flowchart of a conditional jump approach to conditional execution with two branches 802, 804. Upon evaluating the instruction at 803, if the condition is true, the process flows through branch 802 and advances, or “jumps” to the code for calculating the corresponding designated operation. If the condition is false, the process flows through branch 804 and advances, or “jumps” to the code for calculating the corresponding designated operation. These conditional jump approaches can be implemented in a variety of systems, some exemplary ones are depicted in FIG. 8; para. [0065, 0071-0078]).
Claim 2: McClatchey teaches the method of claim 1. McClatchey further teaches wherein the execution unit performing the set of one or more tensor arithmetic operations to determine a value indicative of whether the branching condition for the conditional branching instruction is satisfied comprises the execution unit calculating a single bit value indicating whether or not the branching condition is satisfied (i.e. A value of 1 is to be used if the condition is true, or 0 if it is false; para. [0071, 0072]), the single bit value being communicated to the control circuit (i.e. The conditional Op in the Conditional Op Buffer 1407 selects up to 4 singleton condition definitions, located in the Singleton Condition Op Buffer 1405. The current binary states of the singleton conditions are combined with an offset to construct a pointer into the truth table of a condition set, located in the Conditional Datapath Op Pointer Buffer 1409; para. [0110, 0111]), and used as input to the conditional branching instruction to determine whether or not a branch should be performed (i.e. FIG. 8 depicts a flowchart of a conditional jump approach to conditional execution with two branches 802, 804. Upon evaluating the instruction at 803, if the condition is true, the process flows through branch 802 and advances, or “jumps” to the code for calculating the corresponding designated operation. If the condition is false, the process flows through branch 804 and advances, or “jumps” to the code for calculating the corresponding designated operation. These conditional jump approaches can be implemented in a variety of systems, some exemplary ones are depicted in FIG. 8; para. [0065, 0083-0085]).
Claim 3: McClatchey teaches the method of claim 1. McClatchey further teaches wherein the control circuit prevents the execution unit from writing out the results of the set of one or more tensor arithmetic operations to determine a value indicative of whether the branching condition for the conditional branching instruction is satisfied to memory (i.e. [0082] A reference to a Look-Up Table (LUT), each entry of which refers either to an operation that is to be performed (OP), or to no operation (No-OP). When an instruction is to be executed: [0083] The states c.sub.1, . . . , c.sub.M of the M referenced conditions are queried. [0084] An index into the LUT is constructed by the formula index=Σ.sub.i=1.sup.M2.sup.i-1c.sub.i. [0085] The OP or No-OP at the indexed location in the referenced LUT is performed).
Claim 4: McClatchey teaches the method of claim 3. McClatchey further teaches wherein the conditional branching instruction includes an indicator that memory write out should be selectively disabled (i.e. [0082] A reference to a Look-Up Table (LUT), each entry of which refers either to an operation that is to be performed (OP), or to no operation (No-OP). When an instruction is to be executed: [0083] The states c.sub.1, . . . , c.sub.M of the M referenced conditions are queried. [0084] An index into the LUT is constructed by the formula index=Σ.sub.i=1.sup.M2.sup.i-1c.sub.i. [0085] The OP or No-OP at the indexed location in the referenced LUT is performed).
Claim 5: McClatchey teaches the method of claim 1. McClatchey further teaches wherein the conditional branching instruction (i.e. Conditional computation allows for the selection of an action to perform based on one or more conditions. An exemplary code block is as follows: if (statement) then // perform an action else if (other statement) then // perform a different action else // perform a fallback action. The action that is taken when performing this operation is called a “branch”; para. [0063]) indicates the start of the different part of the program (i.e. FIG. 8 depicts a flowchart of a conditional jump approach to conditional execution with two branches 802, 804. Upon evaluating the instruction at 803, if the condition is true, the process flows through branch 802 and advances, or “jumps” to the code for calculating the corresponding designated operation. If the condition is false, the process flows through branch 804 and advances, or “jumps” to the code for calculating the corresponding designated operation. These conditional jump approaches can be implemented in a variety of systems, some exemplary ones are depicted in FIG. 8; para. [0065, 0083-0085]).
Claim 6: McClatchey teaches the method of claim 1. McClatchey further teaches wherein the execution unit comprises one or more fixed function tensor arithmetic units (i.e. To compute an output tensor block, a neural core multiplies an M×1 input tensor block 101 with an M×N weight tensor block 102 and accumulates the products into weighted sums that are stored in a 1×N intermediate tensor block 103. A O×N parameter tensor block contains the O parameters that specify each of the N neuron activation functions that are applied to the intermediate tensor block 103 to produce a 1×N output tensor block 105; para. [0037, 0051]), and wherein the one or more fixed function tensor arithmetic units are used to determine whether the branching condition for the conditional branching instruction is satisfied (i.e. FIG. 22, a method for conditional computation is illustrated according to embodiments of the present disclosure. At 2201, a plurality of relational operators is concurrently computed on a plurality of inputs, resulting in a plurality of results. At 2202, the plurality of results is combined to determine an index. At 2203, an operation is selected based on the index. At 2204, the selected operation is executed by at least one processing core; para. [0121]).
Claim 7: McClatchey teaches the method of claim 6. McClatchey further teaches wherein the one or more fixed function tensor arithmetic units are configured to perform multiply-accumulate operations (i.e. To compute an output tensor block, a neural core multiplies an M×1 input tensor block 101 with an M×N weight tensor block 102 and accumulates the products into weighted sums that are stored in a 1×N intermediate tensor block 103. A O×N parameter tensor block contains the O parameters that specify each of the N neuron activation functions that are applied to the intermediate tensor block 103 to produce a 1×N output tensor block 105; para. [0037, 0051]).
Claims 8-19 are similar in scope to Claims 1-7 and are rejected under a similar rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Bajic et al. (Pub. No. US 20180293486 A1), Computer-implemented methods and associated hardware for executing directed graphs are disclosed herein. An example method includes deriving a simplified version of a directed graph, applying a pilot input tensor to the simplified version of the directed graph, and obtaining a collection of execution data during the application of the pilot input tensor to the simplified version of the directed graph. The method also includes applying a live input tensor to the directed graph and conditioning the execution of the directed graph using the collection of execution data. An output tensor is obtained from the conditional execution of the directed graph.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN TRAN whose telephone number is (303)297-4266. The examiner can normally be reached on Monday - Thursday - 8:00 am - 5:00 pm MT.
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/TAN H TRAN/Primary Examiner, Art Unit 2141
Prosecution Insights