DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed November 25, 2025 has been accepted and entered. Accordingly, claims 1, 4, 7, 8, 11, 14, 17, and 20 are amended, and claims 3, 10 and 16 are cancelled.
Claims 1-2, 4-9, 11-15 and 17-20 are pending in this application.
Response to Arguments
Applicant's arguments filed November 25, 2025 have been fully considered but they are not persuasive.
Regarding the Applicant’s arguments with respect to claim 1 that “Geng's transmission frame does not include an indicator field where one value in the indicator field indicates a first value, wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame, wherein each of the segments comprises Y bits” (Response filed November 25, 2025, Pages 10-13) and “Kwon and Thaler do not overcome the deficiencies in Geng” (Response filed November 25, 2025, Page 13), Examiner respectfully disagrees with the Applicant.
Geng teaches that “The 64 B/65 B coder maps two continuous XGMII transmission frames to a 65-bit 64 B/65 B code block. The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. The 1-bit data/control header identifies the type of the 64-bit data information in the code block. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information.” (Geng [Para. 0193]). According to Geng, a code block includes a data/control header in addition to the 64 bits of data payload in the code block, and the data/control header functions as the indicator field that indicates whether the payload comprises only data or includes control information. Therefore, Geng teaches the indicator field in the code block that indicates whether the payload in 64 bits is data segment.
Furthermore, Kwon teaches that “Additional header for segmentation. Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’” (Kwon ([Page 319]). According to Kwon, a header in addition to the data segment is an indicator that indicates the payload is data segment, and moreover, the first data segment. Therefore, based on the teaching of Geng and Kwon in combination, an indicator field in addition to the payload indicates the payload carries the first segment of the data frame that consists of 64 bits.
Regarding the Applicant’s arguments with respect to claim 1 that “Thaler uses the 2-bit sync field 151 to indicate transition information but nowhere does Thaler disclose any indication in the payload field of the data frame. Further, Thaler does not disclose the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame” (Response filed November 25, 2025, Page 15), Examiner respectfully disagrees with the Applicant.
Thaler provides that “the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words” (Thaler [Para. 0049]), “The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block shown in FIG. 3A, and blocks that include at least one control word, i.e., the Type 2-12 blocks shown in FIGS. 3B-3D” (Thaler [Para. 0058]) and “when the block is a Type 2 through Type 12 block that includes at least one control word. In this case, the master transition in the sync field 151 is 10, and the payload field 152 is composed of the 8-bit sub-field 157 and the 56-bit sub-field 158.” (Thaler [Para. 61]). According to Thaler, the field of two bits in addition to the payload of 64 bits in the code block functions as the indicator field and the value of “10” in the indicator field indicates that the payload comprises the sub-field in the payload to indicate the presence of at least one control word in the payload. More specifically, Thaler states that “Different values of the TYPE word indicate 1) whether the block from which the frame is derived is composed exclusively of control words, 2) the position of the start of a packet and 3) the position of the end of a packet” (Thaler [Para. 0051]), indicating that the sub-field in the payload indicates presence of the control data and the second data packet. Therefore, Thaler teaches when the indicator field in the code block indicates “10” as the fourth value of the four values of the two-bit field, the payload comprises a sub-indicator field in the payload indicating that the payload comprises control information or a second data frame.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 8-9, 11, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Geng et al. (US20100223535A1, hereinafter Geng) in view of Kwon et al. (IEEE Transactions on Broadcasting, Vol. 62, No. 1, March 2016, hereinafter Kwon) and Thaler (US20060268997A1, hereinafter Thaler).
For claim 1, Geng teaches a line coding method ([Para. 0095], a data coding method. [Para. 0096], perform line coding for the input data to generate an information block), comprising: generating a target code block that comprises an indicator field and a payload ([Para. 0096], a1: Perform line coding for the input data to generate an information block and the information block includes information data and a 1-bit first synchronization header. [Para. 0101], a6: Add a 1-bit second synchronization header into the information block in the code sequence. [Para. 0102], The second synchronization header added into the information block that is negation of the first synchronization bit. [Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. The 1-bit data/control header identifies the type of the 64-bit data information in the code block. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information. [Examiner’s Note: Information data is the payload and data/control bit is the indicator field]), wherein one value in the indicator bit indicates a first value ([Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information), or a fourth value ([Para. 0193], if the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information), wherein each of the segments comprises Y bits ([Para. 0192], 64 B/65 B Coding Process. [Para. 0193], The 64 B/65 B coder maps two continuous XGMII transmission frames to a 65-bit 64 B/65 B code block. The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. [Para. 0011], the Ethernet data frame undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. [Examiner’s Note: In both 64 B/65 B and 64 B/66 B coding system, each segment consists of Y = 64 bits]); wherein N is an integer greater than or equal to 1 and Y is an integer greater than 1 ([Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. [Para. 0011], the Ethernet data frame undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. [Examiner’s Note: In both 64 B/65 B and 64 B/66 B coding system, each segment consists of Y = 64 bits. Each code block is counted in N]), and sending the target code block ([Para. 0096], a1: Perform line coding for the input data … to generate an information block...and the information block includes information data and a 1-bit first synchronization header… [Para. 0103], a7: Send the information block with the added second synchronization header and the corresponding check block).
Although teaching generating a code block with indicator bit and sending the code block, Geng does not explicitly disclose wherein one value in the indicator field indicates a first value, a second value, a third value, wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame, wherein the second value indicates that the payload comprises an intermediate segment of the N equal-length segments of the first data frame, wherein the third value indicates that the payload comprises a last segment of the N equal-length segments of the first data frame.
Kwon is directed to providing the ATSC link-layer protocol (ALP) design and efficiency evaluation. More specifically, Kwon teaches wherein one value in the indicator field indicates a first value ([Page 319, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. [Examiner’s Note: A large data packet in upper layer is segmented into data segments each of which is carried in a physical layer ALP packet. An APL packet may have an additional header that functions as the indicator bit indicating that data information]), a second value ([Page 319, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: A value greater than ‘0x0’ indicates an intermediate segment]), a third value ([Page 319, b) Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last), wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame ([Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. [Page 317, left column, first paragraph in section II. ATSC LINK-LAYER PROTOCOL], ALP takes as input network layer packets such as IP and MPEG-2 TS as input packets. [Page 317, left column, third paragraph in section II. ATSC LINK-LAYER PROTOCOL], When the network layer packet is too large to process easily in the physical layer, it is divided into two or more segments [Examiner’s Note: IP and MPEG packets are data frames. In both 64 B/65 B and 64 B/66 B coding system, each segment consists of 64 bits as Geng teaches]), wherein the second value indicates that the payload comprises an intermediate segment of the N equal-length segments of the first data frame ([Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: Each segment consists of 64 bits as Geng teaches]), wherein the third value indicates that the payload comprises a last segment of the N equal-length segments of the first data frame ([Page 319, b) left column, Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last [Examiner’s Note: Each segment consists of 64 bits as Geng teaches]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
Although teaching generating and sending a code block with indicator field indicating values, Geng and Kwon do not explicitly disclose and wherein when the indicator field indicates the fourth value, the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame.
Thaler is directed to providing coding and decoding packetized data. More specifically, Thaler teaches and wherein when the indicator field indicates the fourth value ([Para. 0049], the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words. [Para. 0058], The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block, and blocks that include at least one control word, i.e., the Type 2-12 blocks. [Para. 61], when the block is a Type 2 through Type 12 block that includes at least one control word, the master transition in the sync field is 10, and the payload field is composed of the 8-bit sub-field and the 56-bit sub-field [Examiner’s Note: When the field of two bits is the indicator field. “10” in the indicator field is the fourth value. When the indicator field indicates the fourth value “10’, the payload comprises a sub-indicator field]), the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame ([Para. 0049], the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words. [Para. 0058], The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block, and blocks that include at least one control word, i.e., the Type 2-12 blocks [Para. 0051], Different values of the TYPE word indicate 1) whether the block from which the frame is derived is composed exclusively of control words, 2) the position of the start of a packet and 3) the position of the end of a packet [Examiner’s Note: The types 2-12 indicate control words and second data packet in the payload]. [Para. 0060], when the block is a Type 1 block, the master transition in the sync field is 01, and the payload field is composed of the eight information words. [Para. 61], when the block is a Type 2 through Type 12 block that includes at least one control word, the master transition in the sync field is 10, and the payload field is composed of the 8-bit sub-field and the 56-bit sub-field [Examiner’s Note: “10” in the indicator field is the fourth value. When the indicator field indicates the fourth value “10’, the payload comprises a sub-indicator field indicating that the payload comprises control information and a second data frame]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Kwon, so that a type word in used to indicate control words, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
For claim 4, Geng, Kwon and Thaler teach the method of claim 1. The references further teach wherein the sub-indicator bit indicates that the payload carries the padding bit, the sub-indicator bit indicates that the payload carries the control information (Thaler [Para. 0051], this number of bits can be used to represent a TYPE word that is included in all frames that are not composed exclusively of information words [Examiner’s Note: TYPE word is the sub-indicator that is only present when there is at least one control word in the block]. Thaler [Para. 0060], FIG. 4B shows the structure of the frame 153 generated when the block is a Type 1 block. In this case, the master transition in the sync field 151 is 01, and the payload field 152 is composed of the eight information words constituting the block, i.e., 64 bits. Thaler [Para. 0061], FIG. 4C shows the structure of the frame 156 generated when the block is a Type 2 through Type 12 block that includes at least one control word. In this case, the master transition in the sync field 151 is 10, and the payload field 152 is composed of the 8-bit sub-field 157 and the 56-bit sub-field 158.The 8-bit sub-field 157 is occupied by the TYPE word. Thaler [Para. 0069], The TYPE word indicates one of the following structural properties of the block: 1) whether the block is composed exclusively of control words [Examiner’s Note: The presence of TYPE word indicates that the payload carries control words and TYPE word indicates whether the payload carries control words exclusively]), or the sub-indicator bit indicates that the payload carries the second data framer, and wherein the second data frame is a complete and unsegmented data frame.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Kwon, so that a type word in used to indicate control words, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
For claim 8, Geng teaches a parsing method ([Para. 0114], a data decoding method corresponding to the data coding method), comprising: receiving a target code block ([Para. 0103] and [FIG. 8], a7: Send the information block with the added second synchronization header and the corresponding check block. [Para. 0115], b1: Receive a data frame which includes an initial information block and a corresponding check block), comprising an indicator field and a payload ([Para. 0096], a1: Perform line coding for the input data to generate an information block and the information block includes information data and a 1-bit first synchronization header. [Para. 0101], a6: Add a 1-bit second synchronization header into the information block in the code sequence. [Para. 0102], The second synchronization header added into the information block that is negation of the first synchronization bit. [Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. The 1-bit data/control header identifies the type of the 64-bit data information in the code block. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information. [Examiner’s Note: Information data is the payload and data/control bit is the indicator bit]), wherein one value in the indicator bit comprises a first value ([Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information), or a fourth value ([Para. 0193], if the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information), wherein each of the segments comprises Y bits ([Para. 0192], 64 B/65 B Coding Process. [Para. 0193], The 64 B/65 B coder maps two continuous XGMII transmission frames to a 65-bit 64 B/65 B code block. The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. [Para. 0011], the Ethernet data frame undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. [Examiner’s Note: In both 64 B/65 B and 64 B/66 B coding system, each segment consists of Y = 64 bits]); wherein N is an integer greater than or equal to 1 and Y is an integer greater than 1 ([Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. [Para. 0011], the Ethernet data frame undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. [Examiner’s Note: In both 64 B/65 B and 64 B/66 B coding system, each segment consists of Y = 64 bits. Each code block is counted in N]); and parsing the target code block ([Para. 0115], b1: Receive a data frame which includes an initial information block and a corresponding check block... [Para. 0121], b7: Perform line decoding for the information blocks after the splitting to recover data).
Although teaching generating a code block with indicator bit and sending the code block, Geng does not explicitly disclose wherein one value in the indicator field indicates a first value, a second value, a third value, wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame, wherein the second value indicates that the payload comprises an intermediate segment of the N equal-length segments of the first data frame, wherein the third value indicates that the payload comprises a last segment of the N equal-length segments of the first data frame.
Kwon is directed to providing the ATSC link-layer protocol (ALP) design and efficiency evaluation. More specifically, Kwon teaches wherein one value in the indicator field indicates a first value ([Page 319, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. [Examiner’s Note: A large data packet in upper layer is segmented into data segments each of which is carried in a physical layer ALP packet. An APL packet may have an additional header that functions as the indicator bit indicating that data information]), a second value ([Page 319, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: A value greater than ‘0x0’ indicates an intermediate segment]), a third value ([Page 319, b) Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last), wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame ([Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. [Page 317, left column, first paragraph in section II. ATSC LINK-LAYER PROTOCOL], ALP takes as input network layer packets such as IP and MPEG-2 TS as input packets. [Page 317, left column, third paragraph in section II. ATSC LINK-LAYER PROTOCOL], When the network layer packet is too large to process easily in the physical layer, it is divided into two or more segments [Examiner’s Note: IP and MPEG packets are data frames. In both 64 B/65 B and 64 B/66 B coding system, each segment consists of 64 bits as Geng teaches]), wherein the second value indicates that the payload comprises an intermediate segment of the N equal-length segments of the first data frame ([Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: Each segment consists of 64 bits as Geng teaches]), wherein the third value indicates that the payload comprises a last segment of the N equal-length segments of the first data frame ([Page 319, b) left column, Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last [Examiner’s Note: Each segment consists of 64 bits as Geng teaches]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
Although teaching generating and sending a code block with indicator field indicating values, Geng and Kwon do not explicitly disclose and wherein when the indicator field indicates the fourth value, the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame.
Thaler is directed to providing coding and decoding packetized data. More specifically, Thaler teaches and wherein when the indicator field indicates the fourth value ([Para. 0049], the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words. [Para. 0058], The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block, and blocks that include at least one control word, i.e., the Type 2-12 blocks. [Para. 61], when the block is a Type 2 through Type 12 block that includes at least one control word, the master transition in the sync field is 10, and the payload field is composed of the 8-bit sub-field and the 56-bit sub-field [Examiner’s Note: When the field of two bits is the indicator field. “10” in the indicator field is the fourth value. When the indicator field indicates the fourth value “10’, the payload comprises a sub-indicator field]), the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame ([Para. 0049], the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words. [Para. 0058], The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block, and blocks that include at least one control word, i.e., the Type 2-12 blocks [Para. 0051], Different values of the TYPE word indicate 1) whether the block from which the frame is derived is composed exclusively of control words, 2) the position of the start of a packet and 3) the position of the end of a packet [Examiner’s Note: The types 2-12 indicate control words and second data packet in the payload]. [Para. 0060], when the block is a Type 1 block, the master transition in the sync field is 01, and the payload field is composed of the eight information words. [Para. 61], when the block is a Type 2 through Type 12 block that includes at least one control word, the master transition in the sync field is 10, and the payload field is composed of the 8-bit sub-field and the 56-bit sub-field [Examiner’s Note: “10” in the indicator field is the fourth value. When the indicator field indicates the fourth value “10’, the payload comprises a sub-indicator field indicating that the payload comprises control information and a second data frame]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Kwon, so that a type word in used to indicate control words, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
For claim 9, Geng, Kwon and Thaler teach the parsing method of claim 8. The references further teach wherein parsing the target code block comprises: determining that a segment carried in the payload is the first segment when the indicator bit comprises the first value (Geng [Para. 0114], the data decoding method includes: Geng [Para. 0115], b1: Receive a data frame which includes an initial information block and a corresponding check block. Kwon [Page 317, left column, first paragraph in section II. ATSC LINK-LAYER PROTOCOL], ALP takes as input network layer packets such as IP and MPEG-2 TS as input packets. Kwon [Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to‘0x0’); determining that the segment carried in the payload is the intermediate segment when the indicator bit comprises the second value (Kwon [Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: The additional segment is the intermediate segment]); or determining that the segment carried in the payload is the last segment when the indicator bit of the target code block comprises the third value (Kwon [Page 319, b) left column, Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Thaler, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
For claim 11, Geng, Kwon and Thaler teach the parsing method of claim 8. The references further teach wherein the sub- indicator bit indicates that the payload carries the padding bit, the sub-indicator bit indicates that the payload carries the control information (Thaler [Para. 0051], this number of bits can be used to represent a TYPE word that is included in all frames that are not composed exclusively of information words [Examiner’s Note: TYPE word is the sub-indicator that is only present when there is at least one control word in the block]. Thaler [Para. 0060], FIG. 4B shows the structure of the frame 153 generated when the block is a Type 1 block. In this case, the master transition in the sync field 151 is 01, and the payload field 152 is composed of the eight information words constituting the block, i.e., 64 bits. Thaler [Para. 0061], FIG. 4C shows the structure of the frame 156 generated when the block is a Type 2 through Type 12 block that includes at least one control word. In this case, the master transition in the sync field 151 is 10, and the payload field 152 is composed of the 8-bit sub-field 157 and the 56-bit sub-field 158.The 8-bit sub-field 157 is occupied by the TYPE word. Thaler [Para. 0069], The TYPE word indicates one of the following structural properties of the block: 1) whether the block is composed exclusively of control words [Examiner’s Note: The presence of TYPE word indicates that the payload carries control words and TYPE word indicates whether the payload carries control words exclusively]), or the sub-indicator bit indicates that the payload carries the second data framer and wherein the second data frame is a complete and unsegmented data frame.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Kwon, so that a type word in used to indicate control words, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
For claim 14, Geng teaches a line coding apparatus ([Para. 0232], a data coding apparatus), comprising: a transmitter ([FIG. 2], EPON system. [Para. 0103], a7: Send the information block. [Para. 0193], If the data/control header is 0, the transmitted 64-bit information is data information … [Para. 0231], the foregoing embodiments and application instances may be implemented by hardware instructed by a program [Examiner’s Note: The hardware in EPON system for transmitting a frame to the decoder is a transmitter]); and at least one processor ([Para. 0096- 0101], a1: Perform line coding for the input data ... [Para. 0231], the foregoing embodiments and application instances may be implemented by hardware instructed by a program [Examiner’s Note: The hardware that performs line coding instructed by a program is a processor]); coupled to the transmitter and configured to cause the line coding apparatus to ([FIG. 2], EPON system. [Para. 0096- 0101], a1: Perform line coding for the input data ... [Para. 0103], a7: Send the information block. [Para. 0231], the foregoing embodiments and application instances may be implemented by hardware instructed by a program [Examiner’s Note: The processor and transmitter are connected in hardware so that the code block is transmitted after generated by the processor]): generate a target code block that comprises an indicator field and a payload ([Para. 0096], a1: Perform line coding for the input data to generate an information block and the information block includes information data and a 1-bit first synchronization header. [Para. 0101], a6: Add a 1-bit second synchronization header into the information block in the code sequence. [Para. 0102], The second synchronization header added into the information block that is negation of the first synchronization bit. [Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. The 1-bit data/control header identifies the type of the 64-bit data information in the code block. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information. [Examiner’s Note: Information data is the payload and data/control bit is the indicator bit]), wherein one value in the indicator field comprises a first value ([Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. If the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information), or a fourth value ([Para. 0193], if the data/control header is 0, the transmitted 64-bit information is data information; if the data/control header is 1, the transmitted 64-bit information includes control information), wherein each of the segments comprises Y bits ([Para. 0192], 64 B/65 B Coding Process. [Para. 0193], The 64 B/65 B coder maps two continuous XGMII transmission frames to a 65-bit 64 B/65 B code block. The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. [Para. 0011], the Ethernet data frame undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. [Examiner’s Note: In both 64 B/65 B and 64 B/66 B coding system, each segment consists of Y = 64 bits]); wherein N is an integer greater than or equal to 1 and Y is an integer greater than 1 ([Para. 0193], The 64 B/65 B code block includes 64-bit data information and 1-bit data/control header. [Para. 0011], the Ethernet data frame undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. [Examiner’s Note: In both 64 B/65 B and 64 B/66 B coding system, each segment consists of Y = 64 bits. Each code block is counted in N]); and send, through the transmitter ([Para. 0103], a7: Send the information block. … [Para. 0231], the foregoing embodiments and application instances may be implemented by hardware instructed by a program [Examiner’s Note: The hardware sending the code block to the decoder is the transmitter]), the target code block ([Para. 0096], a1: Perform line coding for the input data … to generate an information block...and the information block includes information data and a 1-bit first synchronization header… [Para. 0103], a7: Send the information block with the added second synchronization header and the corresponding check block).
Although teaching generating a code block with indicator bit and sending the code block, Geng does not explicitly disclose wherein one value in the indicator field indicates a first value, a second value, a third value, wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame, wherein the second value indicates that the payload comprises an intermediate segment of the N equal-length segments of the first data frame, wherein the third value indicates that the payload comprises a last segment of the N equal-length segments of the first data frame.
Kwon is directed to providing the ATSC link-layer protocol (ALP) design and efficiency evaluation. More specifically, Kwon teaches wherein one value in the indicator field indicates a first value ([Page 319, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. [Examiner’s Note: A large data packet in upper layer is segmented into data segments each of which is carried in a physical layer ALP packet. An APL packet may have an additional header that functions as the indicator bit indicating that data information]), a second value ([Page 319, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: A value greater than ‘0x0’ indicates an intermediate segment]), a third value ([Page 319, b) Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last), wherein the first value indicates that the payload comprises a first segment of N equal-length segments of a first data frame ([Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. [Page 317, left column, first paragraph in section II. ATSC LINK-LAYER PROTOCOL], ALP takes as input network layer packets such as IP and MPEG-2 TS as input packets. [Page 317, left column, third paragraph in section II. ATSC LINK-LAYER PROTOCOL], When the network layer packet is too large to process easily in the physical layer, it is divided into two or more segments [Examiner’s Note: IP and MPEG packets are data frames. In both 64 B/65 B and 64 B/66 B coding system, each segment consists of 64 bits as Geng teaches]), wherein the second value indicates that the payload comprises an intermediate segment of the N equal-length segments of the first data frame ([Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: Each segment consists of 64 bits as Geng teaches]), wherein the third value indicates that the payload comprises a last segment of the N equal-length segments of the first data frame ([Page 319, b) left column, Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last [Examiner’s Note: Each segment consists of 64 bits as Geng teaches]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
Although teaching generating and sending a code block with indicator field indicating values, Geng and Kwon do not explicitly disclose and wherein when the indicator field indicates the fourth value, the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame.
Thaler is directed to providing coding and decoding packetized data. More specifically, Thaler teaches and wherein when the indicator field indicates the fourth value ([Para. 0049], the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words. [Para. 0058], The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block, and blocks that include at least one control word, i.e., the Type 2-12 blocks. [Para. 61], when the block is a Type 2 through Type 12 block that includes at least one control word, the master transition in the sync field is 10, and the payload field is composed of the 8-bit sub-field and the 56-bit sub-field [Examiner’s Note: When the field of two bits is the indicator field. “10” in the indicator field is the fourth value. When the indicator field indicates the fourth value “10’, the payload comprises a sub-indicator field]), the payload comprises a sub-indicator bit to indicate that the payload comprises a padding bit, control information, or a second data frame ([Para. 0049], the 64b/66b coding is applied to a total of 64 received bits. The 64b/66b coding adds a master transition composed of 2 bits to the start of the block to form a frame. The master transition serves both as a reference for frame synchronization and as a flag that indicates when the frame is composed exclusively of information words. [Para. 0058], The 12 different types of blocks are indicated by a code that uses a combination of the master transition and the TYPE word. The 12 types of blocks are divided into two different categories, namely, blocks composed exclusively of information words, i.e., the Type 1 block, and blocks that include at least one control word, i.e., the Type 2-12 blocks [Para. 0051], Different values of the TYPE word indicate 1) whether the block from which the frame is derived is composed exclusively of control words, 2) the position of the start of a packet and 3) the position of the end of a packet [Examiner’s Note: The types 2-12 indicate control words and second data packet in the payload]. [Para. 0060], when the block is a Type 1 block, the master transition in the sync field is 01, and the payload field is composed of the eight information words. [Para. 61], when the block is a Type 2 through Type 12 block that includes at least one control word, the master transition in the sync field is 10, and the payload field is composed of the 8-bit sub-field and the 56-bit sub-field [Examiner’s Note: “10” in the indicator field is the fourth value. When the indicator field indicates the fourth value “10’, the payload comprises a sub-indicator field indicating that the payload comprises control information and a second data frame]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng and Kwon, so that a type word in used to indicate control words, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
For claim 17, Geng, Kwon and Thaler teach the line coding apparatus of claim 14. The references further teach wherein the sub-indicator bit indicates that the payload carries the padding bit, the sub-indicator bit indicates that the payload carries the control information (Thaler [Para. 0051], this number of bits can be used to represent a TYPE word that is included in all frames that are not composed exclusively of information words [Examiner’s Note: TYPE word is the sub-indicator that is only present when there is at least one control word in the block]. Thaler [Para. 0060], FIG. 4B shows the structure of the frame 153 generated when the block is a Type 1 block. In this case, the master transition in the sync field 151 is 01, and the payload field 152 is composed of the eight information words constituting the block, i.e., 64 bits. Thaler [Para. 0061], FIG. 4C shows the structure of the frame 156 generated when the block is a Type 2 through Type 12 block that includes at least one control word. In this case, the master transition in the sync field 151 is 10, and the payload field 152 is composed of the 8-bit sub-field 157 and the 56-bit sub-field 158.The 8-bit sub-field 157 is occupied by the TYPE word. Thaler [Para. 0069], The TYPE word indicates one of the following structural properties of the block: 1) whether the block is composed exclusively of control words [Examiner’s Note: The presence of TYPE word indicates that the payload carries control words and TYPE word indicates whether the payload carries control words exclusively]), or the sub-indicator bit indicates that the payload carries the second data framer, and wherein the second data frame is a complete and unsegmented data frame.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng and Kwon, so that a type word in used to indicate control words, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
Claims 2, 7, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Geng et al. (US20100223535A1, hereinafter Geng) in view of Kwon et al. (IEEE Transactions on Broadcasting, Vol. 62, No. 1, March 2016, hereinafter Kwon) and Thaler (US20060268997A1, hereinafter Thaler), and further in view of Leung et al. (US20100070822A1, hereinafter Leung).
For claim 2, Geng, Kwon and Thaler teach the method of claim 1. The references further teach wherein generating the target code block comprises obtaining N code blocks according to the first data frame (Geng [Para. 0096 - 0101], a1: Perform line coding for the input data … to generate an information block...and the information block includes information data and a 1-bit first synchronization header... Kwon [Page 317, left column, first paragraph in section II. ATSC LINK-LAYER PROTOCOL], ALP takes as input network layer packets such as IP and MPEG-2 TS as input packets), wherein the indicator bit comprises the first value when the payload comprises the first segment (Kwon [Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to‘0x0’), wherein the indicator bit comprises the second value when the payload comprises the nth segment (Kwon [Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: The additional segment is the nth segment]) and wherein the indicator bit comprises the third value when the payload comprises the Nth segment (Kwon [Page 319, b) left column, Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Thaler, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
Although teaching generating and sending a code block with indicator bit indicating values, Geng, Kwon and Thaler do not explicitly disclose wherein generating the target code block comprises obtaining N code blocks according to the first data frame, wherein N is an integer greater than 1, wherein the N code blocks comprise the target code block and N segments that comprise one or more of the first segment, an nth segment, or an Nth segment, wherein n is an integer greater than 1 and less than N.
Leung is directed to providing method and apparatus for encoding and decoding data. More specifically, Leung teaches wherein generating the target code block comprises obtaining N code blocks according to the first data frame ([Para. 0051], in step 410, through an XGMII, the sender transmits the information data as an Ethernet packet from the reconciliation sublayer to a 64-bit information generating module. When the size of the data in the module reaches 64 bits, 64-bit information data is generated. [Para. 0052], when the data is transmitted from the XGMII to the 64-bit information module, the 64-bit information module divides the received data into K blocks, each block containing 64 bits. Afterward, each block is scrambled. The scrambled information data is shown in FIG. 5, where the information blocks are expressed as Si(i=0,1, . . . K)), wherein N is an integer greater than 1 ([Para. 0052], the 64-bit information module divides the received data into K blocks, each block containing 64 bits…where the information blocks are expressed as Si(i=0,1, . . . K) [Examiner’s Note: K may be greater than 1]), wherein the N code blocks comprise the target code block and N segments that comprise one or more of the first segment, an nth segment, or an Nth segment ([Para. 0052], the 64-bit information module divides the received data into K blocks, each block containing 64 bits…where the information blocks are expressed as Si(i=0,1, . . . K)), wherein n is an integer greater than 1 and less than N ([Para. 0052], the 64-bit information module divides the received data into K blocks, each block containing 64 bits…where the information blocks are expressed as Si(i=0,1, . . . K)).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, Kwon and Thaler, so that Ethernet data packet is segmented into code blocks, as taught by Leung. The modification would have allowed the system to improve the encoding gain of the FEC encoding without increasing transmission overhead (Leung [Para. 0013]).
For claim 7, Geng, Kwon and Thaler teach the method of claim 1. The references further teach wherein the indicator field comprises two bits (Geng [Para. 0193], If the data/control header is 1, the transmitted 64-bit information includes control information. Kwon [Page 319, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. Kwon [Page 319, b) Additional header for segmentation], Segment_Sequence_Number –This field is incremented by one with each additional segment belonging to the segmented input packet. Kwon [Page 319, b) Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Thaler, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
The references further teach wherein the indicator field comprises two bits (Thaler [Para. 0059], The frame 150 is composed of the 2-bit sync field 151 followed by the 64-bit payload field 152. The sync field 151 accommodates the 2-bit master transition. Thaler [Para. 0139], the scrambled master transition is always 10 or 01, and never 11 or 00 [Examiner’s Note: 00 and 11 are available for indication bit]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Kwon, so that the sync field has two bits and two bit patterns in the field are not used, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
Leung is directed to providing method and apparatus for encoding and decoding data. More specifically, Leung teaches wherein the indicator field comprises two bits ([Para. 0050], of the two bits in the sync header, one is a major bit for synchronizing blocks and indicating the type of the information data in the information block, and the other is a minor bit. [Para. 0053], if the major bit is “0”, it indicates that the information data in the information blocks Si is pure data. The minor bit in the sync header is a negation of the major bit [Examiner’s Note: A synchronization bit patten is overloaded with the type information of a code block. When the first code block is the first segment and takes the synchronization bit pattern, the other three bit patterns of the two synchronization bits may provide the other three values of the indicator bit for the rest code blocks]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, Kwon and Thaler, so that synchronization bits are overloaded with the type information of a code block, as taught by Leung. The modification would have allowed the system to improve the encoding gain of the FEC encoding without increasing transmission overhead (Leung [Para. 0013]).
For claim 15, Geng, Kwon and Thaler teach the line coding apparatus of claim 14. The references further teach wherein the processor ([Para. 0096- 0101], a1: Perform line coding for the input data ... [Para. 0231], the foregoing embodiments and application instances may be implemented by hardware instructed by a program) is further configured to cause the line coding apparatus to obtain N code blocks according to the first data frame (Geng [0122], a data decoding apparatus is provided to perform the data decoding. Geng [Para. 0096 - 0101], a1: Perform line coding for the input data … to generate an information block...and the information block includes information data and a 1-bit first synchronization header... Kwon [Page 317, left column, first paragraph in section II. ATSC LINK-LAYER PROTOCOL], ALP takes as input network layer packets such as IP and MPEG-2 TS as input packets), wherein the indicator bit comprises the first value when the payload comprises the first segment (Kwon [Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to‘0x0’), wherein the indicator bit comprises the second value when the payload comprises the nth segment (Kwon [Page 319, left column, b) Additional header for segmentation], Segment_Sequence_Number –For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. This field is incremented by one with each additional segment belonging to the segmented input packet [Examiner’s Note: The additional segment is the nth segment]), and wherein the indicator bit comprises the third value when the payload comprises the Nth segment (Kwon [Page 319, b) left column, Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet. A value of ‘0’, indicates that it is not last).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng and Thaler, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
Although teaching generating and sending a code block with indicator bit indicating values, Geng, Kwon and Thaler do not explicitly disclose wherein the processor is further configured to cause the line coding apparatus to obtain N code blocks according to the first data frame, wherein N is an integer greater than 1, wherein the N code blocks comprise the target code block and N segments that comprise one or more of the first segment, an nth segment, or an Nth segment, wherein n is an integer greater than 1 and less than N.
Leung is directed to providing method and apparatus for encoding and decoding data. More specifically, Leung teaches wherein the processor is further configured to cause the line coding apparatus to obtain N code blocks according to the first data frame ([Para. 0051], in step 410, through an XGMII, the sender transmits the information data as an Ethernet packet from the reconciliation sublayer to a 64-bit information generating module. When the size of the data in the module reaches 64 bits, 64-bit information data is generated. [Para. 0052], when the data is transmitted from the XGMII to the 64-bit information module, the 64-bit information module divides the received data into K blocks, each block containing 64 bits. Afterward, each block is scrambled. The scrambled information data is shown in FIG. 5, where the information blocks are expressed as Si(i=0,1, . . . K)), wherein N is an integer greater than 1 ([Para. 0052], the 64-bit information module divides the received data into K blocks, each block containing 64 bits…where the information blocks are expressed as Si(i=0,1, . . . K) [Examiner’s Note: K may be greater than 1]), wherein the N code blocks comprise the target code block and N segments that comprise one or more of the first segment, an nth segment, or an Nth segment ([Para. 0052], the 64-bit information module divides the received data into K blocks, each block containing 64 bits…where the information blocks are expressed as Si(i=0,1, . . . K)), wherein n is an integer greater than 1 and less than N ([Para. 0052], the 64-bit information module divides the received data into K blocks, each block containing 64 bits…where the information blocks are expressed as Si(i=0,1, . . . K)).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng, Kwon and Thaler, so that Ethernet data packet is segmented into code blocks, as taught by Leung. The modification would have allowed the system to improve the encoding gain of the FEC encoding without increasing transmission overhead (Leung [Para. 0013]).
For claim 20, Geng, Kwon and Thaler teach the line coding apparatus of claim 14. The references further teach wherein the indicator field comprises two bits (Geng [Para. 0193], If the data/control header is 1, the transmitted 64-bit information includes control information. Kwon [Page 319, b) Additional header for segmentation], Segment_Sequence_Number – For the ALP packet which carries the first segment of an input packet, the value of this field is set to ‘0x0’. Kwon [Page 319, b) Additional header for segmentation], Segment_Sequence_Number –This field is incremented by one with each additional segment belonging to the segmented input packet. Kwon [Page 319, b) Additional header for segmentation], Last_Segment_Indicator (LSI) – This 1-bit field indicates, when set to ‘1’, that the segment in this payload is the last one of input packet).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng and Thaler, so that the indicator bit indicates the first, intermediate and last segment in a packet, as taught by Kwon. The modification would have allowed the system to achieve overhead reduction mechanisms and efficient transmission, particularly the compression of IP/UDP packet headers (Kwon [Abstract]).
The references further teach wherein the indicator field comprises two bits ([Para. 0059], The frame 150 is composed of the 2-bit sync field 151 followed by the 64-bit payload field 152. The sync field 151 accommodates the 2-bit master transition. [Para. 0139], the scrambled master transition is always 10 or 01, and never 11 or 00 [Examiner’s Note: 00 and 11 are available for other indication bit]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng and Kwon, so that the sync field has two bits and two bit patterns in the field are not used, as taught by Thaler. The modification would have provided a coder and coding with a very low overhead when implemented as a 64b/66b code (Thaler [Para. 0181]).
Leung is directed to providing method and apparatus for encoding and decoding data. More specifically, Leung teaches wherein the indicator field comprises two bits ([Para. 0050], of the two bits in the sync header, one is a major bit for synchronizing blocks and indicating the type of the information data in the information block, and the other is a minor bit. [Para. 0053], if the major bit is “0”, it indicates that the information data in the information blocks Si is pure data. The minor bit in the sync header is a negation of the major bit [Examiner’s Note: A synchronization bit patten is overloaded with the type information of a code block. When the first code block is the first segment and takes the synchronization bit pattern, the other three bit patterns of the two synchronization bits may provide the other three values of the indicator bit for the rest code blocks]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng, Kwon and Thaler, so that synchronization bits are overloaded with the type information of a code block, as taught by Leung. The modification would have allowed the system to improve the encoding gain of the FEC encoding without increasing transmission overhead (Leung [Para. 0013]).
Claims 5, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Geng et al. (US20100223535A1, hereinafter Geng) in view of Kwon et al. (IEEE Transactions on Broadcasting, Vol. 62, No. 1, March 2016, hereinafter Kwon) and Thaler (US20060268997A1, hereinafter Thaler), and further in view of Mei et al. (US20200067827A1, hereinafter Mei).
For claim 5. Geng, Kwon and Thaler teach the method of claim 1. Although teaching generating and sending a code block with indicator bit indicating values, the references do not explicitly disclose wherein the control information comprises at least one of block identification information, transmission acknowledgment information, intermittent test information, sleep information, or link retraining information.
Mei is directed to providing link group configuration method and device. More specifically, Mei teaches wherein the control information comprises at least one of block identification information, transmission acknowledgment information ([Para. 0143], the acknowledgement information returned by the receive end device may be transmitted using a reserved field in an OH code block. For example, a two-bit reserved field after the OH reserved field that carries the first configuration information in Embodiment 1 may be used for transmitting the acknowledgement information. [Para. 0065] and [FIG. 4], one FlexE OH frame includes eight contiguous FlexE OH code blocks. For the first code block in a FlexE frame, a “00x4b” or “0x5” field is used as a mark field to identify the code block as an OH code block [Examiner’s Note: Acknowledgement is control information. FlexE OH code block in FIG. 4 is 64b/66b coding]), intermittent test information, sleep information, or link retraining information.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, Kwon and Thaler, so that acknowledgement is included in the code block, as taught by Mei. The modification would have improved availability and robustness of a link in a transport network (Mei [Para. 0006]).
For claim 12, Geng, Kwon and Thaler teach the parsing method of claim 8. Although teaching generating and sending a code block with indicator bit indicating values, the references do not explicitly disclose wherein the control information comprises at least one of block identification information, transmission acknowledgment information, intermittent test information, sleep information, or link retraining information.
Mei is directed to providing link group configuration method and device. More specifically, Mei teaches wherein the control information comprises at least one of block identification information, transmission acknowledgment information ([Para. 0143], the acknowledgement information returned by the receive end device may be transmitted using a reserved field in an OH code block. For example, a two-bit reserved field after the OH reserved field that carries the first configuration information in Embodiment 1 may be used for transmitting the acknowledgement information. [Para. 0065] and [FIG. 4], one FlexE OH frame includes eight contiguous FlexE OH code blocks. For the first code block in a FlexE frame, a “00x4b” or “0x5” field is used as a mark field to identify the code block as an OH code block [Examiner’s Note: Acknowledgement is control information. FlexE OH code block in FIG. 4 is 64b/66b coding]), intermittent test information, sleep information, or link retraining information.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, Kwon and Thaler, so that acknowledgement is included in the code block, as taught by Mei. The modification would have improved availability and robustness of a link in a transport network (Mei [Para. 0006]).
For claim 18, Geng, Kwon and Thaler teach the line coding apparatus of claim 14. Although teaching generating and sending a code block with indicator bit indicating values, the references do not explicitly disclose wherein the control information comprises at least one of block identification information, transmission acknowledgment information, intermittent test information, sleep information, or link retraining information.
Mei is directed to providing link group configuration method and device. More specifically, Mei teaches wherein the control information comprises at least one of block identification information, transmission acknowledgment information ([Para. 0143], the acknowledgement information returned by the receive end device may be transmitted using a reserved field in an OH code block. For example, a two-bit reserved field after the OH reserved field that carries the first configuration information in Embodiment 1 may be used for transmitting the acknowledgement information. [Para. 0065] and [FIG. 4], one FlexE OH frame includes eight contiguous FlexE OH code blocks. For the first code block in a FlexE frame, a “00x4b” or “0x5” field is used as a mark field to identify the code block as an OH code block [Examiner’s Note: Acknowledgement is control information. FlexE OH code block in FIG. 4 is 64b/66b coding]), intermittent test information, sleep information, or link retraining information.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng, Kwon and Thaler, so that acknowledgement is included in the code block, as taught by Mei. The modification would have improved availability and robustness of a link in a transport network (Mei [Para. 0006]).
Claims 6, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Geng et al. (US20100223535A1, hereinafter Geng) in view of Kwon et al. (IEEE Transactions on Broadcasting, Vol. 62, No. 1, March 2016, hereinafter Kwon) and Thaler (US20060268997A1, hereinafter Thaler), and further in view of Jiang et al. (US20090190595A1, hereinafter Jiang).
For claim 6, Geng, Kwon and Thaler teach the method of claim 1. Although teaching generating and sending a code block with indicator bit indicating values, the references do not explicitly disclose wherein the payload further comprises a cyclic redundancy check (CRC) field for check protection when the payload carries the control information.
Jiang is directed to providing method, system and device for transmitting overhead information. More specifically, Jiang teaches wherein the payload further comprises a cyclic redundancy check (CRC) field for check protection when the payload carries the control information ([Para. 0105], in the overhead coding block, integrity processing is performed for the contents in the coding block through an integrity algorithm. The integrity algorithm may be a 16-bit Cyclic Parity Check (CRC16) algorithm. The contents processed through the integrity algorithm may be the whole 66-bit code block or the 64-bit data subsequent to the synchronization code. [Para. 0106] and [Table 3 between page 6 and 7], Table 3 shows the coding rules in this embodiment. The synchronization code of the overhead code block is “10”. The overhead information and other optional information occupy 48 bits, and the remaining 16 bits are calculated out according to the CRC16 algorithm [Examiner’s Note: The rows in Table 3 with synchronization code 10 and C bytes are code blocks with control information. C denotes the byte of control information and D data information. Payload includes all bits after synchronization code]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, Kwon and Thaler, so that a code block includes CRC field for integrity protection when payload carries control information, as taught by Jiang. The modification would have improved the transmission performance of OAM information on the physical layer (Jiang [Para. 0008]).
For claim 13, Geng, Kwon, and Thaler teach the parsing method of claim 8. Although teaching generating and sending a code block with indicator bit indicating values, the references do not explicitly disclose wherein the payload further comprises a cyclic redundancy check (CRC) field for check protection when the payload carries the control information.
Jiang is directed to providing method, system and device for transmitting overhead information. More specifically, Jiang teaches wherein the payload further comprises a cyclic redundancy check (CRC) field for check protection when the payload carries the control information ([Para. 0105], in the overhead coding block, integrity processing is performed for the contents in the coding block through an integrity algorithm. The integrity algorithm may be a 16-bit Cyclic Parity Check (CRC16) algorithm. The contents processed through the integrity algorithm may be the whole 66-bit code block or the 64-bit data subsequent to the synchronization code. [Para. 0106] and [Table 3 between page 6 and 7], Table 3 shows the coding rules in this embodiment. The synchronization code of the overhead code block is “10”. The overhead information and other optional information occupy 48 bits, and the remaining 16 bits are calculated out according to the CRC16 algorithm [Examiner’s Note: The rows in Table 3 with synchronization code 10 and C bytes are code blocks with control information. C denotes the byte of control information and D data information. Payload includes all bits after synchronization code]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Geng, Kwon and Thaler, so that a code block includes CRC field for integrity protection when payload carries control information, as taught by Jiang. The modification would have improved the transmission performance of OAM information on the physical layer (Jiang [Para. 0008]).
For claim 19, Geng, Kwon and Thaler teach the line coding apparatus of claim 14. Although teaching generating and sending a code block with indicator bit indicating values, the references do not explicitly disclose wherein the payload further comprises a cyclic redundancy check (CRC) field for check protection when the payload carries the control information.
Jiang is directed to providing method, system and device for transmitting overhead information. More specifically, Jiang teaches wherein the payload further comprises a cyclic redundancy check (CRC) field for check protection when the payload carries the control information ([Para. 0105], in the overhead coding block, integrity processing is performed for the contents in the coding block through an integrity algorithm. The integrity algorithm may be a 16-bit Cyclic Parity Check (CRC16) algorithm. The contents processed through the integrity algorithm may be the whole 66-bit code block or the 64-bit data subsequent to the synchronization code. [Para. 0106] and [Table 3 between page 6 and 7], Table 3 shows the coding rules in this embodiment. The synchronization code of the overhead code block is “10”. The overhead information and other optional information occupy 48 bits, and the remaining 16 bits are calculated out according to the CRC16 algorithm [Examiner’s Note: The rows in Table 3 with synchronization code 10 and C bytes are code blocks with control information. C denotes the byte of control information and D data information. Payload includes all bits after synchronization code]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Geng, Kwon and Thaler, so that a code block includes CRC field for integrity protection when payload carries control information, as taught by Jiang. The modification would have improved the transmission performance of OAM information on the physical layer (Jiang [Para. 0008]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2417
/REBECCA E SONG/Supervisory Patent Examiner, Art Unit 2417