CTNF 18/187,001 CTNF 91895 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim s 1-3, 5-8, 10-11, 14 and 16 are rejected under 35 U.S.C. 102 as being anticipated by Gonzalez et al. (US 2014/0248742 A1) . PNG media_image1.png 345 634 media_image1.png Greyscale Fig. 1A of Gonzalez reproduced for ease of reference. Regarding claim 1 , Gonzalez (i.e., Fig. 1A, §0017-§0022) discloses an electronic assembly (100), comprising: a first die (106), comprising a first transmission line (152/153); a second die (104), comprising a second transmission line (151/152), wherein each of the first die (106) and the second die (104) includes a first face (112/114 bottom and top faces of 106 and 108/110 bottom and top faces of 104) and an opposing second face, the first face (108) of the second die (104) is coupled to the second face (114) of the first die (106) through boding insulator layers 130 and 132 , and each of the first transmission line (150/151) and the second transmission line (152/153) has a first end and an opposing second end, left and right ends or right and left ends respectively, see Fig. 1A above ; a first conductive pathway (162) between the first end (left end) of the first transmission line (152) and a first connection point (118) at the first face (112) of the first die (106); a second conductive pathway (162) between the first end (right end) of the second transmission line (153) and a second connection point (118) at the first face (112) of the first die (106); and a third conductive pathway (164) between the second end (right end) of the first transmission line (152) and the second end (left end) of the second transmission line (153). Claim 2 depends on claim 1 and further recites structural limitations directed to the embedding or stacking of the first die and the second die within a common substrate. Gonzalez explicitly discloses a multi-chip package (100) comprising a coreless substrate (102) into which both the first die (104) and the second die (106) are vertically embedded (paragraphs 0017-0022; FIG. 1A). The substrate (102) fully encapsulates and surrounds the embedded dies within insulating layers (130, 132, 134). The active surface (108) of the first die (104) and the active surface (112) of the second die (106) are embedded in the same substrate structure, physically separated by intervening routing and insulating layers. The first face of the second die (104, i.e., active surface 108) is coupled to the second face of the first die (106, i.e., back surface 114) through bonding insulator layers (130 and 132). Claim 3 depends on claim 1 or 2 and further recites that the first transmission line and the second transmission line are formed within respective routing layers of the substrate. Gonzalez explicitly discloses a first routing layer (150) comprising a plurality of conductive traces (151/152) formed on the first insulating layer (130), and a second routing layer (152) comprising conductive traces (152/153) formed on the third insulating layer (134) (FIG. 1A; paragraphs 0038-0040). The transmission lines of the first and second dies are implemented as these routed conductive traces within the parallel routing layers of the build-up substrate. Conductive vias (160, 162, 164) interconnect these routing layers to the electrical contacts of the respective dies. Gonzalez therefore anticipates each limitation of claim 3. Claim 5 depends on preceding claims and further recites that electrical contacts of the first die and electrical contacts of the second die are each coupled to respective conductive vias formed in insulating layers of the substrate. Gonzalez expressly discloses this limitation. A plurality of conductive vias (160) formed in the first insulating layer (130) electrically connect conductive traces of the first routing layer (150) to electrical contacts (116) of the first die (104) (paragraph 0038; FIG. 1A). Similarly, a plurality of conductive vias (162) are formed in the third insulating layer (134) to electrically connect traces of the second routing layer (152) to electrical contacts (118) of the second die (106) (paragraph 0039; FIG. 1A). Gonzalez further discloses large-diameter conductive vias (164) through multiple insulating layers that electrically couple the two routing layers to each other (paragraph 0040; FIG. 1A). Accordingly, every limitation of claim 5 is explicitly disclosed in Gonzalez. Claim 6 depends on preceding claims and further specifies that the first die has a larger footprint than the second die, and that at least a portion of the footprint of the second die lies within the footprint of the first die. Gonzalez explicitly discloses this arrangement. In FIG. 1A and paragraph 0032 of Gonzalez: 'first die 104 has a larger footprint than second die 106. Second die 106 is embedded within substrate 102 and is positioned between first die 104 and land side 122.' Gonzalez further states: 'at least a portion of footprint 107 of second die 106 lies within the footprint 105 of first die 104' and in the preferred embodiment, 'the entire footprint 107 of second die 106 lies within the footprint 105 of first die 104.' The limitation of claim 6 is explicitly anticipated by Gonzalez. Claim 7 depends on preceding claims and further recites that the first die comprises a memory device and the second die comprises a logic device (e.g., a microprocessor or digital signal processor). Gonzalez explicitly discloses this configuration. In paragraph 0032, Gonzalez states: 'in an embodiment of the present invention, first die 104 is a memory device, such as but not limited to a static random-access memory (SRAM), a dynamic access memory (DRAM), a nonvolatile memory (NVM) and second die 106 is a logic device, such as but not limited to a microprocessor and a digital signal processor.' This disclosure identically anticipates the functional characterization of the first and second dies as recited in claim 7. Claim 8 depends on preceding claims and further recites that the substrate includes a routing layer disposed between the first die and the second die. Gonzalez explicitly discloses this configuration. In paragraph 0051, Gonzalez states: 'substrate 102 includes at least one routing layer 150 that is located between first die 104 and second die 106.' In FIG. 1A, first routing layer (150) is clearly shown interposed between first die (104) and second die (106) in the vertical stacking dimension. This routing layer enables direct electrical connections between the two dies through the conductive vias (164). Claim 8 is therefore anticipated by Gonzalez. Claim 10 depends on preceding claims and further recites that the electronic assembly includes a plurality of external conductive contacts (e.g., solder balls or bumps) formed on the substrate for providing external electrical connections. Gonzalez explicitly discloses this limitation. FIG. 1A shows external conductive contacts (140), described as conductive bumps arranged in a ball grid array (BGA), formed on the land side (122) of the substrate (102) (paragraph 0054). Gonzalez further teaches: 'the external conductive contacts 140, however, need not necessarily take the form of balls and may have other shapes or structures, such as but not limited to post, bumps, lands and pins.' Accordingly, claim 10 is fully anticipated by Gonzalez. Claim 11 depends on preceding claims and further recites that the substrate includes at least one conductive trace that has a portion located between the respective footprints of the first die and the second die, and a portion that extends outside the footprint of the second die. Gonzalez specifically describes this arrangement at paragraph 0051: 'substrate 102 includes at least one conductive trace, such as conductive trace 151 that has a portion located between the footprint 105 of first die 104 and footprint 107 of second die 106 and a portion which extends outside footprint 107 of second die 106.' This is an express, verbatim disclosure of the limitation recited in claim 11. Gonzalez unambiguously anticipates claim 11. Claim 14 depends on preceding claims and further recites that the substrate is a coreless substrate. Gonzalez explicitly discloses this limitation. In paragraph 0050, Gonzalez teaches: 'in embodiments of the present invention, substrate 102 maybe a coreless substrate because it is formed on a carrier by a buildup layer process where the carrier is eventually removed from the substrate 102. Still further substrate 102 may be considered a coreless substrate because it does not include a thick core such as a fiber reinforced glass epoxy resin.' This clear and unambiguous disclosure that the substrate is coreless anticipates the limitation of claim 14. Claim 16 depends on preceding claims and further recites that the first die and the second die are each formed from a semiconductor material such as silicon (Si), silicon germanium (SiGe), germanium (Ge), or a III-V compound semiconductor such as gallium arsenide (GaAs) or indium antimonide (InSb). Gonzalez explicitly discloses this limitation at paragraph 0030: 'First die and second die may be formed from any well-known semiconductor material, such as but not limited to silicon (Si), silicon germanium (SiGe), germanium (Ge) as well as any III-V semiconductor, such as gallium arsenide (GaAs) and indium antimonide (InSb).' This is a verbatim anticipation of the semiconductor material limitation of claim 16. Claim 16 is anticipated by Gonzalez . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Knight et al. (US 2005/0002448 A1) . Regarding claim 1 , Knight (i.e., Fig. 4, §0017-§0022) discloses an electronic assembly (Fig. 4), comprising: a first die (10, the substrate 10 might be a die fabricated of GaAs, §0147), comprising a first transmission line (33); a second die (11, §0145), comprising a second transmission line (53), wherein each of the first die (10) and the second die (11) includes a first face (bottom) and an opposing second face (and top faces), the first face (bottom face) of the second die (10) is coupled to the second face (top face) of the first die (11) through capacitive coupling of 14, 15 via dielectric 17, and conductive contact pads 52 and 44 illustratively receive power, ground and a plurality of I/O signals between dies 10 and 11. Conductive connection is achieved by affixing die 11 to die 10 such that conductive connection means 41, 42 and 43 touch their respective contacts 44 and 52 . While each of the first transmission line (53) and the second transmission line (33) has a first end and an opposing second end, left and right ends or right and left ends respectively, see Fig. 4 above ; [AltContent: textbox (CP)] [AltContent: ] [AltContent: ] [AltContent: textbox (CP)] [AltContent: ] [AltContent: textbox (CP)] [AltContent: ] [AltContent: textbox (CP)] [AltContent: textbox (44)] [AltContent: textbox (44)] [AltContent: textbox (44)] [AltContent: textbox (41)] [AltContent: textbox (42)] [AltContent: textbox (43)] PNG media_image2.png 450 750 media_image2.png Greyscale Fig. 4 of Knight reproduced for ease of reference. a first conductive pathway (CP) between the first end (left end) of the first transmission line (33) and a first connection point (15) at the first face (bottom) of the first die (10); Knight, doesn’t show a direct connection of a second conductive pathway (CP) between the first end (left end) of the second transmission line (53) and a second connection point (CP) at the first face (bottom) of the first die (10), however, Knight shows a second conductive pathway (CP) between the first end (left end) of the second transmission line (53) and a second connection point (CP) on the second face (top) of the second die (11) through capacitive coupling connects to the first connection point (CP) at the first face (bottom) of the first die (10). Such a capacitive coupling of second connection point at the second face of the second die to the first connection point at the first face of the first die can be equivalently considered as a connectivity to a second connection point at the first face of the first die because there will exist capacitive coupling between two consecutive connection points at the first face of the first die because of their proximity to each other. Hence it would have been considered by a person of ordinary skill in the art as equivalent to the claimed limitation. Knight finally teaches as per claim 1, a third conductive pathway (41) between the second end (right end) of the first transmission line (33) and the second end (right end) of the second transmission line (53) . 07-21-aia AIA Claim 4, 9, 15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gonzalez in view of Knight . Claim 4 depends on preceding claims and further recites a capacitive or non-conductive coupling between the dies as the manner of signal transmission between the conductive pathways. Gonzalez discloses the general electronic assembly structure with stacked dies and interconnecting conductive pathways, as discussed above. However, Gonzalez relies primarily on direct conductive vias for signal communication between dies. Knight teaches the concept of non-conductive (capacitive) interconnection between integrated circuit dies (paragraphs 0010-0020). Specifically, Knight discloses coupled half-capacitors (14, 15) formed on facing surfaces of adjacent dies/substrates, and transmission lines (33, 53) on each module that couple capacitively through a dielectric (17) disposed at the interface (FIG. 4; paragraphs 0017-0022). Knight explicitly teaches that 'at least some of the signals between two dies... communicate via capacitive coupling' in place of or in addition to conductive coupling. It would have been obvious to a person of ordinary skill in the art to combine the multi-die stacking structure of Gonzalez with the capacitive coupling technique of Knight to achieve non-conductive inter-die signaling. The motivation for doing so is expressly provided by Knight: capacitive coupling eliminates the need for conductive contacts between dies, reduces series inductance, reduces parasitic inductance, and allows reversible assembly - advantages well recognized in the art. A skilled artisan would have found it straightforward to incorporate Knight's capacitive coupling pads into Gonzalez's vertically stacked die structure, yielding all limitations recited in claim 4. Claim 9 depends on preceding claims and further recites a dielectric material disposed between the first die and the second die to facilitate capacitive or non-conductive signal coupling therebetween. Gonzalez discloses the stacked die package with insulating layers (130, 132, 134) between the dies (FIG. 1A; paragraphs 0038-0040). These insulating layers (e.g., ABF - Ajinomoto Build-Up Film) serve as dielectric layers separating the stacked dies and provide electrical insulation between them. Knight additionally teaches that a dielectric (17) is 'preferably used to partly or totally fill the gap between half-capacitors 14 and 15,' and that this dielectric increases the capacitance, provides passivation, enhances thermal conductivity, and mechanically bonds the structure (paragraphs 0047-0048). Knight further discloses various dielectric materials suitable for use between stacked dies, including high-dielectric factor materials such as TiO2 and barium titanate ceramics. It would have been obvious to a person of ordinary skill in the art to include a high-dielectric material at the inter-die interface of Gonzalez's stacked structure, as taught by Knight, to enable or enhance capacitive coupling between the dies and improve mechanical bonding. There would have been a clear motivation to combine these teachings to achieve improved signal coupling performance between the vertically stacked dies. Claim 9 is therefore unpatentable. Claim 15 depends on preceding claims and further recites a conductive power/ground contact on at least one of the dies for providing DC power to the electronic devices of the die, separate from the capacitive signal coupling pathways. Gonzalez discloses that both dies (104 and 106) have electrical contacts (116 and 118 respectively) that are connected through the substrate interconnection structure to enable power and signal distribution (FIG. 1A; FIG. 1B; paragraphs 0034-0036). Gonzalez specifically teaches electrical connections (184) that electrically connect both the first die and the second die to an external conductive contact for delivery of power/ground signals such as VCC and VSS. Knight separately and in detail teaches the use of conductive contacts (52, 44) on the dies for receiving power and ground signals: 'Conductive contact pads 45, 46 and 47 illustratively receive power, ground and a plurality of I/O signals from substrate 10' (paragraphs 0017-0022; FIG. 3 and FIG. 4). Knight further describes the use of metallic fuzz button contacts specifically for power and ground leads as distinct from the capacitive signal coupling. Knight expressly motivates this design: 'it is advantageous to employ the relatively coarse technology of conductive contacts only for DC power leads, while retaining the invention's advantages of many high bandwidth capacitively coupled paths for signaling.' Claim 15 is therefore unpatentable over the combined teachings of Gonzalez and Knight. Claim 19 depends on preceding claims and further recites that the electronic assembly also includes a third die embedded in the substrate, the third die being coupled to at least one of the first die or the second die through the substrate interconnection structure. Gonzalez explicitly discloses multi-die configurations with three or more embedded dies. In paragraph 0100, Gonzalez teaches: 'the substrate may include three or more embedded die, if desired. For example, in an embodiment of the present invention, a multi-chip package 450 having a substrate 460 with three embedded die may be formed by embedding a third die 470 in an additional embedding insulating layer 480 formed above first insulating layer 130 as illustrated in FIG. 4.' Gonzalez further discloses that electrical connections may be formed between third die 470 and second die 106, or third die 470 and first die 104, or to both, through the substrate interconnection structure. Further, Knight discloses modular systems comprising multiple dies: 'a first die 11 and a second die 61' share a common substrate (FIG. 4), and Knight's leapfrog geometry (FIG. 9) extends these teachings to multiple stacked and capacitively coupled dies in a single system. The combination of Gonzalez's three-die embedded package teaching with Knight's multi-die coupling approach yields exactly what claim 19 recites and would have been obvious to one of ordinary skill in the art. Claim 19 is therefore unpatentable. Claim 20 depends on preceding claims and further recites that the electronic assembly is configured as part of a computer system comprising at least a processor, a memory device, and a memory controller communicatively coupled together, wherein the electronic assembly constitutes a component of that computer system. Gonzalez explicitly discloses the integration of the multi-chip package into a computer system. FIG. 3 of Gonzalez shows 'a computer system according to an embodiment of the invention,' comprising a processor (310), a memory device (320), a memory controller (330), a graphics controller (340), an input/output (I/O) controller (350), and other components communicatively coupled through a bus (360) (paragraph 0106). Gonzalez specifically teaches that 'one or more of the components shown in system 300 may be included in/and or may include one or more integrated circuit packages, such as the package structure 100 of FIG. 1A' (paragraph 0107), where package structure 100 is precisely the multi-chip package with embedded dies described as being anticipatory of claim 1. Knight similarly discloses its modular multi-die system as applicable to computer systems and digital processing environments (paragraphs 0145-0155). Both references are directed to improving inter-die communication performance and packaging density in computing systems. It would have been obvious to a person of ordinary skill in the art to employ the claimed electronic assembly as a component in the type of computer system explicitly described by Gonzalez and Knight, as such systems represent the intended and natural application of the disclosed multi-chip package technology. Claim 20 is therefore unpatentable . 07-21-aia AIA Claim s 12, 13, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Knight in view of Gonzalez . Claim 12 depends on preceding claims and further recites that the first conductive pathway and the second conductive pathway each comprise a conductive via passing through an insulating layer, connecting transmission line ends to capacitive connection points at the faces of the dies. Knight discloses that a transmission line (33) on a first die/substrate (10) has its first end connected via a conductive pathway (connection point 15) to a half-capacitor plate at the interface between the dies (FIG. 4; paragraphs 0017-0022). The conductive pathways between the transmission lines and the capacitive coupling regions define the claimed conductive pathways. Gonzalez independently teaches that conductive vias (160, 162, 164) passing through insulating layers (130, 132, 134) connect the transmission line routing layers to electrical contacts on the faces of the dies (paragraphs 0038-0041; FIG. 1A). The via diameters range from 30-50 micrometers for small vias (162) to 100-150 micrometers for large inter-layer vias (164). It would have been obvious to a person of ordinary skill in the art to implement the conductive pathways of Knight's capacitive coupling system using Gonzalez's laser-drilled and electroplated conductive via technology. This would be a routine design choice achievable by artisans familiar with both multi-chip packaging and capacitive inter-die coupling. The combination yields the claimed via-based conductive pathways recited in claim 12 and claim 12 is therefore unpatentable. Claim 13 depends on preceding claims and further recites that the third conductive pathway (connecting the second end of the first transmission line to the second end of the second transmission line) includes a conductive via having a larger diameter than the vias associated with the first and second conductive pathways. Knight teaches the third conductive pathway (41) directly connecting the second ends of the respective transmission lines (33 and 53) between the two dies (FIG. 4; paragraph 0150). This pathway must traverse the full inter-die interface, extending through the dielectric region between the dies. Gonzalez teaches that larger-diameter vias (164), having a diameter of between 100-150 micrometers, are used for conductive pathways that extend through multiple insulating layers (i.e., deeper interfaces), while smaller-diameter vias (162), having a diameter of between 30-50 micrometers, are used for shorter pathways to die contacts (paragraph 0040; FIG. 1A). Gonzalez specifically explains that the larger diameter is used to maintain a manufacturable aspect ratio given the greater depth of penetration. It would have been obvious to a person of ordinary skill in the art to size the third conductive pathway of Knight's arrangement with a larger diameter - following the direct teaching of Gonzalez - because this third pathway spans the full inter-die gap and thus requires a larger diameter via to maintain reliable filling and an acceptable aspect ratio. This is a predictable design choice fully motivated by the combined teachings. Claim 13 is therefore unpatentable. Claim 17 depends on preceding claims and further recites that a transmitter circuit is implemented on one of the dies adjacent to the first transmission line, and a receiver circuit is implemented on the other die adjacent to the second transmission line, the transmitter and receiver circuits enabling non-conductive signal coupling therebetween. Knight expressly discloses this configuration. FIG. 4 of Knight shows that a terminated transmission line (33) interconnects half-capacitors (15) on the substrate with half-capacitors on another die, providing a signal path between die 11 and die 61 (paragraph 0107). Knight discloses dedicated transmitter circuits (300, 300a) and receiver circuits (301, 301a) implemented on the dies 'preferably directly beneath half- capacitors 15a-15aa and 15b-15bb, respectively' (paragraphs 0145-0152; Figs 30-37). These transmitter and receiver circuits operate in conjunction with on-die transmission lines to send and receive signals across the capacitive interface. Gonzalez provides the complementary stacked-die structural framework showing how two dies are packaged vertically with routing layers and vias forming signal paths conducive to integration with Knight's transmitter/receiver approach. It would have been obvious to implement the transmitter and receiver circuits of Knight within Gonzalez's stacked die package, placing each circuit beneath its respective transmission line and capacitive coupling plate. This combination is expressly motivated by the performance advantages described in Knight for non-conductive inter-die coupling. Claim 17 is therefore unpatentable. Claim 18 depends on preceding claims and further recites differential signal coupling means, wherein the electronic assembly comprises a pair of first transmission lines and a corresponding pair of second transmission lines arranged to carry differential signals between the first die and the second die. Knight extensively discloses differential signaling and its application in non-conductive inter-die coupling. FIG. 35 of Knight depicts a block diagram of a preferred, differential off-die signal path (paragraph 0145). Knight teaches a differential transmitter (300a) coupled to die half-capacitors (15a and 15aa) via differential wiring (32a and 32aa), and a differential receiver (301a) coupled from half-capacitors (15b and 15bb) via wiring (32b and 32bb) (paragraphs 0145-0152). Knight expressly states: 'differential binary signaling offers significant advantages in terms of noise immunity' and describes the differential transmitter and receiver circuits in detail (paragraphs 0161-0165; FIG. 37). Gonzalez discloses a package architecture capable of carrying multiple independent signal paths through the plurality of conductive vias (160, 162) and routing layer traces, providing the structural basis for differential signal routing. It would have been obvious to a person of ordinary skill in the art to implement differential signal coupling in the stacked-die package of Gonzalez by adopting Knight's differential transmitter/receiver architecture and pairing the transmission lines accordingly. Differential signaling is a well-established technique that its incorporation into a multi-chip package using capacitive coupling would be a predictable and routine design choice expressly motivated by Knight. Claim 18 is therefore unpatentable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843. 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