DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed on 07/10/2026 have been fully considered but they are not persuasive.
Applicant’s arguments concerning claim 1 is unpersuasive. Regarding the mapping discrepancies argued by the applicant against Fig. 1A of Gonzalez are clarified in this office action in detail.
Specifically, as detailed in the initial rejection, Gonzalez discloses an electronic assembly (100) comprising first and second dies (106, 104) having respective top and bottom faces, wherein the active surface of the second die is coupled to the back surface of the first die through bonding insulator layers (130, 132). Furthermore, Gonzalez explicitly illustrates first and second transmission lines (150, 152) having opposed left and right ends, along with first, second, and third conductive pathways (comprising 151, 153, 162, 164) interconnecting these transmission lines and connection points (118, 116) at the die faces (see FIG. 1A; paragraphs 0017–0022 of Gonzalez). Because every structural limitation recited in amended Claim 1 is identically disclosed within the four corners of Gonzalez, the anticipation rejection under 35 U.S.C. § 102 is proper and is hereby maintained.
Applicant’s amendments to dependent Claims 5 and 6 add limitations regarding conductive vias positioned within specific dies and direct bonding interfaces. Gonzalez expressly teaches the use of a plurality of conductive vias (160, 162) formed in insulating layers to electrically connect routing traces to the electrical contacts of the respective dies, as well as specific footprint relationships where the first die has a larger footprint than the second die, with at least a portion of the second die's footprint lying within the first die's footprint (paragraphs 0032, 0038–0040 of Gonzalez). To the extent applicant argues specific positional arrangements of vias or interfaces, such configurations represent routine optimization and design choices within the skill of an ordinary artisan when implementing Gonzalez's embedded multi-chip architecture.
Regarding the remaining claims rejected under 35 U.S.C. § 103 (including claims directed to capacitive coupling, dielectric materials, power/ground contacts, and system integration), applicant's traversal is unconvincing. Gonzalez provides the foundational multi-chip embedded package architecture, while Knight et al. explicitly teach the advantages of non-conductive capacitive inter-die signaling (such as eliminating inter-die conductive contact needs, reducing series/parasitic inductance, and providing thermal and mechanical benefits).
A person of ordinary skill in the art at the time of the invention would have been motivated to combine Gonzalez's structural stacking framework with Knight's capacitive coupling and transceiver circuits to optimize high-frequency signal transmission and mitigate parasitic penalties. This combination involves combining known prior art elements according to known methods to yield predictable results, failing to establish patentable non-obviousness. Accordingly, the rejections under 35 U.S.C. § 103 over Gonzalez in view of Knight are maintained.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 8-9, 14-16 and 18-20 are rejected under 35 U.S.C. 102 as being anticipated by Gonzalez et al. (US 2014/0248742 A1).
Regarding claim 1, Gonzalez (i.e., Fig. 1A, §0017-§0022) discloses an electronic assembly (100), comprising:
a first die (bottom die 106 of the two dies 104 and 106 in Fig. 1A of Gonzalez), comprising a first transmission line (152);
a second die (top die 104 of the two dies 104 and 106 in Fig. 1A of Gonzalez), comprising a second transmission line (150),
wherein each of the first die (106) and -the second die (104) includes a first face (112 and 108, respectively, bottom face of each die is considered first face while the top face being opposite to the bottom is considered as a second face) and an opposing second face (114 and 110, respectively) the first face (108) of the second die (104) is coupled to the second face (114) of the first die (106, albeit through bonding insulator layers (130 and 132), and each of the first transmission line (152) and the second transmission line (150) has a first end (left end) and an opposing second end (right end);
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Fig. 1A of Gonzales annotated by the examiner show the second conductive path of the claim limitation mapped by the examiner.
a first conductive pathway (162) between the first end (left end) of the first transmission line (152) and a first connection point (right most electrical contacts 118 of the three electrical contacts 118 at the bottom face of the first die 106) at the first face (112) of the first die (106);
a second conductive pathway (starting at the left most of the three electrical contacts 116 to conductive via 160 to conductive traces 151 of first routing layer 150 to the left conductive via 164- to conductive traces 153 of second routing layer 152 to the leftmost of conductive via 162 to the left most electrical contact 118 of the three electrical contacts at the bottom face of the first die 104) between the first end (the left end of the second transmission line 150 attached to right most of the three electrical contacts 116 at the bottom face 108 of the second die 104 is internally connected to the left most electrical contacts 116 at the bottom face 108 of the second die 104, “A plurality of conductive vias 160 are in first insulating layer 130 and electrically connect conductive traces of the first routing layer 150 to electrical contacts 116 of first die 104”, §0021) of the second transmission line (150) and a second connection point (left most electrical contacts 118 of the three electrical contacts 118 at the bottom face of the first die 106) at the first face (112) of the first die (106); and
a third conductive pathway (164 on the right had side of Fig. 1A of Gonzalez above) between the second end (right end) of the first transmission line (152) and the second end (right end) of the second transmission line (150).
Regarding claim 3, Gonzalez also teaches that the first conductive pathway includes a conductive via between the first end of the first transmission line and the first connection point at the first face of the first die (Gonzalez discloses a plurality of conductive vias 162 in third insulating layer 134 between conductive traces of second routing layer 152 and electrical contacts 118 of second die 106 to electrically connect traces of second routing layer 152 to electrical contacts on second die 118, §0022).
Regarding claim 8, Gonzalez discloses that the dies are embedded in insulating layers such as Ajinomoto Build-Up Film (ABF) rather than using solder joints at the die-to-die interface §0021, §0036.
Regarding claim 9, Gonzalez further teaches that the second transmission line (150) is vertically aligned with the first transmission line (152, see Fig. 1A of Gonzalez).
Regarding claim 14, Gonzalez discloses a multi-chip package 100 having a substrate 102 with a plurality of vertically arranged die embedded therein, including first die 104 and second die 106 coupled by routing layers 150 and 152 serving as signal transmission branches. The first branch starting at the right most of the three electrical contacts 116 to conductive via 160 to conductive traces 150 to the right conductive via 164- to conductive traces 152 to the rightmost of conductive via 162 to the right most electrical contact 118 of the three electrical contacts at the bottom face of the first die 104 and the second branch is the second conductive pathway (as mapped in claim 1, see Fig. 1A of Gonzalez). These branches which can be considered as a three-dimensional power combiner (i.e. interpreted as connecting signals between the dies and to the external circuits), comprising a first branch in a first die (albeit partly) of the plurality of dies, and further comprising a second branch in a second die (albeit partly) of the plurality of dies as claimed (§0017-§0022).
Regarding claim 15, Gonzalez teaches a direct bonding interface between the first die and the second die in terms of the second conductive pathway (left most 116 to via 160 to conductive trace 151 to via 164 to conductive trace 153 to via 162 to electrical contact 118 at the bottom face of the first die 104, see Fig. 1A of Gonzalez).
Regarding claim 16, Gonzalez discloses routing traces 150, 152 and conductive vias 160, 162, 164 providing multi-level interconnections between the vertically arranged first die 104 and second die 106, terminating in external conductive contacts 140 §0019-§0022. Wherein each of the first branch and the second branch includes a first end and a second end, the electronic assembly further includes a direct bonding interconnect that connects the first end of the first branch with the first end of the second branch (“A plurality of conductive vias 160 are in first insulating layer 130 and electrically connect conductive traces of the first routing layer 150 to electrical contacts 116 of first die 104”, §0021) and the second end of the first branch is connected to a first terminal (rightmost 140) of the electronic assembly (100), the second end of the second branch is connected to a second terminal of the electronic assembly (second from the leftmost 140, see Fig. 1 A of Gonzalez).
Regarding claim 18, Gonzalez also teaches that the first branch (rightmost 116 to 160 to 150 to the right 164- to 152 to rightmost 162 to rightmost 118) includes a first transmission line (150) parallel to an interface (top and bottom surfaces of the insulator layer 132) between the first die (106) and the second die (104), and
the second branch (leftmost 116 to 160 to 151 to the right 164- to 153 to leftmost 162 to leftmost 118) includes a second transmission line (151) parallel to the interface.
Regarding claims 19 and 20, Gonzalez teaches a system (a computer system 300 includes a processor 310, a memory device 320, a memory controller 330, a graphics controller 340, an input and output (I/0) controller 350, a display 352 (teaches on claim 20), a keyboard 354, a pointing device 356, and a peripheral device 358, all of which may be communicatively coupled to each other through a bus 360, Fig. 3, §0055) comprising:
a circuit board (foundation substrate 170 is a motherboard where an integrated circuit package, such as the package structure 100 of FIG. 1A is used in a component shown in system 300, §0056); and
an electronic assembly (100), communicatively coupled to the circuit board (170), wherein the electronic assembly (100) includes a face of a first die (106) direct bonded (through insulating layers 130 and 132) to a face of a second die (104), and a power combiner (i.e. interpreted as connecting signals between the dies and to the external circuits) having a first branch (rightmost 116 to 160 to 150 to the right 164- to 152 to rightmost 162 to rightmost 118) in (albeit partially) the first die (106) and a second branch (leftmost 116 to 160 to 151 to the right 164- to 153 to leftmost 162 to leftmost 118) in (albeit partially) the second die (104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Gonzalez.
Regarding claim 2, Gonzalez teaches all limitations of claim 1 and Gonzalez further discloses that the second die 106 or first die 104 can be a thin die, such as a die having been thinned to a thickness of between $50-150$ microns (§0044). Although Gonzalez doesn’t teach exactly that the first die has a thickness below about 40 microns as claimed, the Gonzalez lower dimension represent routine optimization of dimensional parameters known in the art within the claimed range (of 40 microns).
Regarding claim 7, Gonzalez teaches all limitations of claim 1 and Gonzalez further discloses that the insulation layers 130 and 132 disposed between the first die 104 and second die 106 (§0021), however, is not explicit about a distance between the first die and the second die is below about 10 microns. However, it would have been obvious to a person of ordinary skill in the art of restricting the spacing layer thicknesses correspond to conventional thin-film packaging dimensions of few microns to a few 10s of microns.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Gonzalez in view of Knight (US 2005/0002448 A1).
Regarding claim 4, Gonzalez teaches all limitations of claim 1 and Gonzalez further recites a capacitive or non-conductive coupling between the dies as the manner of signal transmission between the conductive pathways.
Gonzalez discloses the general electronic assembly structure with stacked dies and interconnecting conductive pathways, as discussed above. However, Gonzalez relies primarily on direct conductive vias for signal communication between dies.
Knight teaches the concept of non-conductive (capacitive) interconnection between integrated circuit dies (paragraphs 0010-0020). Specifically, Knight discloses coupled half-capacitors (14, 15) formed on facing surfaces of adjacent dies/substrates, and transmission lines (33, 53) on each module that couple capacitively through a dielectric (17) disposed at the interface (FIG. 4; paragraphs 0017-0022). Knight explicitly teaches that 'at least some of the signals between two dies... communicate via capacitive coupling' in place of or in addition to conductive coupling.
It would have been obvious to a person of ordinary skill in the art to combine the multi-die stacking structure of Gonzalez with the capacitive coupling technique of Knight to achieve non-conductive inter-die signaling. The motivation for doing so is expressly provided by Knight: capacitive coupling eliminates the need for conductive contacts between dies, reduces series inductance, reduces parasitic inductance, and allows reversible assembly - advantages well recognized in the art. A skilled artisan would have found it straightforward to incorporate Knight's capacitive coupling pads into Gonzalez's vertically stacked die structure, yielding all limitations recited in claim 4.
Claim 5, Gonzalez in view of Knight teaches all limitations of claim 4 and Gonzalez also discloses that the second conductive pathway (left most 116 to via 160 to conductive trace 151 to via 164 to conductive trace 153 to via 162 to electrical contact 118 at the bottom face of the first die 104, see Fig. 1A of Gonzalez) further includes a conductive via (162) in the first die (106), wherein the conductive via (162) in the first die (106) is between the direct bonding interconnect (insulator layer 132) at the second face (top face 114) of the first die (106) and the second connection point (118) at the first face (top face 112) of the first die (106) (§0021-§0022).
Claim 6, The electronic assembly according to claim 5, wherein the second conductive pathway (left most 116 to via 160 to conductive trace 151 to via 164 to conductive trace 153 to via 162 to electrical contact 118 at the bottom face of the first die 104, see Fig. 1A of Gonzalez) further includes a conductive via (160) in the second die (104), wherein the conductive via (160) in the second die (104) is between the first end (left end) of the second transmission line (150) and the direct bonding interconnect (116) at the first face (bottom face 108) of the second die (104) (§0021-§0022).
Allowable Subject Matter
Claims 10-13 and 17 are objected to as being dependent upon a rejected base claims 1 and 14 respectively but would be allowable if rewritten in independent form including all the limitations of the base claim 1 and any intervening claims.
Claims 10-13 are allowable because while the closest prior art of record, Gonzalez discloses a multi-chip package with active surfaces including semiconductor devices like transistors, capacitors, and resistors (§0017) and a base substrate 170 providing electrical communication (§0029), Gonzalez fails to teach or suggest the specific structural arrangement, a base die comprising a first amplifier and a second amplifier (and a third amplifier for claim 11) coupled to the connection points at the first face of the first die in the specific configuration required by the claims 10-13. The prior art lacks any teaching, suggestion, or motivation to specifically modify the base substrate or die arrangement of Gonzalez to incorporate distinct first, second, and third amplifiers (such as specific combinations of power amplifiers and low-noise amplifiers) directly interconnected to the first face of the first die as claimed.
Claim 17 is allowable because a third terminal (third from the left 140 of the four 140 terminals shown in Fig. 1A of Gonzalez) of the electronic assembly (100), like the first and second terminals are closer to a first face (bottom face 112) of the first die (106) than to a second face (top face 114) of the first die (106) contrary to the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights