DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/22/2025 has been entered.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 6, 7, 9-11, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2015/0032913, hereafter “Kim”) in view of Wang (US 2021/0081109) and Cho et al (US 2021/0034300).
Regarding Claim 1, Kim teaches an apparatus, comprising:
a memory controller of a host device (the memory controller corresponding to host controller 1130 and Host I/F 1101 of Fig. 1, which control data reads and writes to storage device 1200, Paragraphs 0040-0041) configured to couple the host device to a memory system through a physical layer interface (PHY) (PHY corresponding to the Host I/F 1101, which couples the host device 100 with memory system 1200 of Fig. 1), the memory controller configured to perform operations including:
initializing the PHY to operate at a first speed (initially, the speed is set to “the first speed mode A,” Paragraph 0063, also see Fig. 6 where the first speed mode A is shown between time t0 and t1);
receiving PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed, from a first buffer of the memory system (“information about the efficient transfer speed is sent from the UFS device 2200 to the UFS host 2100,” Paragraph 0091 and step S130 of Fig. 12, also see the Speed Mode Table of Fig. 10, which may increase an operating speed, and the first buffer of the memory system corresponding to the speed mode table of Fig. 10, which is used to determine a speed, Paragraph 0081, further, configuration data from the Speed Mode Table is sent from the Speed Mode Table to a host at step S130 of Fig. 12, and Fig. 8 clearly shows that this data goes through MA queue (Tx) 222 before being sent to the host. The DMA queue is also a buffer in the broadest reasonable interpretation, giving buffer the plain meaning in the art of “a section of computer memory for temporarily storing information”); and
adjusting a configuration of the PHY in accordance with the PHY configuration information (step S150 of Fig. 12, and “The host controller 2130 changes the data transfer speeds of the interfaces 2101 and 2201 according to the speed change command,” Paragraph 0093) to operate at the second speed (step S160 of Fig. 12).
However, the cited prior art does not explicitly teach:
communicating with the memory system, via the PHY at the second speed, before initialization of the memory system is complete.
Wang teaches communicating with a memory system, via the PHY at a second speed, before initialization of the memory system is complete (communication begins at low speed at step S102 of Fig.11, and increases to a second higher speed at step S105 of Fig. 11, and Fig. 11 is a parameter setting/initialization process, Paragraph 0017, where “initialization” has been interpreted as the time between power-on of the memory device and the time I/O SSD commands received from the host are ready to be executed).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the second speed during initialization (as taught by Wang) in the cited prior art in order to quickly allow high-speed access to the SSD (Paragraph 0056 of Wang).
Further, the cited prior art does not explicitly teach communicating with the memory system before an fDeviceInit operation of the memory system is complete.
Cho teaches communicating with and initializing a system before an fDeviceInit operation of the memory system is complete (Paragraphs 0102-0104).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the fDeviceInit of Cho in the cited prior art in order to notify the host when initialization is complete (Paragraph 0104).
Regarding Claim 2, the cited prior art teaches the apparatus of claim 1, wherein the first buffer is located in a flash memory of the memory system (Paragraph 0044).
Regarding Claim 3, the cited prior art teaches the apparatus of claim 2, wherein the memory controller is further configured to complete initialization of the flash memory after adjusting the configuration of the PHY (shown on Fig. 11 of Wang).
Regarding Claim 6, the cited prior art teaches the apparatus of claim 1, wherein the PHY configuration information comprises a PHY patch associated with the second speed, and wherein adjusting the configuration of the PHY comprises applying the PHY patch (each patch corresponds to a speed mode of Fig. 10, which is applied at step S150 of Fig. 12).
Regarding Claim 7, the cited prior art teaches the apparatus of claim 6, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds (each patch corresponds to a speed mode of Fig. 10, and the plurality of speeds are shown).
Regarding Claim 9, Kim teaches a method, comprising:
initializing, by a memory controller of a host device (the memory controller corresponding to host controller 1130 and Host I/F 1101 of Fig. 1, which control data reads and writes to storage device 1200, Paragraphs 0040-0041), a physical interface (PHY) for connecting the host device to a memory system (PHY corresponding to the Host I/F 1101 to operate at a first speed (initially, the speed is set to “the first speed mode A,” Paragraph 0063, also see Fig. 6 where the first speed mode A is shown between time t0 and t1);
receiving PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed, from a first buffer of the memory system (“information about the efficient transfer speed is sent from the UFS device 2200 to the UFS host 2100,” Paragraph 0091 and step S130 of Fig. 12, also see the Speed Mode Table of Fig. 10, which may increase an operating speed, and the first buffer of the memory system corresponding to the speed mode table of Fig. 10, which is used to determine a speed, Paragraph 0081, further, configuration data from the Speed Mode Table is sent from the Speed Mode Table to a host at step S130 of Fig. 12, and Fig. 8 clearly shows that this data goes through MA queue (Tx) 222 before being sent to the host. The DMA queue is also a buffer in the broadest reasonable interpretation, giving buffer the plain meaning in the art of “a section of computer memory for temporarily storing information”); and
adjusting, by the memory controller, a configuration of the PHY in accordance with the PHY configuration information (step S150 of Fig. 12, and “The host controller 2130 changes the data transfer speeds of the interfaces 2101 and 2201 according to the speed change command,” Paragraph 0093) to operate at the second speed (step S160 of Fig. 12).
However, the cited prior art does not explicitly teach:
communicating with the memory system, via the PHY at the second speed, before initialization of the memory system is complete.
Wang teaches communicating with a memory system, via the PHY at a second speed, before initialization of the memory system is complete (communication begins at low speed at step S102 of Fig.11, and increases to a second higher speed at step S105 of Fig. 11, and Fig. 11 is a parameter setting/initialization process, Paragraph 0017, where “initialization” has been interpreted as the time between power-on of the memory device and the time I/O SSD commands received from the host are ready to be executed).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the second speed during initialization (as taught by Wang) in the cited prior art in order to quickly allow high-speed access to the SSD (Paragraph 0056 of Wang).
Further, the cited prior art does not explicitly teach communicating with the memory system before an fDeviceInit operation of the memory system is complete.
Cho teaches communicating with and initializing a system before an fDeviceInit operation of the memory system is complete (Paragraphs 0102-0104).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the fDeviceInit of Cho in the cited prior art in order to notify the host when initialization is complete (Paragraph 0104).
Regarding Claim 10, the cited prior art teaches the method of claim 9, wherein the first buffer is located in a flash memory of the memory system (Paragraph 0044).
Regarding Claim 11, the cited prior art teaches the method of claim 10, further comprising completing initialization of the flash memory after adjusting the configuration of the PHY (shown on Fig. 11 of Wang).
Regarding Claim 14, the cited prior art teaches the method of claim 9, wherein the PHY configuration information comprises a PHY patch associated with the second speed, and wherein adjusting the configuration of the PHY comprises applying the PHY patch (each patch corresponds to a speed mode of Fig. 10, which is applied at step S150 of Fig. 12).
Regarding Claim 15, the cited prior art teaches the method of claim 14, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds (each patch corresponds to a speed mode of Fig. 10, and the plurality of speeds are shown).
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2015/0032913) in view of Wang (US 2021/0081109), Cho et al (US 2021/0034300) and Sela et al (US 2023/0035584).
Regarding Claim 4, the cited prior art teaches the apparatus of claim 3, but does not explicitly teach wherein initializing the PHY to operate at the first speed comprises completing a link initialization stage of initialization of the host device.
Sela teaches initializing a PHY to operate at a first speed comprising completing a link initialization stage of initialization of a host device (link initialization shown as steps 502 and 504 of Fig. 5).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the link initialization stage of Sela in the cited prior art in order to establish communication between the memory and a host.
Regarding Claim 12, the cited prior art teaches the method of claim 11, but does not explicitly teach wherein initializing the PHY to operate at the first speed comprises completing a link initialization stage of initialization of the host device.
Sela teaches initializing a PHY to operate at a first speed comprising completing a link initialization stage of initialization of a host device (link initialization shown as steps 502 and 504 of Fig. 5).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the link initialization stage of Sela in the cited prior art in order to establish communication between the memory and a host.
Claims 5, 13, 17, 18, 19, 21, 22, 24-26, 28, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2015/0032913) in view of Wang (US 2021/0081109), Cho et al (US 2021/0034300), and Kim et al (US 11,782,853, hereafter “Kim ‘853”).
Regarding Claim 5, the cited prior art teaches the apparatus of claim 1, but does not explicitly teach wherein the memory controller is further configured to perform operations including: transmitting, after initializing the PHY to operate at the first speed, a request for the PHY configuration information to the memory system.
Kim ‘853 teaches transmitting, after initializing a device to operate at the first speed, a request for the configuration information to the memory system (the request corresponding to PWR_req, step S381 of Fig. 4, C10 L1-16).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the transmitting o the request (as taught in Kim ‘853) to adjust the configuration of the PHY in the cited prior art in order to allow a host to control data transfer rates.
Regarding Claim 13, the cited prior art teaches the method of claim 9, but does not explicitly teach: transmitting, after initializing the PHY to operate at the first speed, a request for the PHY configuration information to the memory system.
Kim ‘853 teaches transmitting, after initializing a device to operate at the first speed, a request for the configuration information to the memory system (the request corresponding to PWR_req, step S381 of Fig. 4, C10 L1-16).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the transmitting o the request (as taught in Kim ‘853) to adjust the configuration of the PHY in the cited prior art in order to allow a host to control data transfer rates.
Regarding Claim 17, Kim teaches an apparatus, comprising:
a memory controller (device controller 1230 Fig. 1):
coupled to a memory module (memory module/NVM 1210 of Fig. 1) through a first channel and configured to access data stored in the memory module through the first channel (first channel corresponding to the channel between the device controller 1230 and memory 1210 of Fig. 1); and coupled to a host device through a first physical interface (PHY) and configured to communicate with the host device over the first PHY (PHY corresponding to device interface 1201 of Fig. 1, shown as coupled to a host device), the memory controller configured to perform operations comprising:
after the PHY is initialized to operate at a first speed (initially, the speed is set to “the first speed mode A,” Paragraph 0063, also see Fig. 6 where the first speed mode A is shown between time t0 and t1), generating PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed, from a first buffer of the memory module (“information about the efficient transfer speed is sent from the UFS device 2200 to the UFS host 2100,” Paragraph 0091 and step S130 of Fig. 12, also see the Speed Mode Table of Fig. 10, which may increase an operating speed, and the first buffer of the memory system corresponding to the speed mode table of Fig. 10, which is used to determine a speed, Paragraph 0081, further, configuration data from the Speed Mode Table is sent from the Speed Mode Table to a host at step S130 of Fig. 12, and Fig. 8 clearly shows that this data goes through MA queue (Tx) 222 before being sent to the host. The DMA queue is also a buffer in the broadest reasonable interpretation, giving buffer the plain meaning in the art of “a section of computer memory for temporarily storing information”); and
transmitting the PHY configuration information to the host device (Paragraph 0091).
However, the cited prior art does not explicitly teach:
receiving, from the host device, after the PHY is initialized to operate at a first speed, a request for PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed.
Kim ‘853 teaches receiving, from a host device, after a device is initialized to operate at a first speed, a request for device configuration information for configuring the device to operate at a second speed, greater than the first speed (the request corresponding to PWR_req, step S381 of Fig. 4, C10 L1-16); and
transmitting the configuration information to the host device (step S382 of Fig. 4, C10 L19-23).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented receiving the request from the host (as taught in Kim ‘853) to adjust the configuration of the PHY in the cited prior art in order to allow a host to control data transfer rates.
Further, the cited prior art does not explicitly teach:
communicating with the memory system, via the PHY at the second speed, before initialization of the memory system is complete.
Wang teaches communicating with a memory system, via the PHY at a second speed, before initialization of the memory system is complete (communication begins at low speed at step S102 of Fig.11, and increases to a second higher speed at step S105 of Fig. 11, and Fig. 11 is a parameter setting/initialization process, Paragraph 0017, where “initialization” has been interpreted as the time between power-on of the memory device and the time I/O SSD commands received from the host are ready to be executed).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the second speed during initialization (as taught by Wang) in the cited prior art in order to quickly allow high-speed access to the SSD (Paragraph 0056 of Wang).
Further, the cited prior art does not explicitly teach communicating with the host before an fDeviceInit operation of the memory module is complete.
Cho teaches communicating with and initializing a system before an fDeviceInit operation of the memory module is complete (Paragraphs 0102-0104).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the fDeviceInit of Cho in the cited prior art in order to notify the host when initialization is complete (Paragraph 0104).
Regarding Claim 18, the cited prior art teaches the apparatus of claim 17, wherein the first buffer is located in a flash memory of the memory module (Paragraph 0044).
Regarding Claim 19, the cited prior art teaches the apparatus of claim 18, wherein transmitting the PHY configuration information is performed before initialization of the flash memory is complete (shown on Fig. 11 of Wang).
Regarding Claim 21, the cited prior art teaches the apparatus of claim 17, wherein the PHY configuration information comprises a PHY patch associated with the second speed (each patch corresponds to a speed mode of Fig. 10, which is applied at step S150 of Fig. 12).
Regarding Claim 22, the cited prior art teaches the apparatus of claim 21, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds (each patch corresponds to a speed mode of Fig. 10, and the plurality of speeds are shown).
Regarding Claim 24, Kim teaches a method, comprising:
sending, at a memory controller (device controller 1230 Fig. 1), after a physical interface (PHY) connecting the memory controller to the host device (host 1100 of Fig. 1) is initialized to operate at a first speed (initially, the speed is set to “the first speed mode A,” Paragraph 0063, also see Fig. 6 where the first speed mode A is shown between time t0 and t1), PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed, from a first buffer of a memory module coupled to the memory controller (“information about the efficient transfer speed [configuration information] is sent from the UFS device 2200 to the UFS host 2100,” Paragraph 0091 and step S130 of Fig. 12, also see the Speed Mode Table of Fig. 10, which may increase an operating speed, and the first buffer of the memory system corresponding to the speed mode table of Fig. 10, which is used to determine a speed, Paragraph 0081); and
transmitting, by the memory controller, the PHY configuration information to the host device (Paragraph 0091).
However, the cited prior art does not explicitly teach:
receiving, at a memory controller from a host device, after a physical interface (PHY) connecting the memory controller to the host device is initialized to operate at a first speed, a request for PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed.
Kim ‘853 teaches receiving, at a memory controller from a host device, after a memory connecting the memory controller to the host device is initialized to operate at a first speed, a request for configuration information for configuring the memory to operate at a second speed, greater than the first speed (the request corresponding to PWR_req, step S381 of Fig. 4, C10 L1-16); and
transmitting the configuration information to the host device (step S382 of Fig. 4, C10 L19-23).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented receiving the request from the host (as taught in Kim ‘853) to adjust the configuration of the PHY in the cited prior art in order to allow a host to control data transfer rates.
Further, the cited prior art does not explicitly teach:
communicating with the memory system, via the PHY at the second speed, before initialization of the memory system is complete.
Wang teaches communicating with a memory system, via the PHY at a second speed, before initialization of the memory system is complete (communication begins at low speed at step S102 of Fig.11, and increases to a second higher speed at step S105 of Fig. 11, and Fig. 11 is a parameter setting/initialization process, Paragraph 0017, where “initialization” has been interpreted as the time between power-on of the memory device and the time I/O SSD commands received from the host are ready to be executed).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the second speed during initialization (as taught by Wang) in the cited prior art in order to quickly allow high-speed access to the SSD (Paragraph 0056 of Wang).
Further, the cited prior art does not explicitly teach communicating with the host before an fDeviceInit operation of the memory module is complete.
Cho teaches communicating with and initializing a system before an fDeviceInit operation of the memory module is complete (Paragraphs 0102-0104).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the fDeviceInit of Cho in the cited prior art in order to notify the host when initialization is complete (Paragraph 0104).
Regarding Claim 25, the cited prior art teaches the method of claim 24, wherein the first buffer is located in a flash memory of the memory module (Paragraph 0044).
Regarding Claim 26, the cited prior art taches the method of claim 25, wherein transmitting the PHY configuration information is performed before initialization of the flash memory is complete (shown on Fig. 11 of Wang).
Regarding Claim 28, the cited prior art teaches the method of claim 24, wherein the PHY configuration information comprises a PHY patch associated with the second speed (each patch corresponds to a speed mode of Fig. 10, which is applied at step S150 of Fig. 12).
Regarding Claim 29, the cited prior art teaches the method of claim 28, wherein the buffer stores a plurality of PHY patches associated with a plurality of speeds (each patch corresponds to a speed mode of Fig. 10, and the plurality of speeds are shown).
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2015/0032913) in view of Wang (US 2021/0081109), Cho et al (US 2021/0034300) and Hsiang et al (US 2024/0118583).
Regarding Claim 8, the cited prior art teaches the apparatus of claim 1, but does not explicitly teach wherein the first buffer is configured as read-only.
Hsiang teaches parameters required for operation in a read-only memory (Paragraph 0050).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the read-only memory of Hsiang for the first buffer of the cited prior art so the speeds of the interfaces cannot be changed.
Regarding Claim 16, the cited prior art teaches the method of claim 9, but does not explicitly teach wherein the first buffer is configured as read-only.
Hsiang teaches parameters required for operation in a read-only memory (Paragraph 0050).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the read-only memory of Hsiang for the buffer of the cited prior art so the speeds of the interfaces cannot be changed.
Claims 20 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2015/0032913) in view of Wang (US 2021/0081109), Kim et al (US 11,782,853, hereafter “Kim ‘853”), Cho et al (US 2021/0034300) and Sela et al (US 2023/0035584).
Regarding Claim 20, the cited prior art teaches the apparatus of claim 19, but does not explicitly teach wherein the PHY is initialized to operate at the first speed during a link initialization stage of initialization of the host device.
Sela teaches initializing a PHY to operate at a first speed during a link initialization stage of initialization of the host device (link initialization shown as steps 502 and 504 of Fig. 5).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the link initialization stage of Sela in the cited prior art in order to establish communication between the memory and a host.
Regarding Claim 27, the cited prior art teaches the method of claim 26, but does not explicitly teach wherein the PHY is initialized to operate at the first speed during a link initialization stage of initialization of the host device.
Sela teaches initializing a PHY to operate at a first speed during a link initialization stage of initialization of the host device (link initialization shown as steps 502 and 504 of Fig. 5).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the link initialization stage of Sela in the cited prior art in order to establish communication between the memory and a host.
Claims 23 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2015/0032913) in view of Wang (US 2021/0081109), Kim et al (US 11,782,853, hereafter “Kim ‘853”), Cho et al (US 2021/0034300) and Hsiang et al (US 2024/0118583).
Regarding Claim 23, the cited prior art teaches the apparatus of claim 17, but does not explicitly teach wherein the first buffer is configured as read-only.
Hsiang teaches parameters required for operation in a read-only memory (Paragraph 0050).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the read-only memory of Hsiang for the first buffer of the cited prior art so the speeds of the interfaces cannot be changed.
Regarding Claim 30, the cited prior art teaches the method of claim 24, but does not explicitly teach wherein the first buffer is configured as read-only.
Hsiang teaches parameters required for operation in a read-only memory (Paragraph 0050).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the read-only memory of Hsiang for the first buffer of the cited prior art so the speeds of the interfaces cannot be changed.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Regarding the independent claims:
On pages 8-9 of the submitted remarks, applicant argues that Kim in view of Wang fails to teach or suggest “communicating with the memory system, via the PHY at the second speed, before an fDeviceInit operation of the memory system is complete.”
This argument has been considered and is persuasive. Thus, the prior rejection has been withdrawn. However, a new rejection has been made as noted above.
Applicant further argues that “Wang explicitly discloses that the NAND flash memory is initialized before performing the high speed setting.”
This argument has been considered but is not persuasive.
The examiner has given the term “initialization” the plain meaning of “put in the condition to start operation.” In the memory system of Wang, the initialization has been interpreted as the time between power-on of the memory device and the time I/O SSD commands received from the host are ready to be executed. The examiner maintains that all commands between steps S102-S105 are performed before read/write commands are received from the host, and that this is therefore an “initialization” process in the broadest reasonable interpretation, as the steps are for initializing the SSD at a high-speed in preparation for I/O from the host (see Paragraph 0056, where it is indicated that Fig. 11 is performed during startup/initialization). Though Wang does refer to starting the flash memory and resetting various settings as “initialization” (step S103 and Paragraph 0106), this is all part of the preparation/initialization process for the SSD to transmit data to and from the host at a high speed.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-30 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on (571) 272 - 5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135