Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/22/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C 102(a)(2) as being anticipated by Jovanovic (US6987675B2).
Regarding Claim 1, Jovanovic teaches a boost converter (e.g. soft-switched boost circuit 100) (fig. 1) comprising:
a boost inductor (e.g. inductor 102) (fig. 1), wherein a first terminal (e.g. left-side first terminal of inductor 102 connected to VIN 101) of the boost inductor is configured to receive a rectified voltage signal (i.e. the field of the invention by Jovanovic relates to DC/DC and AC/DC power converters and states boost converter technology is used in front ends of power supplies having power-factor correction, thus a person of ordinary skill in the art would know that Vin in figure 1 could include rectified voltage) (Col 1, [lines 5-17]);
a blocking diode (e.g. blocking diode 110) (fig.1), wherein an anode (e.g. first terminal of blocking diode 110, and the side directly coupled to the right-side second terminal of the boost inductor 102) (fig. 1) of the blocking diode is coupled to a second terminal (e.g. right-side second terminal of the boost inductor 102, main switching node between inductor 102 and 103) (fig. 1) of the boost inductor (e.g. inductor 102) (fig. 1);
a power switch (e.g. switch 103) (fig.1), wherein a first terminal (e.g. top-side terminal of switch 103) (fig. 1) of the power switch (e.g. switch 103) (fig. 1) is coupled to a cathode (e.g. bottom-side of blocking diode 110 coupled through switch 108 to bottom rail and up through diode 116 to the top-side first terminal of switch 103) (fig. 1) of the blocking diode (e.g. blocking diode 110) (fig. 1), a second terminal (e.g. bottom-side second terminal of switch 103 connected to the bottom rail) (fig. 1) of the power switch (e.g. switch 103) is coupled to a reference low voltage (e.g. bottom rail of circuit 100) (fig. 1), and the power switch operates based on a first switching signal (e.g. switching signal from controller 117) (fig. 1);
an output diode (e.g. diode 104) (fig. 1), wherein an anode (e.g. left-side terminal of diode 104 coupled to the second terminal of inductor 102) (fig. 1) of the output diode is coupled to the second terminal of the boost inductor, and a cathode (e.g. right-side terminal of the diode 104 coupled to the output of circuit 100) (fig. 1) of the output diode serves as an output terminal (e.g. the right-side cathode terminal of output diode 104 is coupled to a node coupled to the positive terminal of output voltage Vo) (fig. 1) of the boost converter;
an output capacitor (e.g. capacitor 105) (fig. 1), coupled between the cathode of the output diode (e.g. diode 104) (fig. 1) and the reference low voltage (e.g. bottom rail) (fig. 1); and
a first auxiliary path (active snubber circuit 107) (fig. 1), coupled between the second terminal of the boost inductor (e.g. inductor 102) (fig. 1) and the cathode of the output diode (e.g. diode 104) (fig. 1), and configured to be turned on when the power switch is turned off (e.g. where switch 108 is turned on while switch 103 is turned off) (fig. 3a-3c, and fig. 4a-4b), thereby delaying a discharge of the boost inductor (i.e. the explicit function of the active snubber 107 in Jovanovic, provides a “controlled rate” or delaying the discharge through diode 104 in circuit 100) (fig. 1) (Col 8, [lines 23-35]).
Regarding claim 2, Jovanovic teaches the boost converter (e.g. Jovanovic’s soft-switched boost converter 100) (fig. 1) according to claim 1, wherein the first auxiliary path (e.g. active snubber circuit 107) (fig. 1) comprises:
a first diode (e.g. diode 110) (fig. 1), wherein an anode (e.g. top-side terminal of diode 110 coupled to the right-side terminal cathode of inductor 102) of the first diode is coupled to the second terminal of the boost inductor (e.g. inductor 102) (fig. 1);
a first inductor (e.g. transformer 109) (fig. 1); and
a first switch (e.g. switch 108) (fig. 1), coupled in series to the first inductor (e.g. primary winding N1 of transformer 109) (fig. 1) between a cathode (e.g. second terminal of diode 110) (fig. 1) of the first diode (e.g. diode 110) (fig. 1) and the cathode (e.g. second terminal of diode 104) (fig. 1) of the output diode (e.g. diode 104, which is coupled to the first terminal of switch 108, through clamp circuit 115) (fig. 1), and configured to operate based on a second switching signal (e.g. signal S1 for switch 108 from controller 117) (fig. 1).
Regarding claim 3, Jovanovic teaches the boost converter (e.g. Jovanovic’s soft-switched boost converter 100) (fig. 1) according to claim 2, wherein the first switch (e.g. switch 108) (fig. 1) is turned on when the power switch (e.g. switch 103) (fig. 1) is turned off (e.g. switch 108 is turned on while switch 103 is turned off) (fig. 3a-3c, and fig. 4a-4b).
Allowable Subject Matter
Claims 4-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art of record does not fairly teach or suggest “a second auxiliary path, coupled between the first terminal of the power switch and the reference low voltage, and configured to be turned on when the power switch is turned off, thereby discharging energy stored in parasitic capacitance of the power switch.”
Claims 5-10 are indicated as allowable, as they depend on the allowable claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Chida (US5067066A) fig.3 shows a blocking diode (e.g. blocking diode D3) connected to the second terminal of a boost inductor (e.g. Li) and connected to the first terminal of a power switch (Q2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL ALEXANDER RURYCZ whose telephone number is (571) 272-6489. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Thienvu V. Tran can be reached at (571)270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GABRIEL ALEXANDER RURYCZ/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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