DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on July 27th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on July 27th, 2026 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 6-8, with respect to the rejections of claims under 35 U.S.C 102 (a)(1) and/or 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 4-10 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “wherein a boundary between the first silicon region and the second silicon region is visible in the cross- section” in lines 8-10. It is unclear to the examiner how the boundary between the first silicon region and the second region is visible. For example, it is visible to naked eye, under an optical microscope or Scanning electron microscopy.
Claims 4-10 are rejected for depending on claim 1 and having the above issue incorporating into the claims.
Claim 22 recites “wherein a boundary between the first silicon region and the second silicon region is observable” in lines 1-2. It is unclear to the examiner how the boundary between the first silicon region and the second region is observable. For example, it is observable to naked eye, under an optical microscope or Scanning electron microscopy.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7 and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duan et al. (Pub. No.: US 2005/0181587 A1), hereinafter as Duan.
Regarding claim 1, Duan discloses an integrated circuit (IC) device in Fig. 1-2 and 3A-3D comprising: a substrate (substrate 208) (see Fig. 2 and [0131]); and an elongated structure (nanowire 100/nanowire 310) over the substrate, the elongated structure extending in a first direction (direction from source to drain) parallel to the substrate (see Fig. 2), the elongated structure having a rounded shape in a cross-section perpendicular to the first direction (nanowire 100 being formed as nanowire 310) (see Fig. 3b and [0051], [0139-0142]), and the elongated structure comprising: a first silicon region (nanowire 300 can be made of silicon) (see [0138], [0188]); and a second silicon region (doped surface layer 302), the second semiconductor material silicon region surrounding the first semiconductor material silicon region in the cross-section (see Fig. 3B and [0139-0140]), wherein a boundary between the first silicon region and the second silicon region is visible in the cross- section (a boundary existing between doped surface layer 302 and nanowire 300 as shown in Fig. 3B, furthermore the boundary can be seen at doped region and undoped region by SEM).
Regarding claim 7, Duan discloses the IC device of claim 1, wherein the rounded shape of the cross-section of the elongated structure is a stadium shape (circular shape is also for stadium shape) (see Fig. 3A-3B).
Regarding claim 21, Duan discloses the IC device of claim 1, wherein the boundary between the first silicon region (nanowire 300) and the second silicon region (layer 302) (see Fig. 3B and [0139-0140]) is a grain boundary (grain boundary existing between doped and undoped silicon region of nanowire) (see [0010] of Goto et al (Pub. No.: 2011/0155236 A1) as evidence).
Regarding claim 22, Duan discloses the IC device of claim 21, wherein the boundary between the first silicon region and the second silicon region is observable as a change in grain size between the first silicon region and the second silicon region (grain boundary existing and at the gain boundary and there will be variation in grain sizes at the grain boundary which can be seen by SEM tool).
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (Pub. No.: US 2020/0098756 A1), hereinafter as Lilak.
Regarding claim 17, Lilak discloses an integrated circuit (IC) device in Fig. 1A-1B comprising: a plurality of nanoribbons (all nanowires 132b of the left stack of lower device section 108) (see Figs. 1A-1B and [0040]); a first source or drain (left S/D 120) at a first end of the plurality of nanoribbons (see Fig. 1A and [0036-0037]); a second source or drain (right S/D 120) at a second end of the plurality of nanoribbons, the second end opposite the first end (see Fig. 1A and [0036-0037]); and a gate (a gate electrode 144 of the left stack) formed around a portion of the plurality of nanoribbons, the gate between the first source or drain and the second source or drain (see Figs 1A-1B and [0037-0038]); wherein, at a cross-section through the gate and through the plurality of nanoribbons, each of the plurality of nanoribbons has a rounded shape (oval shape) that tapers towards opposite ends of the plurality of nanoribbons in the cross-section (each of all nanowires 132b of the left stack of lower device section 108 having an oval shape that tapers towards opposite ends of nanowires 132b) (see Fig. 1B and [0040]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (Pub. No.: US 2005/0181587 A1), hereinafter as Duan, as applied to claim 1 above
Regarding claim 4, Duan discloses the IC device of claim 1, but fails to disclose wherein the first silicon region comprises silicon having a grain size of at least 5 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the IC device comprises wherein the first silicon region comprises silicon having a grain size of at least 5 nanometers because it is critical dimension for keeping the grain size small enough for reducing dislocation and defects of the nanowire and maximizing carrier mobility. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 5, Duan discloses the IC device of claim 4, but fails to disclose wherein the first silicon region comprises silicon having a grain size of less than 5 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the IC device comprises wherein the first silicon region comprises silicon having a grain size of less than 5 nanometers because it is critical dimension for keeping the grain size small enough for reducing dislocation and defects of the nanowire and maximizing carrier mobility. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 6, Duan discloses the IC device of claim 1, but fails to disclose wherein the rounded shape has a height in a direction parallel to the substrate and along a central axis of the elongated structure of less than 5 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the IC device comprises wherein the rounded shape has a height in a direction parallel to the substrate and along a central axis of the elongated structure of less than 5 nanometers because it is critical dimension for keeping the nanowire small enough for reducing dislocation and defects and maximizing carrier mobility. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claim 8-10 rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (Pub. No.: US 2005/0181587 A1), hereinafter as Duan, as applied to claim 1 above, and in view of Lilak et al. (Pub. No.: US 2020/0098756 A1), hereinafter as Lilak.
Regarding claim 8, Duan discloses the IC device of claim 1, but fails to disclose wherein the rounded shape of the cross-section of the elongated structure is an oval.
Lilak discloses an integrated circuit device in Figs. 1A-1B comprising an elongated structure (an uppermost nanowire 132b of lower device section 108) extending in a first direction (horizontal direction in Fig. 1A) over a substrate (substrate 110) (see [0036-0037]), wherein the elongated structure having a rounded shape of an oval (oval shape of the uppermost nanowire 132b) in a cross-section perpendicular to the first direction (see Fig. 1B and [0039-0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the rounded shape of cross-section of the elongated structure of Duan to have the oval shape as same as the cross-section of the elongated structure of Lilak because the modified structure would improve carrier mobility and aspect ratio for the channel of the transistors for providing more liable and high performance device with low manufacturing cost.
Regarding claim 9, Duan discloses the IC device of claim 1, the integrated circuit device further comprising a second elongated structure (another nanowire 100/nanowire 310) (see Figs. 2, 3B and [0131-0132]), but fails to disclose the second elongated structure stacked below the elongated structure, the second elongated structure between the substrate and the elongated structure.
Lilak discloses the integrated circuit device comprising an elongated structure (an uppermost nanowire 132b of lower device section 108) extending in a first direction (horizontal direction in Fig. 1A) over a substrate (substrate 110) (see [0036-0037]) and a second elongated structure (middle nanowire 132b of lower device section 108) stacked below the elongated structure, the second elongated structure between the substrate and the elongated structure (see Fig. 1B and [0039-0042]), wherein the elongated structure and the second elongated structure are surrounded by a conductive material (gate electrode 144) (see Figs. 1A-1B and [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the arrangement of the second elongated structure of Duan stacking below the elongated structure as same as the integrated circuit device of Lilak because the modified structure would improve the spacing of the IC device for making more compact and smaller devices and eventually lowering manufacturing cost.
Regarding claim 10, the combination of Duan and Lilak discloses the IC device of claim 9, Duan fails to disclose wherein the elongated structure and the second elongated structure are surrounded by a conductive material, Lilak further disclose wherein the elongated structure and the second elongated structure are surrounded by a conductive material (gate electrode 144) (see Figs. 1A-1B and [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the arrangement of all elongated structures of Duan including the conductive material surrounding all the elongated structures as same as IC device of Lilak because the modified structure would improve the spacing of the IC device for making more compact and smaller devices and eventually lowering manufacturing cost.
Claims 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over GARDNER et al. (Pub. No.: US 2022/0238520 A1), hereinafter as GARDNER in view of Lilak et al. (Pub. No.: US 2020/0098756 A1), hereinafter as Lilak.
Regarding claim 11, GARDNER discloses an integrated circuit (IC) device in Fig. 17 comprising: a support structure (dielectric layer 120 and substrate 110) (see [0027]); a first plurality of elongated structures (layers 132, 134, 136 and 138 of nano stack in NMOS device 1631) over the support structure, the first plurality of elongated structures extending in a first direction (horizontal direction in Fig. 17) parallel to the support structure, the first plurality of elongated structures having a certain shape in a cross-section perpendicular to the first direction (see Fig. 17 and [0042-0043]); and a second plurality of elongated structures (layers 132, 134, 136 and 138 of nano stack in PMOS device 932) over the support structure, the second plurality of elongated structures (layers 132, 134, 136 and 138 of nano stack in PMOS device 932) extending in the first direction, the second plurality of elongated structures having a certain shape in a cross-section perpendicular to the first direction (see Fig. 17 and [0037-0038]); wherein an outer semiconductor layer of the first plurality of elongated structures (shell 1620) comprises a first semiconductor material (can be silicon) (see [0042]), and an outer semiconductor layer of the second plurality of elongated structures (shell 1220) comprises a second semiconductor material (can be silicon germanium) different from the first semiconductor material (see [0006], [0013] and [0038]).
GARDNER fails to disclose the first plurality of elongated structures and the second plurality of elongated structures having a rounded shape.
Lilak discloses an integrated circuit device in Figs. 1A-1B comprising a first plurality of elongated structure (all nanowires 132b of the left stack of lower device section 108) having a rounded shape (oval shape) in a cross-section perpendicular to a first direction (horizontal direction in Fig. 1A) extending parallel to a support structure (substrate 110) (see [0036-0037] and [0039-0042]); a second plurality of elongated structure (all nanowires 132b of the middle stack of lower device section 108) having a rounded shape (oval shape) in a cross-section perpendicular to a first direction (horizontal direction in Fig. 1A) extending parallel to the support structure (substrate 110) (see [0036-0037] and [0039-0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the shape of cross-section of first plurality of elongated structures and the second plurality of elongated structures of Duan to have the oval shape as same as the cross-section of the elongated structure of Lilak because the modified structure would improve carrier mobility and aspect ratio for the channel of the transistors for providing more liable and high performance device with low manufacturing cost.
Regarding claim 12, the combination of GARDNER and Lilak discloses the IC device of claim 11, wherein the first semiconductor material comprises silicon (shell 1620 can comprise Si), and the second material comprises germanium (shell 1220 can comprise SixGey) (see GARNDER and [0038], [0042]).
Regarding claim 13, the combination of GARDNER and Lilak discloses the IC device of claim 12, wherein the second semiconductor material further comprises silicon (shell 1220 can comprise SixGey) (see GARNDER and [0038], [0042]).
Regarding claim 15, the combination of GARDNER and Lilak discloses the IC device of claim 11, wherein each of the first plurality of elongated structure has a maximum height proximate to a midline of the first plurality of elongated structures (midline of), the midline extending through each of the first plurality of elongated structures (see Lilak and Fig. 1B).
Regarding claim 16, the combination of GARDNER and Lilak discloses the IC device of claim 15, wherein, in the cross-section, the rounded shapes of the first plurality of elongated structures taper towards ends of the first plurality of elongated (the oval shape of the all nanowires 132b of the left stack of lower device section 108 has taper shape toward each end) (see Lilak and Fig. 1B).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over GARDNER et al. (Pub. No.: US 2022/0238520 A1), hereinafter as GARDNER in view of Lilak et al. (Pub. No.: US 2020/0098756 A1), hereinafter as Lilak, as applied to claim 11 and further in view of Bao et al. (Pub. No.: US 2024/0186393 A1), hereinafter as Bao.
Regarding claim 14, the combination of GARDNER and Lilak discloses the IC device of claim 11, further comprising: a third material (gate electrode metal stack 1630) surrounding the first plurality of elongated structures (see GARDNER, Fig. 17 and [0042]); and a fourth material (gate electrode metal stack 1230) surrounding the second plurality of elongated structures, But the combination of GARDNER and Lilak fails to disclose the third material different from the fourth material.
Bao discloses an integrated circuit (IC) device in Figs. 21A, 26A-26C comprising: a support structure (substrate 202) (see [0048]); a first plurality of elongated structures (plurality of active layers 208b) over the support structure (see Fig. 21A and [0063]), the first plurality of elongated structures extending in a first direction (horizontal direction in Fig. 26B) parallel to the support structure, the first plurality of elongated structures having a rectangular shape in a cross-section perpendicular to the first direction (see Fig. 26A); and a second plurality of elongated structures (plurality of cores 702) over the support structure, the second plurality of elongated structures extending in the first direction (see Fig. 26A, 26C and [0107]); a third material (metal 2106) surrounding the first plurality of elongated structures (plurality of active layers 208b) (see Fig. 21A and [0096]); and a fourth material (metal 2506) surrounding the second plurality of elongated structures (plurality of cores 702) (see Fig. 25A and [0103]), the third material different from the fourth material (see [0096] and [0103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the third material and fourth material of GARDNER to be different material as same as the materials of the IC device of Bao because the modified structure would create different work functions for NMOS and PMOS transistors that would optimize threshold voltage and lower leakage current and further improve the device performance.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (Pub. No.: US 2020/0098756 A1), hereinafter as Lilak, as applied to claim 17 in view of GARDNER et al. (Pub. No.: US 2022/0238520 A1), hereinafter as GARDNER.
Regarding claim 18, Lilak discloses the IC device of claim 17, disclose wherein each of the plurality of nanoribbons comprises a core (material of nanowires 132b) (see Fig. 1B and [0041]), but fails to disclose wherein each of the plurality of nanoribbons comprises an outer layer.
GARDNER discloses an integrated circuit (IC) device in Fig. 17 comprising: a support structure (dielectric layer 120 and substrate 110) (see [0027]); a first plurality of nanoribbons (layers 132, 134, 136 and 138 of nano stack and shells 1620 in NMOS device 1631) over the support structure; wherein each of the plurality of nanoribbons comprises a core (each layer of layers 132, 134, 136 and 138 as a core) and an outer layer (shell 1620) surrounds the core surrounding the core (see [0006], [0013] and [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the outer layer of GARDNER into the IC device of Lilak for surrounding the core because the modified structure would provide high performance 3D nanosheet with optimum mobility.
Regarding claim 19, the combination of Lilak and GARDNER discloses the IC device of claim 18, wherein, in the cross-section, the outer layer surrounds the core (see GARDNER, Fig. 17 and [0042]).
Regarding claim 20, the combination of Lilak and GARDNER discloses the IC device of claim 19, but fails to disclose wherein the outer layer has a thickness between 1 nanometers and 3 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the IC device comprises the outer layer has a thickness between 1 nanometer and 3 nanometers because it is critical dimension for keeping the shell to be thin enough for reducing dislocation and defects on the surface and maximizing carrier mobility. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
