Prosecution Insights
Last updated: May 29, 2026
Application No. 18/188,201

DISPLAY SYSTEM, METHOD FOR CONTROLLING DISPLAY SYSTEM, AND DRIVER CIRCUIT MOUNTED IN DISPLAY SYSTEM

Non-Final OA §103
Filed
Mar 22, 2023
Priority
Mar 22, 2022 — JP 2022-045236
Examiner
DANIELSEN, NATHAN ANDREW
Art Unit
2622
Tech Center
2600 — Communications
Assignee
Wacom Co. Ltd.
OA Round
7 (Non-Final)
73%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
693 granted / 946 resolved
+11.3% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
966
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
74.1%
+34.1% vs TC avg
§102
5.2%
-34.8% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 946 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 April 2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 4, 5, 10, 11, and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 12,027,119; hereinafter Yamamoto ‘119), in view of Iwamoto et al (US 2010/0321372; hereinafter Iwamoto (first cited in the Office action mailed 07 November 2024)). • Regarding claims 1, 10, and 11, Yamamoto ‘119 discloses a display system and corresponding driver circuit and method (figure 2) comprising: a display device (figure 2) including: a plurality of column signal lines arranged in a horizontal direction (elements SL in figure 2), a plurality of first row signal lines arranged in a vertical direction (odd-numbered elements GL in figure 2), a plurality of second row signal lines arranged in the vertical direction (even-numbered elements GL in figure 2), a plurality of first image elements arranged at intersections between the first row signal lines and the column signal lines (elements 110 corresponding to odd-numbered elements GL in figure 2), and a plurality of second image elements arranged at intersections between the second row signal lines and the column signal lines (elements 110 corresponding to even-numbered elements GL in figure 2); and a driver circuit (element 20 in figure 2 and comprising elements 21 in figure 6) including: a plurality of first drive circuits, each disposed for a corresponding one of the first row signal lines and, in operation, drives two or more corresponding ones of the first image elements via the corresponding one of the first row signal lines (elements 21(i-2), 21(i), and 21(i+2) in figure 6), and a plurality of second drive circuits, each disposed for a corresponding one of the second row signal lines and, in operation, drives two or more corresponding ones of the second image elements via the corresponding one of the second row signal lines (elements 21(i-1) and 21(i+1) in figure 6); wherein a first drive circuit of the first drive circuits, in operation, via the corresponding one of the first row signal lines, supplies first electric charge to the two or more corresponding ones of the first image elements during a first period and extracts the first electric charge from the two or more corresponding ones of the first image elements during a second period different from the first period (at least GL(i) in figure 1 and col. 3, lines 35-47), wherein a second drive circuit of the second drive circuits, in operation, via the corresponding one of the second row signal lines, supplies second electric charge to the two or more corresponding ones of the second image elements during a third period, at least part of which overlaps with the second period, or extracts the second electric charge from the two or more corresponding ones of the second image elements during a fourth period, at least part of which overlaps with the first period (at least GL(i+1) in figure 1 and col. 3, lines 35-47), wherein the display device is different from the driver circuit (elements 10 and 20 in figure 2 are different from each other), wherein the first drive circuit includes an output terminal through which the first electric charge is supplied and extracted (element 211 in figure 7 and col. 15, line 39, through col. 16, line 12), and a capacitive element having one end coupled to the output terminal (element C11 in figure 7 and col. 15, line 39, through col. 16, line 12), and wherein the second drive circuit includes an output terminal through which the second electric charge is supplied and extracted (element 211 in figure 7 and col. 15, line 39, through col. 16, line 12), and a capacitive element having one end coupled to the output terminal (element C11 in figure 7 and col. 15, line 39, through col. 16, line 12). However, Yamamoto ‘119 fails to disclose the additional details of the display system. In the same field of endeavor, Iwamoto discloses where: a potential of the one end of the capacitive element of [the] first drive circuit is decreased at a beginning of the second period (note the relationship between G1 and G2 in figure 6 and ¶s 168-170), and a potential of the one end of the capacitive element of [the] second drive circuit is increased at the beginning of the second period (note the relationship between G1 and G2 in figure 6 and ¶s 168-170). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Yamamoto ‘119 according to the teachings of Iwamoto, for the purpose of realizing the stabilization of a potential of a scan signal line outside a selection period of the scan signal line (¶ 170). • Regarding claims 2, 4, 5, and 20-22 Yamamoto ‘119, in view of Iwamoto, discloses everything claimed, as applied to claim 1. Additionally, Yamamoto ‘119 discloses where: Claim 2: the display system further comprises: a first clock line that couples a first clock to each of the first drive circuits (GCK1 and GCK3 in figure 6); and a second clock line that couples a second clock to each of the second drive circuits (GCK2 and GCK4 in figure 6), each of the first drive circuits, in operation, supplies the first electric charge to or extracts the first electric charge from the two or more corresponding ones of the first image elements according to alternation of the first clock (col. 16, line 56, through col. 18, line 28), each of the second drive circuits, in operation, supplies the second electric charge to or extracts the second electric charge from the two or more corresponding ones of the second image elements according to alternation of the second clock (col. 16, line 56, through col. 18, line 28), and the first clock line and the second clock line are arranged parallel and adjacent to each other (figure 6). Claim 4: the first drive circuits and the second drive circuits are alternately connected in series (note where elements 21(i-2), 21(i), and 21(1+2) in figure 6 are alternately connected in series to elements 21(i-1) and 21(i+1)), each of the first drive circuits, in operation, retains information indicated by a signal output from a corresponding one of the second drive circuits that is connected to a preceding stage and outputs a signal including the information retained during the first period to a corresponding one of the second drive circuits that is connected to a subsequent stage (note the connections between elements 21 in figure 6), each of the second drive circuits, in operation, retains information indicated by a signal output from a corresponding one of the first drive circuits that is connected to a preceding stage and outputs a signal including the information retained during the third period to a corresponding one of the first drive circuits that is connected to a subsequent stage (note the connections between elements 21 in figure 6), each of the first drive circuits, in operation, initializes the information retained therein according to a signal output from a corresponding one of the first drive circuits that is connected to a stage immediately following or following the subsequent stage or according to a signal output from a corresponding one of the second drive circuits that is connected to a stage immediately following or following the subsequent stage (note the connections between elements 21 in figure 6), and each of the second drive circuits, in operation, initializes the information retained therein according to a signal output from a corresponding one of the first drive circuits that is connected to a stage immediately following or following the subsequent stage or according to a signal output from a corresponding one of the second drive circuits that is connected to a stage immediately following or following the subsequent stage (note the connections between elements 21 in figure 6). Claim 5: the plurality of first drive circuits are alternately connected in series (odd-numbered elements GL in figure 2), each of the first drive circuits, in operation, retains information indicated by a signal output from a corresponding one of the first drive circuits that is connected to a preceding stage and outputs a signal including the information retained during the first period to a corresponding one of the first drive circuits that is connected to a subsequent stage (note the connections between elements 21 in figure 6), the plurality of second drive circuits are alternately connected in series (odd-numbered elements GL in figure 2), and each of the second drive circuits, in operation, retains information indicated by a signal output from a corresponding one of the second drive circuits that is connected to a preceding stage and outputs a signal including the information retained during the third period to a corresponding one of the second drive circuits that is connected to a subsequent stage (note the connections between elements 21 in figure 6). Claims 20-22: the first drive circuits are different from the second drive circuits (the odd-numbered elements GL in figure 2 are different from the even-numbered elements GL in figure 2), a reset terminal of a first one of the first drive circuits is connected to an output terminal of a second one of the first drive circuits (note where GL(i) in figure 6 is connected to RG of element 21(i-2)), the first one of the first drive circuits and the second one of the first drive circuits are connected to a same clock line (elements 21(i-2) and 21(i) in figure 6 are connected to GCK1 and GCK 3), an output terminal of the first one of the first drive circuits is connected to an input terminal of one of the second drive circuits (note where GL(i-2) in figure 6 is connected to SG of element 21(i-1)), an output terminal of the one of the second drive circuits is connected to an input terminal of the second one of the first drive circuits (note where GL(i-1) in figure 6 is connected to SG of element 21(i)), and the one of the second drive circuits and the first one of the first drive circuits are connected to different clock lines (note where elements 21(i-2), 21(i), and 21(1+2) in figure 6 are connected to GCK1 and GCK3 while elements 21(i-1) and 21(i+1) are connected to GCK2 and GCK4). Claims 3, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto ‘119, in view of Iwamoto, and further in view of Izadian (US 2010/0307798). • Regarding claims 3, 12, and 14, Yamamoto ‘119, in view of Iwamoto, discloses everything claimed, as applied to claim 1. Additionally, Yamamoto ‘119 discloses where: Claim 3: the display system further comprises: a first clock line that couples a first clock to each of the first drive circuits (GCK1 and GCK3 in figure 6); and a second clock line that couples a second clock to each of the second drive circuits (GCK2 and GCK4 in figure 6), each of the first drive circuits, in operation, supplies the first electric charge to or extracts the first electric charge from the two or more corresponding ones of the first image elements according to alternation of the first clock (col. 16, line 56, through col. 18, line 28), each of the second drive circuits, in operation, supplies the second electric charge to or extracts the second electric charge from the two or more corresponding ones of the second image elements according to alternation of the second clock (col. 16, line 56, through col. 18, line 28). Claims 12 & 14: the display system further comprises: a first clock line that couples a first clock to each of the first drive circuits (GCK1 and GCK3 in figure 6); and a second clock line that couples a second clock to each of the second drive circuits (GCK2 and GCK4 in figure 6). However, Yamamoto ‘119, in view of Iwamoto, fails to disclose the additional details of the display system. In the same field of endeavor, Izadian discloses where: Claim 3: a first the combination of elements 6-X (where X represents a combination of numbers and letters, e.g. 12A in 6-12A) having the upward pointing arrows in figure 6B and ¶s 167-169); and a second the combination of elements 6-X having the downward pointing arrows in figure 6B and ¶s 167-169), the first figure 6B). Claims 12 & 14: a first the combination of elements 6-X (where X represents a combination of numbers and letters, e.g. 12A in 6-12A) having the upward pointing arrows in figure 6B and ¶s 167-169); and a second the combination of elements 6-X having the downward pointing arrows in figure 6B and ¶s 167-169), each of the first each of elements 6-X illustrated using dashed lines in figure 6B is connected to adjacent elements 6-X illustrated using shading by vias illustrated using circles), the lower layer line of the first note the relationship between the dashed and shaded elements 6-X in figure 6B), and the upper layer line of the first note the relationship between the dashed and shaded elements 6-X in figure 6B). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Yamamoto ‘119, as modified by Iwamoto, according to the teachings of Izadian, for the purpose of eliminating cross talk while allowing much higher data transfer speeds (¶ 19). Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto, in view of Iwamoto, and further in view of Yamamoto (US 2008/0150914; hereinafter Yamamoto ‘914). • Regarding claims 6-9, Yamamoto ‘119, in view of Iwamoto discloses everything claimed, as applied to claim 2. Additionally, Yamamoto ‘119 discloses where: Claim 7: the driver circuit is disposed on a side of a side surface of the display device (note the relationship between at least GCK1, GCK2, elements 21(i) and 21(i+1), GL(1), and GL(i+1) in figure 6), and the first clock line and the second clock line are arranged on a side of a side surface of the driver circuit opposite to the display device (note the relationship between at least GCK1, GCK2, elements 21(i) and 21(i+1), GL(1), and GL(i+1) in figure 6). Claim 9: the driver circuit is disposed on a side of a side surface of the display device (note the relationship between at least GCK1, GCK2, elements 21(i) and 21(i+1), GL(1), and GL(i+1) in figure 6), and the first clock line and the second clock line are arranged on a side of a side surface of the driver circuit opposite to the display device (note the relationship between at least GCK1, GCK2, elements 21(i) and 21(i+1), GL(1), and GL(i+1) in figure 6). However, Yamamoto ‘119, in view of Iwamoto, fails to disclose the details of a position detector and a touch sensor. In the same field of endeavor, Yamamoto ‘914 discloses where: Claim 6: the display system further comprises: a position indicator including a resonance circuit (element 11 in figures 1 and 2 and ¶ 26); a drive coil that, in operation, supplies power to the position indicator (element 3 in figure 1 and ¶ 26); and a position detector including an electro-magnetic resonance detection coil that, in operation, detects a position indicated by the position indicator (element 2 in figure 1 and ¶ 26). Claim 7: the driver circuit is disposed between the position detector and the drive coil and on a side of a side surface of the display device (element 1 in figure 1 is located between elements 2 and 3, in view of the preceding teachings of Yamamoto ‘119 (i.e. the relationship between the driver circuit and the display)), the position detector is disposed on a side of a display surface of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line (note the relationship between elements 1 and 2 in figure 1, in view of the preceding teachings of Yamamoto ‘119), and the drive coil is disposed on a side of a back surface of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line (note the relationship between elements 1 and 3 in figure 1, in view of the preceding teachings of Yamamoto ‘119). Claim 8: the display device further includes a touch sensor including a plurality of detection electrodes arranged in a planar form (element 5 in figure 5 and ¶ 32, where the structure of a ”capacitive touch sensor” is well known in the art). Claim 9: the driver circuit is disposed on a side of a side surface of the display device and on a side of a back surface of the touch sensor (element 1 in figure 1 is located between elements 2 and 3, in view of the preceding teachings of Yamamoto ‘119 (i.e. the relationship between the driver circuit and the display)), and the touch sensor is disposed on a side of a display surface of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line (note the relationship between elements 1 and 5 in figure 1, in view of the preceding teachings of Yamamoto ‘119). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Yamamoto ‘119, as modified by Iwamoto, according to the teachings of Yamamoto ‘914, for the purpose of providing constant stable position detection with sufficient electric current supplied to a position indicator when a detector is formed of a transparent member on the display-surface side of a display (¶ 9). Response to Arguments Applicant’s arguments with respect to claims 1, 10, and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Closing Remarks/Comments Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571) 272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN DANIELSEN/Primary Examiner, Art Unit 2622
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Prosecution Timeline

Show 14 earlier events
Jul 09, 2025
Response after Non-Final Action
Jul 15, 2025
Non-Final Rejection mailed — §103
Oct 14, 2025
Response Filed
Dec 30, 2025
Final Rejection mailed — §103
Mar 02, 2026
Response after Non-Final Action
Apr 30, 2026
Request for Continued Examination
May 05, 2026
Response after Non-Final Action
May 20, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
73%
Grant Probability
87%
With Interview (+14.0%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 946 resolved cases by this examiner. Grant probability derived from career allowance rate.

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