DETAILED ACTION
1. This action is in response to the applicant remarks filed on 6/10/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
3. Applicant’s arguments with respect to claim(s) 1, 10, and 14 have been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-2, 6-7, 9, 14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al. (US 20050231180) in view of Sakaguchi et al. (US 20190294189).
Regarding claim 1: Nagata et al. disclose a power supply circuit (i.e. figure 4) comprising:
a first transistor (i.e. M201) having a source coupled (i.e. electrically coupled) to an input voltage (Vin) node (i.e. node at Vin) and having a drain coupled (i.e. electrically coupled) to an output voltage (Vout) node (i.e. node at Vout);
a second transistor (i.e. M214) having a drain coupled (i.e. electrically coupled) to a gate of the first transistor (i.e. M201);
a third transistor (i.e. M207) having a drain coupled (i.e. electrically coupled) to a source of the second transistor (i.e. M214) and having a source coupled (i.e. electrically coupled) to a reference potential node (i.e. ground node) of the power supply circuit (i.e. figure 4),
a first amplifier (i.e. AMP1b) having a first input coupled to a reference voltage node (i.e. node at Vr) and having an output coupled to a gate of the third transistor (i.e. M207), wherein a feedback path (i.e. path from VFBb) is coupled between the Vout node (i.e. node at Vout) and a second input of the first amplifier (i.e. AMP1b); and
a second amplifier (i.e. AMP2b) having a first input coupled to a bias node (i.e. node at Vb1), having a second input coupled (i.e. electrically coupled) to the source of the second transistor (i.e. M214), and having an output coupled (i.e. electrically coupled) to a gate of the second transistor (i.e. M207),
but does not specifically disclose the second transistor being coupled in cascode with the third transistor.
Sakaguchi et al. disclose (i.e. figure 2) a voltage regulator comprising the second transistor (i.e. 24) being coupled in cascode with the third transistor (i.e. 22).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Sakaguchi et al. to provide a voltage regulator low in manufacturing cost and small in variation of the characteristics of a detection function, while having a high breakdown voltage.
Regarding claim 2: Nagata et al. disclose (i.e. figure 4) further comprising a capacitive element (i.e. C203) coupled (i.e. electrically coupled) between the source of the second transistor (i.e. M214) and the Vout node (i.e. node at Vout).
Regarding claim 6: Nagata et al. disclose (i.e. figure 4) further comprising a current source (i.e. from M209) coupled between the Vin node (i.e. node at Vin) and the drain of the second transistor (i.e. M214).
Regarding claim 7: Nagata et al. disclose (i.e. figure 4) wherein no buffer (i.e. see configuration of figure 4) is coupled between the drain of the second transistor (i.e. M214) and the gate of the first transistor (i.e. M201).
Regarding claim 9: Nagata et al. disclose (i.e. figure 4) further comprising a voltage divider (i.e. R201, R202) coupled between the Vout node (i.e. node at Vout) and the reference potential node (i.e. ground node) of the power supply circuit, wherein a tap of the voltage divider (i.e. R201, R202) is coupled to the feedback path (i.e. path from VFBb).
Regarding claim 14: Nagata et al. disclose a method of amplification, comprising:
driving a gate of a first transistor (i.e. M207) in an output stage (i.e. stage circuit included M207, M201) of an amplifier circuit (i.e. circuit of AMP1b, AMP2b) with a first amplifier (i.e. AMP1b); and
biasing a gate of a second transistor (i.e. M201) in the output stage (i.e. stage circuit included M207, M201) of the amplifier circuit (i.e. circuit of AMP1b, AMP2b) with a second amplifier (i.e. AMP2b) receiving feedback from a source of the second transistor (i.e. M201),
but does not specifically disclose the second transistor being coupled in cascode with the first transistor.
Sakaguchi et al. disclose (i.e. figure 2) a voltage regulator comprising the second transistor (i.e. 24) being coupled in cascode with the first transistor (i.e. 22).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Sakaguchi et al. to provide a voltage regulator low in manufacturing cost and small in variation of the characteristics of a detection function, while having a high breakdown voltage.
Regarding claim 19: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated).
Regarding claim 20: (i.e. figure 4) wherein the third transistor (i.e. M207) is a power transistor of a low-dropout (LDO) regulator (i.e. 201).
6. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yasusaka (US 20190302820) in view of Sakaguchi et al. (US 20190294189).
Regarding claim 10: Yasusaka discloses an amplifier circuit (i.e. figure 8) comprising:
an input stage (i.e. stage 11, M4 for Vin); and
an output stage (i.e. stage 12, M3, M2 for Vout) having an input (i.e. input of the output stage) coupled (i.e. electrically coupled) to an output of the input stage (i.e. stage 11, M4 for Vin), the output stage (i.e. stage 12, M3, M2 for Vout) comprising:
a first transistor (i.e. M2) having a gate coupled (i.e. electrically coupled) to the input (i.e. input of the output stage) of the output stage (i.e. stage 12, M3, M2 for Vout); and
an amplifier (i.e. 12) having a first input coupled to a bias node (i.e. at 16), having a second input coupled (i.e. electrically coupled) to a source of the second transistor (i.e. M3), and having an output coupled (i.e. electrically coupled) to a gate of the second transistor (i.e. M3), the amplifier being configured to effectively boost a transconductance of the second transistor (i.e. by the configuration of 12 and M3),
but does not specifically disclose a second transistor coupled in cascode with the first transistor.
Sakaguchi et al. disclose (i.e. figure 2) a voltage regulator comprising a second transistor (i.e. 24) coupled in cascode with the first transistor (i.e. 22).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Sakaguchi et al. to provide a voltage regulator low in manufacturing cost and small in variation of the characteristics of a detection function, while having a high breakdown voltage.
Regarding claim 11: (i.e. figure 8) wherein the boosted transconductance of the second transistor (i.e. M3) is based on a gain of the amplifier (i.e. provide the gain by the configuration of 12 and M3).
7. Claims 3 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al. (US 20050231180) in view of Sakaguchi et al. (US 20190294189) and further in view of Pruvost (US 20190220050).
Regarding claims 3 and 17-18: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the second amplifier has a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the second amplifier has a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the amplifier has a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the second amplifier has a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
Regarding claim 8: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
8. Claims 4-5 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al. (US 20050231180) in view of Sakaguchi et al. (US 20190294189) and further in view of Yasusaka (US 20190302820).
Regarding claims 4 and 15: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the second amplifier is configured to effectively boost a transconductance of the second transistor.
Yasusaka disclose a regulator (i.e. figure 8) comprising the second amplifier (i.e. 12) is configured (i.e. configuration of amplifier 12) to effectively boost a transconductance of the second transistor (i.e. M3).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Yasusaka to achieve stable operation in a wide load range and fast load response combined with low current consumption.
Regarding claims 5 and 16: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the boosted transconductance is based on a gain of the second amplifier.
Yasusaka disclose a regulator (i.e. figure 8) comprising the boosted transconductance is based on a gain of the second amplifier (i.e. base on the output of 12 provide to M3).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Yasusaka to achieve stable operation in a wide load range and fast load response combined with low current consumption.
9. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yasusaka (US 20190302820) in view of Sakaguchi et al. (US 20190294189) and further in view of Pruvost (US 20190220050).
Regarding claim 12: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the amplifier has a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the amplifier has a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the amplifier has a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the amplifier has a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
Regarding claim 13: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the amplifier circuit has a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the amplifier circuit has a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the amplifier circuit has a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the amplifier circuit has a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838
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