DETAILED ACTION
1. This action is in response to the RCE filed on 1/7/26.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/7/26 has been entered.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2, 6-7, 9, 14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagata et al. (US 20050231180).
Regarding claim 1: Nagata et al. disclose a power supply circuit (i.e. figure 4) comprising:
a first transistor (i.e. M201) having a source coupled (i.e. electrically coupled) to an input voltage (Vin) node (i.e. node at Vin) and having a drain coupled (i.e. electrically coupled) to an output voltage (Vout) node (i.e. node at Vout);
a second transistor (i.e. M214) having a drain coupled (i.e. electrically coupled) to a gate of the first transistor (i.e. M201);
a third transistor (i.e. M207) having a drain coupled (i.e. electrically coupled) to a source of the second transistor (i.e. M214) and having a source coupled (i.e. electrically coupled) to a reference potential node (i.e. ground node) of the power supply circuit (i.e. figure 4);
the second transistor (i.e. M214) being coupled in cascode (i.e. electrically coupled in series) with the third transistor (i.e. M207) (i.e. figure 4 shows transistor M207 is electrically coupled in series with transistor M214);
a first amplifier (i.e. AMP1b) having a first input coupled to a reference voltage node (i.e. node at Vr) and having an output coupled to a gate of the third transistor (i.e. M207), wherein a feedback path (i.e. path from VFBb) is coupled between the Vout node (i.e. node at Vout) and a second input of the first amplifier (i.e. AMP1b); and
a second amplifier (i.e. AMP2b) having a first input coupled to a bias node (i.e. node at Vb1), having a second input coupled (i.e. electrically coupled) to the source of the second transistor (i.e. M214), and having an output coupled (i.e. electrically coupled) to a gate of the second transistor (i.e. M207).
Regarding claim 2: (i.e. figure 4) further comprising a capacitive element (i.e. C203) coupled (i.e. electrically coupled) between the source of the second transistor (i.e. M214) and the Vout node (i.e. node at Vout).
Regarding claim 6: (i.e. figure 4) further comprising a current source (i.e. from M209) coupled between the Vin node (i.e. node at Vin) and the drain of the second transistor (i.e. M214).
Regarding claim 7: (i.e. figure 4) wherein no buffer (i.e. see configuration of figure 4) is coupled between the drain of the second transistor (i.e. M214) and the gate of the first transistor (i.e. M201).
Regarding claim 9: (i.e. figure 4) further comprising a voltage divider (i.e. R201, R202) coupled between the Vout node (i.e. node at Vout) and the reference potential node (i.e. ground node) of the power supply circuit, wherein a tap of the voltage divider (i.e. R201, R202) is coupled to the feedback path (i.e. path from VFBb).
Regarding claim 14: Nagata et al. disclose a method of amplification, comprising:
driving a gate of a first transistor (i.e. M207) in an output stage (i.e. stage circuit included M207, M201) of an amplifier circuit (i.e. circuit of AMP1b, AMP2b) with a first amplifier (i.e. AMP1b); and
biasing a gate of a second transistor (i.e. M201) in the output stage (i.e. stage circuit included M207, M201) of the amplifier circuit (i.e. circuit of AMP1b, AMP2b) with a second amplifier (i.e. AMP2b) receiving feedback from a source of the second transistor (i.e. M201), the second transistor (i.e. M201) being coupled in cascode (i.e. electrically coupled in series) with the first transistor (i.e. M207) (i.e. figure 4 shows transistor M207 is electrically coupled in series with transistor M201).
Regarding claim 19: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore, the previous rejections based on the apparatus will not be repeated).
Regarding claim 20: (i.e. figure 4) wherein the third transistor (i.e. M207) is a power transistor of a low-dropout (LDO) regulator (i.e. 201).
5. Claims 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yasusaka (US 20190302820).
Regarding claim 10: Yasusaka discloses an amplifier circuit (i.e. figure 8) comprising:
an input stage (i.e. stage 11, M4 for Vin); and
an output stage (i.e. stage 12, M3, M2 for Vout) having an input (i.e. input of the output stage) coupled (i.e. electrically coupled) to an output of the input stage (i.e. stage 11, M4 for Vin), the output stage (i.e. stage 12, M3, M2 for Vout) comprising:
a first transistor (i.e. M2) having a gate coupled (i.e. electrically coupled) to the input (i.e. input of the output stage) of the output stage (i.e. stage 12, M3, M2 for Vout)
a second transistor (i.e. M3) coupled in cascode (i.e. electrically coupled in series) with the first transistor (i.e. M2) (i.e. figure 4 shows transistor M3 is electrically coupled with transistor M2); and
an amplifier (i.e. 12) having a first input coupled to a bias node (i.e. at 16), having a second input coupled (i.e. electrically coupled) to a source of the second transistor (i.e. M3), and having an output coupled (i.e. electrically coupled) to a gate of the second transistor (i.e. M3), the amplifier being configured to effectively boost a transconductance of the second transistor (i.e. by the configuration of 12 and M3).
Regarding claim 11: (i.e. figure 8) wherein the boosted transconductance of the second transistor (i.e. M3) is based on a gain of the amplifier (i.e. provide the gain by the configuration of 12 and M3).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 3 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al. (US 20050231180) in view of Pruvost (US 20190220050).
Regarding claims 3 and 17-18: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the second amplifier has a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the second amplifier has a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the amplifier has a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the second amplifier has a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
Regarding claim 8: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA.
(i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the power supply circuit is a low-dropout (LDO) regulator with a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
8. Claims 4-5 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al. (US 20050231180) in view of Yasusaka (US 20190302820).
Regarding claims 4 and 15: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the second amplifier is configured to effectively boost a transconductance of the second transistor.
Yasusaka disclose a regulator (i.e. figure 8) comprising the second amplifier (i.e. 12) is configured (i.e. configuration of amplifier 12) to effectively boost a transconductance of the second transistor (i.e. M3).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Yasusaka to achieve stable operation in a wide load range and fast load response combined with low current consumption.
Regarding claims 5 and 16: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the boosted transconductance is based on a gain of the second amplifier.
Yasusaka disclose a regulator (i.e. figure 8) comprising the boosted transconductance is based on a gain of the second amplifier (i.e. base on the output of 12 provide to M3).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Yasusaka to achieve stable operation in a wide load range and fast load response combined with low current consumption.
9. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yasusaka (US 20190302820) in view of Pruvost (US 20190220050).
Regarding claim 12: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the amplifier has a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the amplifier has a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the amplifier has a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the amplifier has a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
Regarding claim 13: Nagata et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the amplifier circuit has a quiescent current less than 1 µA.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Nagata et al.’s invention to have the amplifier circuit has a quiescent current less than 1 µA in order to stability of the regulator. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
In addition, Pruvost discloses a regulator comprising the amplifier circuit has a quiescent current less than 1 µA (i.e. ¶ 35).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagata et al.’s invention with the regulator as disclose by Pruvost to have the amplifier circuit has a quiescent current less than 1 µA, because it provides the stability against a variation of supply voltage, and losses in the system.
Response to Arguments
10. Applicant's arguments filed 10/1/25 have been fully considered but they are not persuasive.
Applicant argues that “Nagata does not anticipate "a third transistor having a drain coupled to a source of the second transistor and having a source coupled to a reference potential node of the power supply circuit, the second transistor being coupled in cascode with the third transistor," as recited in claim 1. More specifically, transistor M214 is not coupled in cascode with transistor M207 of Nagata (see FIG. 4). To a person having ordinary skill in the art of electronic circuits, "coupled in cascode" is a specific circuit topology, and the Examiner cannot consider transistors M207 and M214 of Nagata as being coupled in cascode, even though such transistors are clearly electrically coupled to one another. Generally, to be coupled in cascode in an amplifier circuit, one transistor should be configured as a common-source amplifier, and the other transistor coupled thereto should be configured as a common-gate amplifier (e.g., a drain of the common-source amplifier/transistor should be coupled to a source of the common-gate amplifier/transistor). In Nagata, the drain of transistor M207 is coupled to the drain of transistor M214, which clearly means these two transistors are not coupled in cascode.”
“Thus, Nagata does not anticipate "a first transistor having a source coupled to an input voltage (Vin) node and having a drain coupled to an output voltage (Vout) node; a second transistor having a drain coupled to a gate of the first transistor; [and] a third transistor having a drain coupled to a source of the second transistor and having a source coupled to a reference potential node of the power supply circuit, the second transistor being coupled in cascode with the third transistor," as recited in independent claim 1.”
The Examiner disagrees, because the claimed limitation does not require “to be coupled in cascode in amplifier circuit”. Claim 1, merely recited “the second transistor being coupled in cascode with the third transistor. The term “coupled in cascode” is broadly interpreted as “electrically coupled in series”. Accordingly, Nagata et al.’s figure 4 shows the second transistor M214 is being electrically coupled in series with the third transistor M207 via its input and output terminals, respectively. Therefore, Nagata et al.’s figure 4 disclose the second transistor (i.e. M214) being coupled in cascode (i.e. electrically coupled in series) with the third transistor (i.e. M207).
In addition, the term “coupled” is broadly interpreted as “electrically coupled”. Thus, Nagata et al. disclsoes a first transistor (i.e. M201) having a source coupled (i.e. electrically coupled) to an input voltage (Vin) node (i.e. node at Vin) and having a drain coupled (i.e. electrically coupled) to an output voltage (Vout) node (i.e. node at Vout);
a second transistor (i.e. M214) having a drain coupled (i.e. electrically coupled) to a gate of the first transistor (i.e. M201); a third transistor (i.e. M207) having a drain coupled (i.e. electrically coupled) to a source of the second transistor (i.e. M214) and having a source coupled (i.e. electrically coupled) to a reference potential node (i.e. ground node) of the power supply circuit (i.e. figure 4); the second transistor (i.e. M214) being coupled in cascode (i.e. electrically coupled in series) with the third transistor (i.e. M207) (i.e. figure 4 shows transistor M207 is electrically coupled in series with transistor M214) as recited in claim 1.
Moreover, Applicant argues that “Nagata fails to anticipate or suggest "driving a gate of a first transistor in an output stage of an amplifier circuit with a first amplifier; and biasing a gate of a second transistor in the output stage of the amplifier circuit with a second amplifier receiving feedback from a source of the second transistor, the second transistor being coupled in cascode with the first transistor," as recited in independent claim 14 (emphasis added).
In rejecting claim 14, the Examiner relies on FIG. 4 of Nagata and maps the claimed "first transistor" to transistor M201 (pages 10-11 of the FOA) and the claimed "second transistor" to transistor M214. However, transistor M214 is not coupled in cascode with transistor M201 of Nagata (see FIG. 4). To a person having ordinary skill in the art of electronic circuits, "coupled in cascode" is a specific circuit topology, and the Examiner cannot arbitrarily state that transistors M201 and M214 of Nagata are coupled in cascode, even though such transistors may arguably be electrically coupled to one another. Generally, to be coupled in cascode in an amplifier circuit, one transistor should be configured as a common-source amplifier, and the other transistor coupled thereto should be configured as a common-gate amplifier (e.g., a drain of the common-source amplifier/transistor should be coupled to a source of the common-gate amplifier/transistor). In Nagata, the gate of transistor M201 is coupled to the drain of transistor M214, which clearly means these two transistors are not coupled in cascode.”
The Examiner disagrees, because the claimed limitation does not require “to be coupled in cascode in amplifier circuit”. Claim 14, merely recited “the second transistor being coupled in cascode with the first transistor. The term “coupled in cascode” is broadly interpreted as “electrically coupled in series”. Accordingly, Nagata et al.’s figure 4 shows the second transistor M201 is being electrically coupled in series with the first transistor M207. Therefore, Nagata et al.’s figure 4 disclose the second transistor (i.e. M201) being coupled in cascode (i.e. electrically coupled in series) with the first transistor (i.e. M207).
Furthermore, Applicant’s argues that “the source of transistor M214 of Nagata (considered by the Examiner as teaching the claimed "second transistor") is connected directly to electrical ground for the (see the "ground voltage" in FIG. 4 and para. [0064]). Error amplifier AMP2b (considered by the Examiner as teaching the claimed "second amplifier") does not receive feedback from electrical ground, but [at] an inverting input terminal of the instead receives feedback from "the output voltage Vout second error amplifier AMP2b" (para. [0066] and FIG. 4). Therefore, Nagata does not teach "a second amplifier receiving feedback from a source of the second transistor" as recited in claim 14.
Consequently, Nagata does not describe "driving a gate of a first transistor in an output stage of an amplifier circuit with a first amplifier; and biasing a gate of a second transistor in the output stage of the amplifier circuit with a second amplifier receiving feedback from a source of the second transistor, the second transistor being coupled in cascode with the first transistor," as recited in claim 14.”
Applicant’s arguments with respect to claim(s) 14 above have been considered but are moot because the new ground (see the rejection of claim 14 above).
Applicant’s arguments with respect to claim(s) 10 have been considered but are moot because the new ground (see the rejection of claim 10 above).
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nguyen Tran/Primary Examiner, Art Unit 2838