DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 8/12/2026 is acknowledged. Claims 1, 3, 12, 21 and 24 have been amended. Claims 22-23 remain withdrawn from consideration.
Response to Arguments
Applicant’s arguments with respect to claims 1-21, 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 19 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blatchford et al. (US 2013/0069081 A1).
Regarding claim 1, Blatchford teaches a row cell circuit (Fig. 8 of Blatchford), comprising:
a diffusion region (active region including 114-116 in Fig. 8 of Blatchford) on a substrate (substrate in Fig. 8), the diffusion region comprising a first diffusion region portion (116) and a second diffusion region portion (114), each disposed along a first axis (axis along the main dimension of the active region) in a first direction (left-right direction in Fig. 8), wherein:
the first diffusion region portion and the second diffusion region portion intersect along a second axis (axis of the gate 102) in a second direction (up-down direction) orthogonal to the first direction; and
a first gate (102) disposed along the second axis on the diffusion region, wherein the first gate comprises a first gate first side (right side of the gate 102) on the first diffusion region portion and a first gate second side (left side of the gate 102) on the second diffusion region portion, wherein:
the first diffusion region portion has a first width (width of the active area 116) in the second direction at the first gate first side; and
the second diffusion region portion has a second width (width of the active area 114) greater than the first width in the second direction at the first gate second side.
Regarding claim 2, Blatchford teaches all limitations of the row cell circuit of claim 1, and also teaches wherein: the first diffusion region portion comprises a first portion first side (upper side of active area 116 in Fig. 8 of Blatchford) and a first portion second side (lower side of active area 116 in Fig. 8 of Blatchford), each orthogonal to the first gate first side (as shown in Fig. 8 of Blatchford); and the second diffusion region portion comprises a second portion first side (upper side of active area 114) and a second portion second side (lower side of active area 114), each orthogonal to the first gate second side (as shown in Fig. 8 of Blatchford).
Regarding claim 3, Blatchford teaches all limitations of the row cell circuit of claim 2, and also teaches wherein the first portion second side and the second portion second side extend along a third axis (as shown in Fig. 8 of Blatchford, lower sides of active areas 114 and 116 are aligned to a single axis) in the first direction.
Regarding claim 4, Blatchford teaches all limitations of the row cell circuit of claim 2, and also teaches wherein the second diffusion region portion further comprises a second portion end (upper portion of the active area 114 that is under the gate 102 and is not in contact with active area 116) disposed along the second axis, wherein the second portion end of the second diffusion region portion is orthogonal to the first portion first side of the first diffusion region portion (as shown in Fig. 8 of Blatchford).
Regarding claim 5, Blatchford teaches all limitations of the row cell circuit of claim 4, and also teaches wherein the second portion first side is orthogonal to the second portion end (as shown in Fig. 8 of Blatchford).
Regarding claim 6, Blatchford teaches all limitations of the row cell circuit of claim 1, and also teaches wherein the first gate comprises a dummy gate (as described in [0030] of Blatchford, the gate 102 is unconnected, which means it is a dummy gate).
Regarding claim 19, Blatchford teaches all limitations of the row cell circuit of claim 1 integrated into an integrated circuit (IC) (the IC described in [0017] of Blatchford).
Regarding claim 21, Blatchford teaches a method of fabricating a row cell circuit, comprising:
forming a diffusion region (active region including 114-116 in Fig. 8 of Blatchford) on a substrate (substrate of Fig. 8), the diffusion region comprising a first diffusion region portion (116) and a second diffusion region portion (114), each disposed along a first axis (axis along the main dimension of the active region) in a first direction (left-right direction in Fig. 8), wherein forming the diffusion region on the substrate further comprises:
forming the first diffusion region portion (116) and the second diffusion region portion (114) intersecting along a second axis (axis of the gate 102) in a second direction (up-down direction in Fig. 8) orthogonal to the first direction; and
forming a first gate (102) along the second axis on the diffusion region, wherein the first gate comprises a first gate first side (right side of the gate 102) on the first diffusion region portion and a first gate second side (left side of the gate 102) on the second diffusion region portion, wherein forming the diffusion region further comprises:
forming the first diffusion region portion having a first width (width of the active area 116) in the second direction at the first gate first side; and
forming the second diffusion region portion having a second width (width of the active area 114) greater than the first width in the second direction at the first gate second side (as shown in Fig. 8 of Blatchford).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-18, 20 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Blatchford in view of Guha et al. (US 2019/0393352 A1).
Regarding claim 7, Blatchford teaches all limitations of the row cell circuit of claim 6, but does not teach further comprising a nanosheet disposed within the first gate and above the diffusion region in a vertical direction orthogonal to the first direction and the second direction.
Guha teaches a nanowire device (Fig. 5 of Guha) wherein the silicon channel region are made of nanosheets (512A/B in Fig. 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel regions of the transistors nanosheets, as disclosed by Guha, in order to increase gate-channel interface and device density.
As incorporated, the active region 114-116 of Blatchford would be formed as nanosheets and have the same width pattern as the initial regions 114-116 shown in Fig. 7 of Blatchford.
Regarding claim 8, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 7, and also teaches wherein the nanosheet comprises: a first nanosheet portion (nanosheets made corresponding to active area 116 of Blatchford) having the first width (as combined in claim 7 above); a second nanosheet portion (nanosheets made corresponding to active area 114 of Blatchford) having the second width (as combined in claim 7 above); and a right-angle corner (jog 106) between the first nanosheet portion and the second nanosheet portion.
Regarding claim 9, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 7, and also teaches wherein the nanosheet comprises a same material as the diffusion region (the nanosheets are made of silicon, as stated in [0049] of Guha).
Regarding claim 10, Blatchford teaches all limitations of the row cell circuit of claim 2, and further comprising: a second gate (100 in Fig. 8 of Blatchford) disposed along a fourth axis (axis of gate 100) in the second direction on the diffusion region adjacent to the first gate first side, wherein the second gate comprises a second gate first side (right side of gate 100) and a second gate second side (left side of gate 100); but does not teach the row cell circuit further comprising: a first nanosheet disposed between the second gate first side and the second gate second side.
Guha teaches a nanowire device (Fig. 5 of Guha) wherein the silicon channel region are made of nanosheets (512A/B in Fig. 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel regions of the transistors nanosheets, as disclosed by Guha, in order to increase gate-channel interface and device density.
As incorporated, the active regions 116 and 114 of Blatchford would be formed as nanosheets and have the same width pattern as the initial regions 116-114 shown in Fig. 8 of Blatchford.
Regarding claim 11, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 10, and also teaches wherein the nanosheet has the first width in the second direction (as combined in claim 10 and shown in Fig. 8 of Blatchford).
Regarding claim 12, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 10, and further comprising: a third gate (104 in Fig. 8 of Blatchford) disposed along a fifth axis (axis of gate 104) in the second direction on the diffusion region adjacent to the first gate second side (as shown in Fig. 8 of Blatchford), the third gate comprising:
a third gate first side (right side of gate 104);
a third gate second side (left side of gate 104); and
a second nanosheet (wider nanosheets formed to replace active area 114 as incorporated in claim 10 above) disposed between the third gate first side and the third gate second side.
Regarding claim 13, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 12, and also teaches wherein the second nanosheet has the second width in the second direction (as combined in claim 10 above).
Regarding claim 14, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 10, and also teaches wherein:
the first diffusion region portion (116 in Fig. 8 of Blatchford) extends between the first gate first side and the second gate second side; and
the first portion first side and the first portion second side are each orthogonal to the first gate first side and the second gate second side (as shown in Fig. 8 of Blatchford).
Regarding claim 15, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 10, and further comprising a first source/drain region (the S/D region of gate 100 in Fig. 8 of Blatchford) disposed between the first gate and the second gate on the first diffusion region portion, the first source/drain region electrically coupled to the first nanosheet (this is implicit feature of a transistor).
Regarding claim 16, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 12, and also teaches wherein: the second diffusion region portion (114 in Fig. 8 of Blatchford) extends between the first gate second side and the third gate first side (as defined in claim 10 above); and the second portion first side and the second portion second side are each orthogonal to the first gate second side and the third gate first side (as combined in claim 12 above).
Regarding claim 17, Blatchford in view of Guha teaches all limitations of the row cell circuit of claim 12, and further comprising a second source/drain region (as taught in claim 1 above) disposed between the first gate second side and the third gate first side on the second diffusion region portion, the second source/drain region electrically coupled to the second nanosheet (as combined in claim 12 above).
Regarding claim 18, Blatchford teaches all limitations of the row cell circuit of claim 2, but does not teach wherein the first portion first side, the first portion second side, the second portion first side, and the second portion second side comprise surfaces extending in a vertical direction orthogonal to the first direction and the second direction.
Guha teaches a nanowire device (Fig. 5 of Guha) wherein the silicon channel region are made of nanosheets (512A/B in Fig. 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel regions of the transistors nanosheets, as disclosed by Guha, in order to increase gate-channel interface and device density.
As incorporated, the active areas 116-114 of Blatchford would be formed as nanosheets and have the same width pattern as the initial regions 116-114 shown in Fig. 8 of Blatchford. The sidewalls of these nanosheets are surfaces that are orthogonal to the first and second directions.
Regarding claim 20, Blatchford teaches all limitations of the row cell circuit of claim 1, but does not teach the row cell circuit integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
Guha teaches an integrated circuits included in a smartphone, tablet, mobile phone, desktop computer, … (see [0121] of Guha).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the device of Blatchford to the integrated circuits such as smartphone, tablet, mobile phone, desktop computer… in situations where different width transistors are used in order to reduce variations in photolithographic effects and to reduce the difference in overhang of transistor gates ([0010] of Blatchford).
Regarding claim 24, Blatchford teaches an integrated circuit (IC) (circuit in Fig. 8 of Blatchford) comprising:
a circuit disposed on a substrate (substrate in Fig. 8), the circuit comprising a plurality of row cell circuits (it is implicit that there are many circuits shown in Fig. 8), each row cell circuit comprising:
a diffusion region (active region including 114-116 in Fig. 8 of Blatchford) on the substrate, the diffusion region comprising a first diffusion region portion (116) and a second diffusion region portion (114), each disposed along a first axis (axis along the main dimension of the active region) in a first direction (left-right direction in Fig. 8), wherein: the first diffusion region portion and the second diffusion region portion intersect along a second axis (axis of the gate 102) in a second direction (up-down direction) orthogonal to the first direction; and
a first gate (102) disposed along the second axis on the diffusion region, wherein the first gate comprises a first gate first side (right side of gate 102) on the first diffusion region portion and a first gate second side (left side of gate 102) on the second diffusion region portion, wherein:
the first diffusion region portion has a first width (width of the active area 116) in the second direction at the first gate first side; and
the second diffusion region portion has a second width (width of active area 114) greater than the first width in the second direction at the first gate second side (as shown in Fig. 8 of Blatchford).
But Blatchford does not teach the circuit is a logic circuit.
Guha teaches an integrated circuits included in a smartphone, tablet, mobile phone, desktop computer, … (see [0121] of Guha).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the device of Blatchford to the integrated circuits such as smartphone, tablet, mobile phone, desktop computer… in situations where different width transistors are used in order to reduce variations in photolithographic effects and to reduce the difference in overhang of transistor gates ([0010] of Blatchford).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
