ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-19 still pending.
Claims 1, 13 and 16 were amended.
Claims 20-30 were cancelled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6-7, 9, 11-12 and 15-19 have been considered but are moot because the new ground of rejection necessitated do to applicant amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Bernardon et. al. DE Publication 102004018261 (Bernardon).
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Regarding claim 1, D'Souza discloses a power supply circuit, comprising: at least one voltage supply (i.e., Vboost) (Fig. 3) selectively coupled to an output node (i.e., 131) (Fig. 3) of the power supply circuit (i.e., 300) (Fig. 3) and configured to generate at least one voltage (for example voltage provided by converters 382 and 383) (Fig. 3) using power from a power source (i.e., 150) (Fig. 3), the output node (i.e., 131) (Fig. 3) being for coupling to an active load (i.e., 110) (Fig. 3);
and a boost converter (i.e., 381) (Fig. 3) configured to generate an output voltage using power from the power source (i.e., 150) (Fig. 3), the boost converter having: an inductive (i.e., L1) (Fig. 3) element coupled to the power source (i.e., 150) (Fig. 3) and a switching node (i.e., SN) (Fig. 3); a first transistor (i.e., SW1) (Fig. 3) coupled between the switching node (i.e., SN) (Fig. 3) and a reference potential node; a second transistor (i.e., SW2) (Fig. 3)
wherein the boost converter (i.e., 381) (Fig. 3) and the at least one voltage supply (i.e., Vboost) (Fig. 3) are selectively coupled to the output node (i.e., 131) (Fig. 3) based on power draw by the active load (i.e., 110) (Fig. 3).
D'Souza fail to disclose a second transistor having a drain coupled to the switching node; and a third transistor having a source coupled to a source of the second transistor, a drain of the third transistor being coupled to the output node.
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Bernardon, in the same field of endeavor discloses a power supply circuit (see Fig. 3A), comprising: a boost converter having:
an inductive element (i.e., L) (Fig. 3A) coupled to a power source and a switching node(i.e., see reference character added SN for purpose of explanation) (Fig. 3A);
a first transistor (i.e., M3) (Fig. 3A) coupled between the switching node (i.e., SN) (Fig. 3A) and a reference potential node (i.e., GND) (Fig. 3A);
a second transistor (i.e., M1) (Fig. 3A) having a drain coupled to the switching node (i.e., M1) (Fig. 3A); and a third transistor (i.e., M2) (Fig. 3A) having a source coupled to a source of the second transistor (i.e., M1) (Fig. 3A), a drain of the third transistor (i.e., M2) (Fig. 3A) being coupled to the output node (i.e., ON) (Fig. 3A) for the purpose of limiting the current to step up or step down the input voltage.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a boost converter having a second transistor having a drain coupled to the switching node; and a third transistor having a source coupled to a source of the second transistor, a drain of the third transistor being coupled to the output node in D'Souza, as describe by Bernardon, in order to limiting the current to for boost or buck and input voltage.
Regarding claim 2, D'Souza in view of Bernardon, as applied in linking claims, discloses the claimed invention. More particularly D'Souza disclose the use of a single cell but fails to discloses wherein the at least one voltage is lower than a battery voltage of a cell in the power source. However, D'Souza, which use the cell as a power source, discloses that the converter 382 and 383 could be a buck converter or a buck-boost converter in place of the boost converter, wherein the selection of converter only depends on the output voltage requirements (for example see paragraph 30). Also, it is well known that a buck converter regulated supply voltage to be less than the input voltage (as disclosed by Bernandon).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide at least one voltage is lower than a battery voltage of a cell in the power source (for example by using a buck converter instead of a boost converter) as describe by D'Souza since it is well known that a buck converter regulated supply voltage to be less than the input voltage as taught by Bernandon in order to fulfill output voltage requirements.
Claim 3 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Bernardon et. al. DE Publication 102004018261 (Bernardon) and in further view of Long US Patent 10023054 (Long).
Regarding claim 3, D'Souza in view of Bernardon, as applied in linking claim, discloses the claimed invention but fails to disclose wherein the power source comprises a stacked multi-cell battery and wherein the at least one voltage is less than a battery voltage of a cell in the stacked multi-cell battery.
Long, in the same field of endeavor, discloses energy storage modules (or battery) 110 as power source comprising different voltage across each cell. For example, one embodiment of an energy storage module 110 has 12 battery cells each supplying a voltage of approximately 3V to 4.2V, resulting in a voltage range for the energy storage module 110 of approximately 36V to 50V (see column 2, lines 63-67 and column 3, lines 1-8). Therefore by dividing an energy storage module into stacked multi-cell battery the thermal management of the power source is improved.
Regarding at least one voltage being less than a battery voltage of a cell in the stacked multi-cell battery, D'Souza in view of Bernardon, as applied in linking claim, disclose the use of a cell as a power source. Further D'Souza discloses that the converter 382 and 383 could be a buck converter or a buck-boost converter in place of the boost converter, wherein the selection of converter only depends on the output voltage requirements (for example see paragraph 30). Also, it is well known that a buck converter regulated supply voltage to be less than the input voltage (as disclosed by Bernandon).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide the power source comprising a stacked multi-cell battery and wherein the at least one voltage is less than a battery voltage of a cell in the stacked multi-cell battery since providing an energy storage module divided into stacked multi-cell battery improves the thermal management of the power source and it is well know that using a buck converter regulated supply voltage to be less than the input voltage.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Bernardon et. al. DE Publication 102004018261 (Bernardon) in further view Cai et. al., CN Document 109375605 (Cai).
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Regarding claim 4, D'Souza in view of Bernardon, as applied in linking claim, discloses the invention but fails to disclose at least one voltage supply including a first voltage supply selectively coupled to the output node via first enable circuitry.
Cai, in the same field of endeavor discloses several voltage supplied (i.e., 1-3) (Fig. 3), each including a enable circuit (K012 -K01n) (Fig. 3). For example, Cai discloses a first voltage supply (i.e., 1) (Fig. 3) selectively coupled to the output node (i.e., see reference added ON for purpose of explanation) via first enable circuitry (i.e., K012) for the purpose of interrupting the connection between the voltage supply and the output node.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide at least one voltage supply includes a first voltage supply selectively coupled to the output node via first enable circuitry in D'Souza in view of Bernardon, as described by Cai in order to limit the connection between the voltage supply and the output node.
Regarding claim 6, D'Souza in view of Bernardon and in further view of Cai discloses the claimed invention. For example, as applied in linking claims, Cai discloses a several voltage supplied (i.e., 1-3) (Fig. 3), each including a enable circuit (K012 -K01n) (Fig. 3), including a at least one voltage supply further includes a second voltage supply (i.e., 2) (Fig. 3) selectively coupled to the output node via second enable circuitry (i.e., K01n) (Fig. 3).
Claims 7, 9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Bernardon et. al. DE Publication 102004018261 (Bernardon) and in further view of Nebrigic et. al. US Publication 20070212596 A (Nebrigic).
Regarding claim 7, D'Souza in view of Bernardon, as applied in linking claims, discloses the invention but fails to disclose a discharge circuit coupled in parallel with the inductive element.
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Nebrigic, in the same field of endeavor discloses a discharge circuit (i.e., see element 46 including see Dynamic Controller 50 and connections to boost converter 30b) (Fig. 5 and Fig. 15) coupled in parallel with the inductive element (i.e., L) (Fig. 5 and Fig. 15) in order to discharge the inductive element.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a discharge circuit coupled in parallel with the inductive element in D'Souza in view of Bernardon, as described by Nebrigic in order to discharge the inductive element.
Regarding claim 9, D'Souza in view of Bernardon and in further view of Nebrigic, as applied in linking claims, discloses the claimed invention, more particularly Nebrigic discloses the discharge circuit (i.e., 46) (Fig. 5) configured to provide a discharge path for the inductive element based on the second transistor (i.e., MR) (Fig. 5) being turned off.
Regarding claim 11, D'Souza in view of Bernardon and in further view of Nebrigic, as applied in linking claims, discloses the claimed invention, more particularly Nebrigic discloses the discharge circuit comprising a sense circuit (i.e., see element 300 coupled to the Gain amplifier 78) (Fig. 15)configured to sense a current across the inductive element (i.e., L) (Fig. 15), wherein the second transistor (i.e., MR) (Fig. 15) is configured to be turned off based on the current (i.e., If) (Fig. 15).
Regarding claim 12, D'Souza in view of Bernardon and in further view of Nebrigic, as applied in linking claims, discloses the claimed invention, more particularly Nebrigic the sense circuit (i.e., see element 300 coupled to the Gain amplifier 78) (Fig. 15) comprises a comparator (i.e., Gain Amplifier) (Fig. 15) configured to sense the current across the inductive element (i.e., L) (Fig. 15) by comparing a source voltage (i.e., Vf) (Fig. 15) and a drain voltage (i.e., Vo) (Fig. 15) of the second transistor (i.e., MR) (Fig. 15).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Bernardon et. al. DE Publication 102004018261 (Bernardon) and in further view of Prevost US Patent 9602098 (Prevost).
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Regarding claim 15, D'Souza in view of Bernardon, as applied in linking claims, discloses the claimed invention but fails to disclose a fourth transistor coupled between the reference potential node and sources of the second transistor and the third transistor.
Prevost in the same field of endeavor discloses the use of a fourth transistor (or shunt transistor) coupled between back to back transistor and a reference potential node or the reference potential node and sources of the second transistor (i.e., ShA) (Fig. 5) and the third transistor (i.e., ShB) (Fig. 5) as an alternative for a bypass circuit.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a fourth transistor coupled between the reference potential node and sources of the second transistor and the third transistor in D'Souza in view of Bernardon, as described by Prevost in order to provide an alternative for a bypass circuit.
Claim 16-17 is rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Saccomanno et al. US Publication 20230116750 (Saccomanno).
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Regarding claim 16, D'Souza discloses a power supply circuit (i.e., 300) (Fig. 3), comprising: at least one voltage supply (i.e., Vboost) (Fig. 3) configured to provide at least one voltage (see voltage supplied by converter 382 and 383) using power from a power source (i.e., 150) (Fig. 3);
and a boost converter (i.e., 381) (Fig. 3) having an input coupled to the power source (i.e., 150) (Fig. 3) and an output selectively coupled to the at least one voltage supply (i.e., see amplifier 110) (Fig. 1), the power supply circuit including an output node (i.e., 131) (Fig. 3) for coupling to an active load (for example see amplifier 110) (Fig. 1), and wherein the boost converter (i.e., 381 ) (Fig. 3) and the at least one voltage supply (i.e., Vboost) (Fig. 3) are selectively coupled to the output node (i.e., 131) (Fig. 3) based on power draw by the active load (i.e., 110) (Fig. 3).
D'Souza fail to discloses wherein the at least one voltage is lower than a battery voltage of a cell in the power source. However, D'Souza, which use the battery as a power source, discloses that the converter 382 and 383 could be a buck converter or a buck-boost converter in place of the boost converter, it will only depend on the output voltage requirements (for example see paragraph 30). It is well known that a buck converter regulated supply voltage to be less than the input voltage (for reference see Saccomanno paragraph 003).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide at least one voltage is lower than a battery voltage of a cell in the power source (for example by using a buck converter instead of a boost converter) as describe by D'Souza since it is well known that a buck converter regulated supply voltage to be less than the input voltage as taught by Saccomanno in order to fulfill output voltage requirements.
Regarding claim 17, D'Souza in view of Saccomanno, as applied in linking claim, discloses the claimed invention but fails to disclose the boost converter (i.e., 381) (Fig. 3) comprising: an inductive element (i.e., L1) (Fig. 3) coupled between the power source (i.e., 150) (Fig. 3) and a switching node (for example see added reference character SN) (Fig. 3); a first switch (i.e., SW1) (Fig. 3) coupled between the switching node (i.e., SN) (Fig. 3) and a reference potential node of the power supply circuit; and a second switch (i.e., SW2) (Fig. 3) coupled to the output of the boost converter (i.e., 381) (Fig. 3) and selectively coupled to the switching node (i.e., SN) (Fig. 3).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza et al. US Publication 20210265911 (D'Souza) in view of Saccomanno et al. US Publication 20230116750 (Saccomanno) in further view of Bernardon et. al. DE Publication 102004018261 (Bernardon).
Regarding claim 18, D'Souza in view of Saccomanno, as applied in linking claims, discloses the claimed invention. For example D'Souza discloses the use of switches as current limiting circuits but fail to disclose the boost converter further comprising a third switch coupled between the second switch and the switching node.
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Bernardon, in the same field of endeavor discloses a power supply circuit (see Fig. 3A), comprising: a boost converter comprising a third switch coupled between the second switch and the switching node and a third transistor (i.e., M2) (Fig. 3A) having a source coupled to a source of the second transistor (i.e., M1) (Fig. 3A), a drain of the third transistor (i.e., M2) (Fig. 3A) being coupled to the output node (i.e., ON) (Fig. 3A) for the purpose of step up or step down the input voltage.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a boost converter having a third switch coupled between the second switch and the switching node in D'Souza in view of Saccomanno, as describe by Bernardon, in order to boost or buck and input voltage.
Regarding claim 19, D'Souza in view of Saccomanno in further view of Bernardon, as applied in linking claims, discloses the claimed invention, More particularly Bernardon disclose wherein the second switch (i.e., M1) (Fig. 3A) and the third switch (i.e., M2) (Fig. 3A) comprising back-to-back transistors.
Allowable Subject Matter
Claims 5, 8, 10 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art as applied above fails to disclose all the elements recited in linking claims combined with a first enable circuitry including: a fourth transistor having a source coupled to the first voltage supply; a fifth transistor having a source coupled to the reference potential node; and a sixth transistor having a drain coupled to drains of the fourth transistor and the fifth transistor and a source coupled to the output node.
Regarding claim 8, the prior art as applied above fails to disclose all the elements recited in linking claims combined with the discharge circuit comprising: a fourth transistor having a drain coupled to the power source; a fifth transistor having a drain coupled to the switching node; and a sixth transistor having a drain coupled to sources of the fourth transistor and the fifth transistor, wherein a source of the sixth transistor is coupled to the reference potential node.
Regarding claim 10, the prior art as applied above fails to disclose all the elements recited in linking claims combined with the boost converter configured in a bypass mode by turning on the second transistor and the third transistor and by turning off the first transistor.
Regarding claim 13, the prior art as applied above fails to disclose all the elements recited in linking claims combined with wherein: the output node is for coupling to an active load; the at least one voltage supply is coupled to the output node and the boost converter is decoupled from the output node, based on the active load being configured to have a first output power; the boost converter is configured in a bypass mode and the at least one voltage supply is decoupled from the output node, based on the active load being configured to have a second output power greater than the first output power; and the boost converter is configured in a boost mode and the at least one voltage supply is decoupled from the output node, based on the active load being configured to have a third output power greater than the second output power.
Claims 14 is dependent of claim 13.
Conclusion
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/YAHVEH COMAS TORRES/
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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