DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claim 1 be found allowable, claim 5 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Applicant is advised that should claim 11 be found allowable, claim 13 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Applicant is advised that should claim 19 be found allowable, claim 20 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1, 4-5, 11-13, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bennett et al. (US 2021/0081330) in view of Doucette et al. (US 2023/0161500).
As per claims 1 and 11, Bennett et al. (hereinafter “Bennett”) teaches a zoned namespaces (ZNS) storage computing device comprising:
a processor (host device fig. 1, 104, [0026]); and
non-volatile memory ([0027], lines 1-2) comprising a plurality of zones including a given zone ([0049] describing multiple zones), wherein
the processor is configured to execute a zone writing program to: receive zone write commands ([0066] describing write commands to zones); and
responsive to receiving the zone write commands, execute the zone write commands on the given zone of the non-volatile memory of the storage computing device ([0068]-[0070] describe execution of the 3 commands in the table of fig. 5B) in an order specified by zone write sequence numbers ([0068] describing the write to the first block indicating that the zone is empty, [0053] describing how when a zone is empty the WP is at 0 and as described in [0068] the write pointer is incremented based on the number of blocks written; wherein the execution occurs sequentially in the zone based upon the write pointer) included in a zone descriptor for the given zone (as illustrated in fig. 5B with the table being the zone write descriptor), wherein
the zone write sequence numbers are included in the zone write commands (As illustrated in fig. 5B with each line being a command therefore the write pointer being included in the zone write commands; see [0066]).
Bennett et al. does not teach that the zone write command includes a field storing the write sequence number (in this case the “Write ID” of Bennett) such that the sequence number is embedded as reserved fields of the zone write command as issued by a host device and specifying a sequential execution order for a zone for writes to logical blocks of the zone within the non-volatile memory of the storage computing device. Doucette et al. (hereinafter Doucette) teaches a system that assigns and tags write requests with sequence numbers in a system utilizing zoned solid state drives (see figures 1-2; par. 0027-0028, 0056-0060, 0080). The sequence numbers allow the writes to be processed sequentially even when they are received out of order. The write request contains a tagged sequence number, a starting LBA of a LZone and a skip mask indicating the blocks of the LZone that are already written. The location of each of these elements in the request may be considered a reserved field.
An obvious modification can be made-utilizing the sequence number (“Write ID”) embedded in a field of the write instruction sent from the processor to the non-volatile memory of Bennett, as suggested by Doucette. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Bennett to include the Write ID (sequence number) embedded in a field of the write command sent from the processor the non-volatile memory, as taught by Doucette, because Doucette teaches that this modification would help to ensure data integrity by ensuring that older data is not overwriting newer data (see paragraphs [0027] and [0028]).
As per claim 4, Bennett teaches wherein
each of the plurality of zones has an associated zone descriptor (fig. 5B, with each line used to write data to each zone, see [0051] wherein each zone is represented using the ZSLBA); and
each zone descriptor has associated zone write sequence numbers, which record an order in which zone write commands are issued by a memory controller of a host device (As illustrated in fig. 5B with WP being updated).
As per claims 5 and 13, Doucette teaches that the sequence number is attached to the write command (figure 1-2; par. 0027-0028, 0056-0060 – writes are tagged with sequence numbers) which would constitute a “reserved field”.
As per claim 12, Bennett teaches The ZNS storage method of claim 11, further comprising:
retrieving the zone descriptor and the zone write sequence numbers for the given zone from a host device ([0064], lines 4-6 wherein the memory device which stores the table is construed to be the host as it hosts the table 550), wherein
each of the plurality of zones has an associated zone descriptor (fig. 5B, with each line used to write data to each zone, see [0051] wherein each zone is represented using the ZSLBA); and
each zone descriptor has associated zone write sequence numbers, which record an order in which zone write commands are issued by a memory controller of the host device (As illustrated in fig. 5B).
As per claim 19, Bennett teaches a zoned namespaces (ZNS) storage computing system comprising:
a storage device comprising non-volatile memory ([0027], lines 1-2) divided into a plurality of zones [0049] describing multiple zones); and
a host device comprising a memory controller (As illustrated in fig. 3 with the host device comprising the controller), wherein
the host device and the storage device store one or a plurality of zone descriptors containing information about one or more of the plurality of zones ([0064] wherein the host sends commands to the storage device and therefore allows the table of fig. 5B to be generated and stored in the storage device. Therefore the host device and the storage device in conjunction store the plurality of descriptors);
the one or the plurality of zone descriptors contain zone write sequence numbers, which record an order in which zone write commands are issued by the memory controller for a given zone of the plurality of zones ([0068] describing the write to the first block indicating that the zone is empty, [0053] describing how when a zone is empty the WP is at 0 and as described in [0068] the write pointer is incremented based on the number of blocks written; wherein the execution occurs sequentially in the zone based upon the write pointer);
the storage device receives the zone write commands ([0066] describing write commands to zones); and
responsive to receiving the zone write commands, the storage device executes the zone write commands on the given zone of the non-volatile memory of the storage device in an order specified by zone write sequence numbers included in a zone descriptor for the given zone ([0068] describing the write to the first block indicating that the zone is empty, [0053] describing how when a zone is empty the WP is at 0 and as described in [0068] the write pointer is incremented based on the number of blocks written; wherein the execution occurs sequentially in the zone based upon the write pointer).
Bennett et al. does not teach that the zone write command includes a field storing the write sequence number (in this case the “Write ID” of Bennett) such that the sequence number is embedded as reserved fields of the zone write commands as issued by a host device and specifying a sequential execution order for a zone for writes to logical blocks of the zone within the non-volatile memory of the storage computing device. Doucette teaches a system that assigns and tags write requests with sequence numbers in a system utilizing zoned solid state drives (see figures 1-2; par. 0027-0028, 0056-0060, 0080). The sequence numbers allow the writes to be processed sequentially even when they are received out of order. The write request contains a tagged sequence number, a starting LBA of a LZone and a skip mask indicating the blocks of the LZone that are already written. The location of each of these elements in the request may be considered a reserved field.
An obvious modification can be made-utilizing the sequence number (“Write ID”) embedded in a field of the write instruction sent from the processor to the non-volatile memory of Bennett, as suggested by Doucette. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Bennett to include the Write ID (sequence number) embedded in a field of the write command sent from the processor the non-volatile memory, as taught by Doucette, because Doucette teaches that this modification would help to ensure data integrity by ensuring that older data is not overwriting newer data (see paragraphs [0027] and [0028]).
As per claim 20, Doucette teaches that the sequence number is attached to the write command (figure 1-2; par. 0027-0028, 0056-0060 – writes are tagged with sequence numbers) which would constitute a “reserved field”.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Bennett and Doucette as applied to claim 1 above, and further in view of Tsokos et al. (US 2019/0370475) (hereafter Tsokos).
As per claim 2, Bennett teaches all the limitations of claim 1. Bennett does not explicitly teach wherein the processor is configured as firmware.
However, Tsokos teaches wherein the processor is configured as firmware ([0065]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the firmware of Tsokos with the processor of Bennett because there is a finite number of ways of implementing a processor ([0065]), i.e. software, firmware, or hardware (or a combination of any 2 or all 3).
As per claim 3, Bennett teaches all the limitations of claim 1. Bennett does not explicitly teach wherein the processor includes an application specific integrated circuit (ASIC), however Tsokos teaches implementing a processor as an ASIC ([0065]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teaching of Tsokos of implementing the processor of Bennett as an ASIC because there is a finite number of ways of implementing a processor ([0065]), i.e. either as an integrated circuit or discrete components.
Allowable Subject Matter
Claims 6-10 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed November 14, 2025 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to the amended subject matter have been addressed above. More specifically Doucette, discloses, “FIG. 2F shows another process 270 for handling write requests, according to one aspect of the present disclosure. In block B272, the ZTL 138 receives a tetris write request from the file system manager 134 with a tagged sequence number, a starting LBA of a LZone (141A, FIG. 1E) and a skip mask indicating the blocks of the LZone that are already written.” [par. 0080]. This further shows that the sequence number is a part of the tagged write requests.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., NVMe zone write commands) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
20 February 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139