DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The present application having Application No. 18/189,251 filed on 03/24/2023 presents claims 1-27 for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a frequency governor configured to…”, “a thermal-balancing scheduler configured to…” in claim 1-9.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 1, the limitations “a frequency governor configured to…”, “a thermal-balancing scheduler configured to…” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Applicant’s specification (paragraphs [0005] [0015] [0018] [0020]) merely recites exemplary “frequency governor” and “thermal-balancing scheduler” configured to perform various functionalities recited in claims 1-9. The specification does not provide algorithm support corresponding to these functions under the 112(f) interpretation of these nonce terms. While the specification recites ““frequency governor” and “thermal-balancing scheduler” exist within a computing device and functionality describing their roles. However, the written description fails to describe the corresponding structure, flowcharts, pseudocode, material, or acts for performing the entire claimed functions and to clearly link the structure, material, or acts to the functions. Functional language alone (e.g., scale a frequency or schedule tasks) fails written description for computer-implemented means-plus-function claims. Thus, the limitations are indefinite for failure to disclose adequate structure in the specification that signals a lack of written description under 35 U.S.C. 112(a) for these limitations.
The dependent claims 2-9 are also rejected based on virtue of their dependency to independent claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitations “a frequency governor configured to…”, “a thermal-balancing scheduler configured to…” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, algorithm, workflow, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. No hardware equivalents (e.g. DVFS circuitry), steps, workflow or equivalents disclose how scaling occurs per request or how scheduling integrates thermal data with task assignment. The specification fails to adequately disclose the corresponding structures. The claims fail to inform POSITA of metes and bounds with reasonable certainty such that the claims will cover all ways of performing a functions, known and unknown. Such an unbounded limitations render the claims indefinite. Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10-12 and 19-21 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Majumdar et al. (US 2017/0371719 A1) (hereinafter Majumdar) in view of Derek R. Kumar (US 2015/0346800 A1) (hereinafter Kumar).
As per claim 1, A computing device (e.g. Majumdar: [Fig. 1] [0016] discloses computing system. [Abstract] [0013] system, apparatus and method for performing temperature-aware task scheduling and proactive power management. [0056] discloses non-transitory storage medium comprising instructions that implements the method. Also see [Figs. 5-8] methods for performing temperature-aware task scheduling and power proactive management.) comprising: a plurality of processor clusters, each processor cluster comprising a temperature sensor (e.g. Majumdar: [Fig. 1] [0016-0022] discloses computing system comprising SOC that includes a plurality of processor cores 110A-N and number of sensors 170A-N that are spread throughout the SOC. In one embodiment, each sensor tracks the temperature of corresponding component. In another embodiment, there is a sensor for the different regions of SoC, where sensors are spread throughout SOC and located so as to track the temperature in different areas of SOC to monitor hot spots in SOC. [Fig. 2] [0029-0030] discloses sensors are spread throughout APU rather than in one region. For example each compute unit of GPU and core of CPU includes a sensor to monitor the temperature of each compute unit. Also see [0047].); a frequency governor configured to scale a frequency of each of the plurality of processor clusters (e.g. Majumdar: [0021] discloses power management unit uses dynamic voltage and frequency scaling (DVFS) to change the frequency and/or voltage of a processing unit. [0025-0026] SoC includes a phase-locked loop (PLL) unit configured to individually control and alter the frequency of each of the clock signals provides to respective ones of processor cores independently. [0043] if measured processing unit temperature is greater than or equal to the thermal limit, then the power management unit reduces the voltage and frequency supplied to the given processing unit.); and a thermal-balancing scheduler (e.g. Majumdar: [0013] discloses SoC includes a scheduler and a power management unit to schedule tasks. Scheduler schedules tasks to the processing units in a manner that minimizes non-uniform heat generation on the SoC. The scheduler prevents thermal limits from being exceeded by the SoC. Also see [0019] [Fig. 2] [0029] [Fig. 3][0031-0032] [0035-0037] [0039-0040] [0043] [0050-0051].) configured to: receive, from each temperature sensor, a temperature indication that indicates a temperature of a corresponding processor cluster to obtain an indication of thermal conditions of the plurality of processor clusters (e.g. Majumdar: [0022] [0030] discloses sensors tracks the temperature of corresponding component to monitor whether there are any hot spots in SoC. [0032] the task scheduler and proactive power manger utilize the measured temperature as inputs for determining thermal margin and temperature gradient, to schedule tasks. [Figs. 2, 3 and related description] the task scheduler receives temperature margins, temperature gradients and thermal metrics. Also see [0034-0036] [0047]. Thus, Majumdar expressly discloses receiving temperature indications from sensors corresponding to the respective processing units to determine thermal conditions.); schedule tasks to the plurality of processor clusters based upon the thermal conditions of the plurality of processor clusters (e.g. Majumdar: [0013] discloses system/apparatus/method for performing temperature aware task scheduling to plurality of processing units. The scheduler schedules pending tasks to the processing units to prevent thermal limits from being exceeded. [0015] [0019] discloses minimizing non-uniform heat generation on the SoC by scheduling tasks to the plurality of processing units based on the thermal gradients and the thermal margin. [0032] [0035] task scheduler and power manger utilize temperature margin and temperature gradient as input to determine how to schedule tasks. The task scheduler assigns task to a plurality of compute units of a SoC based on thermal margins and thermal gradient. [0037] the task scheduler schedules tasks such that the temperature increase of the compute units executing their assigned tasks stay below the temperature margin. Also see [0038-0040] [0043] [0048] [0051] [0053].); and request the frequency governor to scale a frequency of one or more of the plurality processor clusters based upon the scheduled tasks (e.g. Majumdar: [0021] discloses power management unit uses dynamic voltage and frequency scaling (DVFS) to change the frequency and/or voltage of a processing unit. [0025-0026] SoC includes a phase-locked loop (PLL) unit configured to individually control and alter the frequency of each of the clock signals provides to respective ones of processor cores independently. [0043] if measured processing unit temperature is greater than or equal to the thermal limit, then the power management unit reduces the voltage and frequency supplied to the given processing unit.).
As discussed above, Majumdar discloses requesting/scaling a frequency of one or more of the plurality of processor cluster but does not expressly disclose that “request to scale a frequency is based upon the scheduled tasks.”
However, Kumar discloses request the frequency governor to scale a frequency of one or more of the plurality processor clusters based upon the scheduled tasks (e.g. Kumar: [Abstract] discloses scheduling the plurality of tasks to be executed on the plurality of processing core during an execution window, and sets frequency of the processing cores based on one of the tasks scheduled to be executed on that processing core and thermal level. [0060] discloses setting frequency of CPU core based on the QoS of scheduled task. Thus, Kumar expressly discloses setting/scaling frequency of processing cores based upon the scheduled tasks.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Majumdar’s thermally aware scheduler with Kumar’s task-based frequency-scaling control because both references are directed to thermal management in multi-core computing environment and both use thermal state information to control processor operation. Incorporating Kumar’s teaching of setting processing-core frequency based on the scheduled task into Majumdar’s scheduler would have predictably improved thermal balancing by not only assigning tasks according to thermal conditions, but also adjusting the operating frequency of the selected processing units according to the tasks scheduled thereon. The combination would merely have involved applying a known task-aware frequency-scaling technique to Majumdar’s known thermal-aware scheduling system to obtain predictable results.
As per claim 2, the combination of Majumdar and Kumar discloses The computing device of claim 1 [See rejection to claim 1 above], wherein the thermal-balancing scheduler is configured to schedule tasks to the plurality of processor clusters to keep a thermal balance between the plurality of processor clusters (e.g. Majumdar: [Abstract] discloses minimizing non-uniform heat generation on the SoC by scheduling tasks to processing units based on the thermal conditions of processing units. [0013] discloses a scheduler schedules tasks to the processing units in a manner that minimizes non-uniform heat generation, and prevents thermal limits from being exceeded. [0019] discloses scheduler is configured to schedule tasks to cores and compute units so as to minimize, or otherwise reduce, non-uniform heat generation on SoC based on thermal conditions. [0048] discloses scheduling/assigning tasks to processing units to minimize non-uniform heat generation while preventing the thermal limits of the processing units from being exceeded. Also see [0015]).
As per claim 3, the combination of Majumdar and Kumar discloses The computing device of claim 1 [See rejection to claim 1 above], wherein the thermal-balancing scheduler is configured to characterize each of the plurality of processor clusters as one of a plurality of thermal states and the thermal-balancing scheduler is configured to schedule tasks based upon the thermal states of the plurality of processor clusters (e.g. Majumdar: [Abstract] [0014-0015] discloses monitoring a thermal margin available on each processing unit and determining thermal gradients of each processing unit; and discloses scheduling tasks based on the thermal metric, thermal gradients and thermal margin of the processing units. The SoC allows a given pending task to be scheduled on a given processing unit if the thermal gradient of the processing unit is less than or equal to the thermal margin of the given processor. [0019] discloses scheduler schedules tasks to cores and compute units based on the thermal metrics, the thermal gradients of each processing unit, and the thermal margin available on each processing unit. [0022] furthermore, Majumdar also discloses tracking temperature in different areas of SoC to monitor whether there are any hot spots in SoC. Thus, by determining thermal margin and thermal gradient of the processor or identifying any hot spots, Majumdar implicitly characterizes a thermal state for each processing unit. Since, margin is calculated as thermal limit minus current temperature of the components—this directly implies a state relative to thresholds.).
As per claims 10-12, these are method claims having similar limitations as cited in device/system claims 1-3, respectively. Thus, claims 10-12 are also rejected under the same rationale as cited in the rejection of rejected claims 1-3, respectively.
As per claims 19-21, these are non-transitory processor readable storage medium claims having similar limitations as cited in device/system claims 1-3, respectively. Thus, claims 19-21 are also rejected under the same rationale as cited in the rejection of rejected claims 1-3, respectively.
Allowable Subject Matter
Claims 4-9, 13-18 and 22-27 are rejected/objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, after addressing any claim objections/rejections detailed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hiren Patel whose telephone number is (571) 270-3366. The examiner can normally be reached on Monday-Friday 9:30 AM to 6:00 PM.
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If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner’s supervisor, April Y. Blair, can be reached at the following telephone number: (571) 270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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April 1, 2026
/HIREN P PATEL/Primary Examiner, Art Unit 2196