DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/15/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/15/2026 is in compliance with the provisions on 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 03/13/2026.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-14 and 20 have been considered but are moot because the arguments do not apply to the same combination of references being used in the current rejection. Applicant’s arguments are directed solely to the claimed invention as amended 03/13/2026, which has been rejected under new ground of rejection necessitated by amendment. See rejection below for full detail.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-6, 10-14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. (US 2022/0103767 A1) in view of Yamashita et al. (US 2013/0214128 A1) in view of Egawa (US 2015/0334323 A1) in view of Negishi (US 2017/0353679 A1).
Regarding claim 1, Yin et al. (hereafter referred as Yin) teaches an image sensor (Yin, Figs. 2 and 9-10, Paragraph 0020, 0040 and 0046) comprising:
n photo diodes which respectively generate electric charges in response to incident light and are adjacent to each other, where n is an integer equal to 2 or greater (Yin, Fig. 10, photodiode PD1-PD4, Paragraph 0040 and 0046, The n photo diodes are PD1-PD4 of sensing pixel 1010. Alternatively, the n photo diodes may be only PD1 and PD3 (sub-pixels R_5 and G2_5).);
a first pixel signal output circuit (Yin, Fig. 10, third transistor RST1 and fourth transistor SF1) shared by n photo diodes, wherein the first pixel signal output circuit converts an amount of the electric charges of each the n photo diodes in order into a first pixel signal in response to a first mode signal, and outputs the first pixel signal in order (Yin, Fig. 10, Paragraphs 0040 and 0049, “the sensing pixel 1010 may time-divisionally turn on the second transistors RTX1, RTX2, RTX3, and RTX4”. A first mode signal is the signal for controlling transistors RTX1, RTX2, RTX3, and RTX4 to time-divisionally turn on.); and
a second pixel signal output circuit (Yin, Figs. 9-10, sixth transistor DRST1, seventh transistor DSF1) includes a source-follower (Yin, Figs. 9-10, seventh transistor DSF1, Paragraph 0037), a floating diffusion region connected to the source-follower (Yin, Figs. 9-10, node DFN1 (Examiner notes DFN is well known as the floating diffusion, However, Yin does not explicitly state it is a floating diffusion).),
wherein first mode transistors are connected between each of the n photo diodes and the first pixel signal output circuit and are gated in order by the first mode signal (Yin, Fig. 10, second transistors RTX1, RTX2, RTX3, and RTX4, Paragraphs 0040 and 0049), and second mode transistors are connected between each of the n photo diodes and the floating diffusion region and are turned on simultaneously in response to a second mode signal (Yin, Fig. 10, fifth transistor DTX1, DTX2, DTX3, and DTX4, Paragraphs 0045 and 0053, “the sensing array 110 may simultaneously turn on all fifth transistors of the sensing sub-pixels R_5…B_5, and may simultaneously turn on all fifth transistors of sixteen other sensing sub-pixels of the sensing pixels 1110 to 1190”, A second mode signal is the signal for controlling the fifth transistors DTX1, DTX2, DTX3, and DTX4 to simultaneously turn on.),
wherein the floating diffusion region (Yin, Fig. 10, node DFN1) shared by the n photo diodes stores the electric charges transmitted from the n photo diodes (Yin, Fig. 10, node DFN1),
wherein the second pixel signal output circuit converts amounts of the electric charges of the n photo diodes stored together in the floating diffusion region or a voltage corresponding to the amounts of the electric charges of n photo diode into a second pixel signal in response to the second mode signal, and outputs the second pixel signal. (Yin, Fig. 10, Paragraphs 0045 and 0053, “the sensing array 110 may simultaneously turn on all fifth transistors of the sensing sub-pixels R_5, R_6, R_8, R_9, G1_4, G1_5, G1_7, G1_8, G2_2, G2_3, G2_5, G2_6, B_1, B_2, B_4, and B_5, and may simultaneously turn on all fifth transistors of sixteen other sensing sub-pixels of the sensing pixels 1110 to 1190”).
However, Yin does not teach the second pixel signal output circuit includes a transmission transistor, the floating diffusion region connected between the transmission transistor and the source-follower, and a storage region disposed between the n photo diodes and the floating diffusion region and connected between the n photo diodes and the transmission transistor, wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized, the second mode transistors are connected between each of the n photo diodes and the storage region; wherein the storage region shared by the n photo diodes stores the electric charges transmitted from the n photo diodes in a charge domain before being transferred to the floating diffusion region through the transmission transistor, nor wherein the second pixel signal output circuit converts amounts of the electric charges of the n photo diodes stored together in the storage region.
In reference to Yamashita et al. (hereafter referred as Yamashita), Yamashita teaches a pixel signal output circuit (Yamashita, Fig. 25) includes a source-follower (Yamashita, Fig. 25, source follower (SF), Paragraph 0061), a transmission transistor (Yamashita, Fig. 25, second charge transfer unit TX2, Paragraph 0061), a floating diffusion region connected between the transmission transistor and the source-follower (Yamashita, Fig. 25, floating diffusion FD, Paragraph 0061 and 0224) and a storage region disposed between n photo diodes (Yamashita, Fig. 25, PD_A and PD_B) and the floating diffusion region and connected between the n photo diodes and the transmission transistor (Yamashita, Fig. 25, first signal holding unit MEM, Paragraph 0219),
second mode transistors are connected between each of the n photo diodes and the storage region (Yamashita, Fig. 25, TX1_A and TX1_B, Paragraph 0220);
wherein the storage region shared by the n photo diodes stores the electric charges transmitted from the n photo diodes in a charge domain before being transferred to the floating diffusion region through the transmission transistor (Yamashita, Fig. 25, first signal holding unit MEM, Paragraph 0220 and 0238),
wherein the pixel signal output circuit converts amounts of the electric charges of the n photo diodes stored together in the storage region (Yamashita, Fig. 25, first signal holding unit MEM, Paragraph 0220 and 0238).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Yin with the pixel output circuitry as seen in Yamashita since it is a known pixel output circuit capable of summing signals for readout and performing global shutter (Yamashita, Paragraph 0006 and 0238) and would provide similar and expected results.
However, the combination of Yin and Yamashita does not teach wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized.
In reference to Egawa, Egawa teaches a pixel signal output circuit (Egawa, Figs. 9 and 14) includes a source-follower (Egawa, Figs. 9 and 14, TRampA, Paragraph 0061), a transmission transistor (Egawa, Figs. 9 and 14, TRmixA1, Paragraph 0061), a floating diffusion region connected between the transmission transistor and the source-follower (Egawa, Figs. 9 and 14, FDAm, Paragraph 0061) and a storage region disposed between two photo diodes (Egawa, Figs. 9 and 14, PD_Gr1 and PD_B1) and the floating diffusion region and connected between the n photo diodes and the transmission transistor (Egawa, Figs. 9 and 14, FDA1, Paragraph 0061); and
wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the two photo diodes is minimized (Egawa, Figs. 14, FDA1, Paragraph 0109).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin and Yamashita with the teaching of placing the storage region between the photodiodes as seen in Egawa to reduce the distance between the photodiodes and the storage region and since it is a known placement for a pixel circuit which includes a storage region, transmission transistor and floating diffusion region.
However, the combination of Yin, Yamashita and Egawa does not teach wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized, where n is four.
In reference to Negishi, Negishi teaches wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized, where n is four (Negishi, Fig. 10A and 12, Paragraph 0133, Storage region (FD unit 229) is disposed where the sum of distances is minimized.).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin, Yamashita and Egawa with the teaching of the placement of a storage region to minimize the sum of distances for four photodiodes as seen in Negishi since it is a known placement for the location of a charge storing region for four photodiodes and would produce similar and expected results for reducing the distance between the photodiodes and the storage region.
Regarding claim 3, the combination of Yin, Yamashita, Egawa and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit comprises:
a first floating diffusion region which stores the electric charges transmitted from a photo diode connected to an on-state first mode transistor from among the n first mode transistors (Yin, Fig. 10, Node FN1, (Examiner notes FN is well known as the floating diffusion as seen in Yamashita, Fig. 6, floating diffusion node 163));
a first source-follower which amplifies a voltage that corresponds to an amount of the electric charges stored in the first floating diffusion region (Yin, Figs. 9-10, fourth transistor SF1, Paragraph 0036).
However, the combination of Yin, Yamashita, Egawa and Negishi does not teach a first selection transistor which outputs the first pixel signal that corresponds to the voltage output from the first source-follower, to a column line, in response to a column selection signal.
In further reference to Yamashita, Yamashita teaches a first selection transistor which outputs the first pixel signal that corresponds to the voltage output from the first source-follower, to a column line, in response to a column selection signal (Yamashita, Fig. 25, selection transistor SEL, Paragraph 0061).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin, Yamashita, Egawa and Negishi with the select transistor in the pixel output circuits as seen in Yamashita to allow for further control for selecting when to output pixel signals to the column line.
Regarding claim 5, the combination of Yin, Yamashita, Egawa and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), further comprising n second mode transistors each of which comprises a first end connected to a corresponding photo diode from among the n photo diodes and a second other end connected to the second pixel signal output circuit and is gated at the same time by the second mode signal (Yin, Figs. 9-10, fifth transistor DTX1-DTX4, Paragraphs 0050 and 0053).
Regarding claim 6, the combination of Yin, Yamashita, Egawa and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the second pixel signal output circuit comprises:
the transmission transistor which comprises a first end connected to the storage region and is gated by a transmission signal (Yamashita, Fig. 25, second charge transfer unit TX2, Paragraph 0061);
the floating diffusion region which comprises a first end connected to a second other end of the transmission transistor and stores the electric charges transmitted from the storage region (Yin, Figs. 9-10, node DFN1, Yamashita, Fig. 25, floating diffusion FD, Paragraph 0061 and 0224);
the source-follower which amplifies a voltage that corresponds to amounts of the electric charges stored in the floating diffusion region (Yin, Figs. 9-10, seventh transistor DSF1, Paragraph 0037, Yamashita, Fig. 25, source follower (SF), Paragraph 0061).
However, the combination of Yin, Yamashita, Egawa and Negishi does not teach a second selection transistor which outputs the second pixel signal, that corresponds to the voltage output from the source-follower, to the column line, in response to the column selection signal.
In further reference to Yamashita, Yamashita teaches a second selection transistor which outputs the second pixel signal, that corresponds to the voltage output from the second source-follower, to the column line, in response to the column selection signal (Yamashita, Fig. 25, selection transistor SEL, Paragraph 0061).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin, Yamashita, Egawa and Negishi with the select transistor in the pixel output circuits as seen in Yamashita to allow for further control for selecting when to output pixel signals of the second pixel signal output circuit to the column line.
Regarding claim 10, the combination of Yin, Yamashita, Egawa and Negishi
teaches the image sensor of claim 1 (see claim 1 analysis), wherein the n photo diodes are adjacent to each other in a column direction and at least one of the first pixel signal output circuit and the second pixel signal output circuit is shared by the n photo diodes and other n photo diodes adjacent to corresponding photo diodes from among n photo diodes in a row direction (Yin, Figs. 2 and 10, The n photo diodes may be only PD1 and PD3 (sub-pixels R_5 and G2_5). Referring to Figure 2, PD1 and PD3 (sub-pixels R_5 and G2_5) are adjacent in the column direction. Other n photo diodes adjacent the n photo diodes may be PD2 and PD4 (sub-pixels G1_5 and B_5) and are adjacent in the row direction.).
Regarding claim 11, the combination of Yin, Yamashita, Egawa and Negishi
teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit converts amounts of the electric charges of some photo diodes from among the n photo diodes into the first pixel signal and outputs the first pixel signal in order or at the same time, in response to the first mode signal (Yin, Figs. 5-6, Paragraph 0049, Some of the n photo diodes are read out in order from times t0 to t13 (Fig. 5) or t0’ to t8’ (Fig. 6). “Some” may be seen as one photo diode, two photo didoes or three photo diodes.), and the second pixel signal output circuit outputs the second pixel signal that corresponds to amounts of the electric charges of the remaining photo diodes from among n photo diodes, in response to the second mode signal (Yin, Figs. 5-6, Paragraph 0053, Outputting all of the n photo diodes includes outputting the remaining photo diodes from among n photo diodes.).
Regarding claim 12, the combination of Yin, Yamashita, Egawa and Negishi
teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit converts amounts of the electric charges of some photo diodes from among the n photo diodes into the first pixel signal and outputs the first pixel signal in order or at the same time, in response to the first mode signal (Yin, Figs. 5-6, Paragraph 0049, Some of the n photo diodes are read out in order from times t0 to t13 (Fig. 5) or t0’ to t8’ (Fig. 6). “Some” may be seen as one photo diode, two photo didoes or three photo diodes.).
Regarding claim 13, the combination of Yin, Yamashita, Egawa and Negishi
teaches the image sensor of claim 1 (see claim 1 analysis), wherein the second pixel signal output circuit outputs the second pixel signal that corresponds to amounts of the electric charges of some photo diodes from among the n photo diodes, in response to the second mode signal (Yin, Figs. 5-6, Paragraph 0053, Outputting all of the n photo diodes includes outputting some of the photo diodes from among n photo diodes.).
Regarding claim 14, the combination of Yin, Yamashita, Egawa and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit is operated by using a rolling shutter driving method, in response to the first mode signal, and the second pixel signal output circuit is operated by using a global shutter driving method, in response to the second mode signal (Yin, Paragraph 0026).
Regarding claim 20, the combination of Yin, Yamashita, Egawa and Negishi teaches an image processing apparatus comprising:
the image sensor of claim 1 (see claim 1 analysis); and
an image processor which receives a digital pixel signal corresponding to the first pixel signal or the second pixel signal from the image sensor to generate image data Yin, Paragraph 0029, “back-end digital processing circuit may generate a sensing image according to the first sensing signals”).
Claim(s) 1-3, 5-6, 10-14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. (US 2022/0103767 A1) in view of Ha (US 2022/0264049 A1) in view of Negishi (US 2017/0353679 A1).
Regarding claim 1, Yin et al. (hereafter referred as Yin) teaches an image sensor (Yin, Figs. 2 and 9-10, Paragraph 0020, 0040 and 0046) comprising:
n photo diodes which respectively generate electric charges in response to incident light and are adjacent to each other, where n is an integer equal to 2 or greater (Yin, Fig. 10, photodiode PD1-PD4, Paragraph 0040 and 0046, The n photo diodes are PD1-PD4 of sensing pixel 1010. Alternatively, the n photo diodes may be only PD1 and PD3 (sub-pixels R_5 and G2_5).);
a first pixel signal output circuit (Yin, Fig. 10, third transistor RST1 and fourth transistor SF1) shared by n photo diodes, wherein the first pixel signal output circuit converts an amount of the electric charges of each the n photo diodes in order into a first pixel signal in response to a first mode signal, and outputs the first pixel signal in order (Yin, Fig. 10, Paragraphs 0040 and 0049, “the sensing pixel 1010 may time-divisionally turn on the second transistors RTX1, RTX2, RTX3, and RTX4”. A first mode signal is the signal for controlling transistors RTX1, RTX2, RTX3, and RTX4 to time-divisionally turn on.); and
a second pixel signal output circuit (Yin, Figs. 9-10, sixth transistor DRST1, seventh transistor DSF1) includes a source-follower (Yin, Figs. 9-10, seventh transistor DSF1, Paragraph 0037), a floating diffusion region connected to the source-follower (Yin, Figs. 9-10, node DFN1 (Examiner notes DFN is well known as the floating diffusion, However, Yin does not explicitly state it is a floating diffusion).),
wherein first mode transistors are connected between each of the n photo diodes and the first pixel signal output circuit and are gated in order by the first mode signal (Yin, Fig. 10, second transistors RTX1, RTX2, RTX3, and RTX4, Paragraphs 0040 and 0049), and second mode transistors are connected between each of the n photo diodes and the floating diffusion region and are turned on simultaneously in response to a second mode signal (Yin, Fig. 10, fifth transistor DTX1, DTX2, DTX3, and DTX4, Paragraphs 0045 and 0053, “the sensing array 110 may simultaneously turn on all fifth transistors of the sensing sub-pixels R_5…B_5, and may simultaneously turn on all fifth transistors of sixteen other sensing sub-pixels of the sensing pixels 1110 to 1190”, A second mode signal is the signal for controlling the fifth transistors DTX1, DTX2, DTX3, and DTX4 to simultaneously turn on.),
wherein the floating diffusion region (Yin, Fig. 10, node DFN1) shared by the n photo diodes stores the electric charges transmitted from the n photo diodes (Yin, Fig. 10, node DFN1),
wherein the second pixel signal output circuit converts amounts of the electric charges of the n photo diodes stored together in the floating diffusion region or a voltage corresponding to the amounts of the electric charges of n photo diode into a second pixel signal in response to the second mode signal, and outputs the second pixel signal. (Yin, Fig. 10, Paragraphs 0045 and 0053, “the sensing array 110 may simultaneously turn on all fifth transistors of the sensing sub-pixels R_5, R_6, R_8, R_9, G1_4, G1_5, G1_7, G1_8, G2_2, G2_3, G2_5, G2_6, B_1, B_2, B_4, and B_5, and may simultaneously turn on all fifth transistors of sixteen other sensing sub-pixels of the sensing pixels 1110 to 1190”).
However, Yin does not teach the second pixel signal output circuit includes a transmission transistor, the floating diffusion region connected between the transmission transistor and the source-follower, and a storage region disposed between the n photo diodes and the floating diffusion region and connected between the n photo diodes and the transmission transistor, wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized, the second mode transistors are connected between each of the n photo diodes and the storage region; wherein the storage region shared by the n photo diodes stores the electric charges transmitted from the n photo diodes in a charge domain before being transferred to the floating diffusion region through the transmission transistor, nor wherein the second pixel signal output circuit converts amounts of the electric charges of the n photo diodes stored together in the storage region.
In reference to Ha, Ha teaches a pixel signal output circuit (Ha, Fig. 4) includes a source-follower (Ha, Fig. 4, transistors DX, Paragraph 0055), a transmission transistor (Ha, Fig. 4, transistors TR1, Paragraph 0047), a floating diffusion region connected between the transmission transistor and the source-follower (Ha, Fig. 4, common node CL1) and a storage region disposed between n photo diodes (Ha, Fig. 4, PD1-PD4) and the floating diffusion region and connected between the n photo diodes and the transmission transistor (Ha, Fig. 4, FD1, Paragraph 0035),
a second mode transistor is connected between each of the n photo diodes and the storage region (Ha, Fig. 4, TS1-TS4, Paragraph 0035);
wherein the storage region shared by the n photo diodes stores the electric charges transmitted from the n photo diodes in a charge domain before being transferred to the floating diffusion region through the transmission transistor (Ha, Fig. 4, FD1, Paragraph 0035),
wherein the pixel signal output circuit converts amounts of the electric charges of the n photo diodes stored together in the storage region (Ha, Paragraph 0020 and 0030).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Yin with the pixel output circuitry as seen in Ha since it is a known pixel output circuit capable of summing signals for readout and would provide similar and expected results (Ha, Paragraph 0030).
However, the combination of Yin and Ha does not teach wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized.
In reference to Negishi, Negishi teaches wherein the storage region is disposed at a position where a sum of distances from the storage region to each of the n photo diodes is minimized (Negishi, Fig. 10A and 12, Paragraph 0133, Storage region (FD unit 229) is disposed where the sum of distances is minimized.).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin and Ha with the teaching of the placement of a storage region to minimize the sum of distances for four photodiodes as seen in Negishi since it is a known placement for the location of a charge storing region for four photodiodes and would produce similar and expected results for reducing the distance between the photodiodes and the storage region.
Regarding claim 3, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit comprises:
a first floating diffusion region which stores the electric charges transmitted from a photo diode connected to an on-state first mode transistor from among the n first mode transistors (Yin, Fig. 10, Node FN1, (Examiner notes FN is well known as the floating diffusion as seen in Ha, Fig. 4));
a first source-follower which amplifies a voltage that corresponds to an amount of the electric charges stored in the first floating diffusion region (Yin, Figs. 9-10, fourth transistor SF1, Paragraph 0036).
However, the combination of Yin, Ha and Negishi does not teach a first selection transistor which outputs the first pixel signal that corresponds to the voltage output from the first source-follower, to a column line, in response to a column selection signal.
In further reference to Ha, Ha teaches a first selection transistor which outputs the first pixel signal that corresponds to the voltage output from the first source-follower, to a column line, in response to a column selection signal (Ha, Fig. 4, election transistor SX, Paragraph 0054).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin, Ha and Negishi with the select transistor in the pixel output circuits as seen in Ha to allow for further control for selecting when to output pixel signals to the column line.
Regarding claim 5, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), further comprising n second mode transistors each of which comprises a first end connected to a corresponding photo diode from among the n photo diodes and a second other end connected to the second pixel signal output circuit and is gated at the same time by the second mode signal (Yin, Figs. 9-10, fifth transistor DTX1-DTX4, Paragraphs 0050 and 0053).
Regarding claim 6, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the second pixel signal output circuit comprises:
the transmission transistor which comprises a first end connected to the storage region and is gated by a transmission signal (Ha, Fig. 4, transistors TR1, Paragraph 0047);
the floating diffusion region which comprises a first end connected to a second other end of the transmission transistor and stores the electric charges transmitted from the storage region (Yin, Figs. 9-10, node DFN1, Ha, Fig. 4, common node CL1);
the source-follower which amplifies a voltage that corresponds to amounts of the electric charges stored in the floating diffusion region (Yin, Figs. 9-10, seventh transistor DSF1, Paragraph 0037, Ha, Fig. 4, transistors DX, Paragraph 0055).
However, the combination of Yin, Ha and Negishi does not teach a second selection transistor which outputs the second pixel signal, that corresponds to the voltage output from the source-follower, to the column line, in response to the column selection signal.
In further reference to Ha, Ha teaches a second selection transistor which outputs the second pixel signal, that corresponds to the voltage output from the second source-follower, to the column line, in response to the column selection signal ((Ha, Fig. 4, election transistor SX, Paragraph 0054)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Yin, Ha and Negishi with the select transistor in the pixel output circuits as seen in Ha to allow for further control for selecting when to output pixel signals of the second pixel signal output circuit to the column line.
Regarding claim 10, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the n photo diodes are adjacent to each other in a column direction and at least one of the first pixel signal output circuit and the second pixel signal output circuit is shared by the n photo diodes and other n photo diodes adjacent to corresponding photo diodes from among n photo diodes in a row direction (Yin, Figs. 2 and 10, The n photo diodes may be only PD1 and PD3 (sub-pixels R_5 and G2_5). Referring to Figure 2, PD1 and PD3 (sub-pixels R_5 and G2_5) are adjacent in the column direction. Other n photo diodes adjacent the n photo diodes may be PD2 and PD4 (sub-pixels G1_5 and B_5) and are adjacent in the row direction.).
Regarding claim 11, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit converts amounts of the electric charges of some photo diodes from among the n photo diodes into the first pixel signal and outputs the first pixel signal in order or at the same time, in response to the first mode signal (Yin, Figs. 5-6, Paragraph 0049, Some of the n photo diodes are read out in order from times t0 to t13 (Fig. 5) or t0’ to t8’ (Fig. 6). “Some” may be seen as one photo diode, two photo didoes or three photo diodes.), and the second pixel signal output circuit outputs the second pixel signal that corresponds to amounts of the electric charges of the remaining photo diodes from among n photo diodes, in response to the second mode signal (Yin, Figs. 5-6, Paragraph 0053, Outputting all of the n photo diodes includes outputting the remaining photo diodes from among n photo diodes.).
Regarding claim 12, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit converts amounts of the electric charges of some photo diodes from among the n photo diodes into the first pixel signal and outputs the first pixel signal in order or at the same time, in response to the first mode signal (Yin, Figs. 5-6, Paragraph 0049, Some of the n photo diodes are read out in order from times t0 to t13 (Fig. 5) or t0’ to t8’ (Fig. 6). “Some” may be seen as one photo diode, two photo didoes or three photo diodes.).
Regarding claim 13, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the second pixel signal output circuit outputs the second pixel signal that corresponds to amounts of the electric charges of some photo diodes from among the n photo diodes, in response to the second mode signal (Yin, Figs. 5-6, Paragraph 0053, Outputting all of the n photo diodes includes outputting some of the photo diodes from among n photo diodes.).
Regarding claim 14, the combination of Yin, Ha and Negishi teaches the image sensor of claim 1 (see claim 1 analysis), wherein the first pixel signal output circuit is operated by using a rolling shutter driving method, in response to the first mode signal, and the second pixel signal output circuit is operated by using a global shutter driving method, in response to the second mode signal (Yin, Paragraph 0026).
Regarding claim 20, the combination of Yin, Ha and Negishi teaches an image processing apparatus comprising:
the image sensor of claim 1 (see claim 1 analysis); and
an image processor which receives a digital pixel signal corresponding to the first pixel signal or the second pixel signal from the image sensor to generate image data Yin, Paragraph 0029, “back-end digital processing circuit may generate a sensing image according to the first sensing signals”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at (571) 272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WESLEY J CHIU/ Examiner, Art Unit 2639
/TWYLER L HASKINS/ Supervisory Patent Examiner, Art Unit 2639
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