Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 15, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seebacher et al. (US 20220329206 A1), hereafter referred to as “Seebacher”.
Regarding claim 1, in the embodiment of Figs. 2A, 2E, 3A, and 3B, Seebacher discloses:
A power amplifier circuit (Figs. 2A, 2E, 3A, and 3B, power amplifier 200,250) comprising:
a first amplification circuit element (input transistor T1P) comprising an output terminal (T1P collector) to which a power supply voltage (amplified voltage difference VB1) is supplied and configured to amplify a harmonic signal input to an input terminal of the first amplification circuit element (paragraph [0017], lines 7-9, RF input signal is introduced to the input of transistor T1P);
a second amplification circuit element (input transistor T1N) comprising an output terminal (T1N collector) to which the power supply voltage is supplied, and configured to amplify the harmonic signal input to an input terminal of the second amplification circuit element (paragraph [0017], lines 7-9, RF input signal is introduced to the input of transistor T1N);
a bias circuit (Figs. 2A, transconductance amplifier 202 and transistor T3 form a bias circuit) that configured to supply a bias to each of the input terminal of the first amplification circuit element and the input terminal of the second amplification circuit element (paragraph [0017] lines 11-14, T1P and T1N are biased by T3);
a first resistance circuit element (left resistor R¬SENSE) comprising one end electrically connected to the output terminal of the first amplification circuit element (left of left resistor RSENSE is connected to T1P collector through element LS, as shown in Figs. 2A and 2E); and
a second resistance circuit element (right resistor R¬SENSE) comprising one end electrically connected to the output terminal of the second amplification circuit element (right of right resistor RSENSE is connected to T1N collector through element LS, as shown in Figs. 2A and 2E) and a second end electrically connected to a second end of the first resistance circuit element in series (as shown in Figs. 2A and 2E);
wherein the bias circuit is electrically connected to a connection point (node between left RSENSE and right RSENSE) in a portion in which the second end of the first resistance circuit element and the second end of the second resistance circuit element are electrically connected in series (left and right RSENSE are in series, as shown in Figs. 2A and 2E).
Regarding claim 2, in the embodiment of Figs. 2A, 2E, 3A, and 3B, Seebacher discloses:
the bias circuit is electrically connected to the connection point that becomes a virtual ground based on a relationship between the first amplification circuit element and the second amplification circuit element (T3 is shown to be connected to ground).
Regarding claims 3 and 16, in the embodiment of Figs. 2A, 2E, 3A, and 3B, Seebacher discloses:
depending on the power supply voltage supplied to the first amplification circuit element and the power supply voltage supplied to the second amplification circuit element , an adjustment current is supplied from the connection point to the bias circuit or from the bias circuit to the connection point, the adjustment current comprising a current configured to adjust the bias (Fig. 2A, paragraph [0025], lines 24-32, Transconductance amplifier 202 provides amplified current proportional to common mode voltage VE2,DC and VREF, The bias feedback loop formed by 202, T3, T1P, T1N adjust the bias current of T1P, T1N).
Regarding claim 15, in the embodiment of Figs. 2A, 2E, 3A, and 3B, Seebacher discloses:
the first amplification circuit element and the second amplification circuit element constitute a differential amplifier circuit (paragraph [0019] lines 1-5, a differential signal is amplified by input transistors T1P and T1N).
Allowable Subject Matter
Claims 5, 7, 10-13 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5, 19, and 20:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “a second diode electrically connected to the first resistance circuit element in series between the output terminal of the first amplification circuit element and the connection point; and
a third diode electrically connected to the second resistance circuit element in series between the output terminal of the second amplification circuit element and the connection point.”
Regarding claims 17 and 18:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “a first diode electrically connected in series between the connection point and the bias circuit.”
Claims 7, 10-13 are objected to as being dependent on objected claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MALANE LIENG/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843