DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-11 and 13 are objected to because of the following informalities:
In claim 1, lines 7-8, “pass process queries to targeted entities and relationships” should read “pass processed queries to targeted entities and relationships”
In claim 8, line 2, “are implemented on neuromorphic chip device” should read “are implemented on a neuromorphic chip device”
In claim 13, line 1, “The method of claim 12 wherein,” should read “The method of claim 12, wherein”
Dependent claims 2-11 are objected based on being directly or indirectly dependent on objected claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1,
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 1 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“process incoming queries”
“set policies for processing in the neurons and synapses of the plurality of neural arrays”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass processing incoming queries (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can process incoming queries); and setting policies for processing in the neurons and synapses of the neural arrays (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can, for the neurons and synapses of the neural arrays, set policies for processing).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a plurality of neural arrays, each of the neural arrays containing circuits that represent neurons and synapses, each of the neurons and synapses having processing, communication, learning and storage capability, wherein entities and relationships of the knowledge graph are configured within the plurality of neural arrays”
“a query processing engine coupled in parallel to the plurality of neural arrays”
“a policy/compliance engine coupled to the plurality of neural arrays”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“pass process queries to targeted entities and relationships representing the plurality of neural arrays”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and engines for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 2,
Claim 2 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 2 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“locate an entity represented in the knowledge graph within the plurality of neural arrays”
“pool neighbors of the entity in the knowledge graph as represented in the plurality of neural arrays”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass locating an entity represented in the knowledge graph (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can locate an entity represented within the knowledge graph); and pooling neighbors of the entity in the knowledge graph (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can pool neighbors of the entity in the knowledge graph).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“the query processing engine”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 1 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and engines for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 3,
Claim 3 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 3 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“wherein the pooled neighbors … perform accelerated risk calculations”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass using the pooled neighbors to perform accelerated risk calculations (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can perform accelerated risk calculations).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“the plurality of neural arrays”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 2 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and engines for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 4,
Claim 4 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 4 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“permit or restrict access to data represented in one or more parts of the knowledge graph represented in the plurality of neural arrays based on the set policies”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass permitting or restricting access to data represented in the knowledge graph based on the set policies (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can, based on the set policies, restrict or permit access to data represented in the knowledge graph).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“the policy/compliance engine”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 1 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and engines for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 5,
Claim 5 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 5 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 1. The limitations of claim 5 are only additional elements to the abstract ideas of claim 1.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“one or more non-volatile memory storage units coupled to the plurality of neural arrays”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 1 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, and memory storage units for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 6,
Claim 6 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 6 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 1. The limitations of claim 6 are only additional elements to the abstract ideas of claim 1.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a central processing unit (CPU) coupled to the plurality of neural arrays, the query processing engine and the policy/compliance engine”
“one or more vector processing units coupled to the CPU, the plurality of neural arrays, the query processing engine and the policy/compliance engine”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 1 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, and processing units for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 7,
Claim 7 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 7 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 1. The limitations of claim 7 are only additional elements to the abstract ideas of claim 1.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the plurality of neural arrays, the query processing engine, and the policy/compliance engine are implemented on a dedicated hardware device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 1 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, and a dedicated hardware device for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 8,
Claim 8 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 8 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 7. The limitations of claim 8 are only additional elements to the abstract ideas of claim 7.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the plurality of neural arrays, query processing and policy/compliance engine are implemented on neuromorphic chip device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 7 of generic neural arrays, engines, and a dedicated hardware device, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, and a neuromorphic chip device for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 9,
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 9 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 1. The limitations of claim 9 are only additional elements to the abstract ideas of claim 1.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the plurality of neural arrays, query processing and policy/compliance engine are implemented using a customizable hardware device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 1 of generic neural arrays and engines, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, and a customizable hardware device for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 10,
Claim 10 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 10 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 6. The limitations of claim 10 are only additional elements to the abstract ideas of claim 6.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a three-dimensional architecture including one or more memory layers and wherein the CPU constitutes one layer of the three-dimensional architecture, wherein the CPU is interconnected to the one or more memory layers and the one or more memory layers are further interconnected to the plurality of neural arrays, which constitutes another distinct layer”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 6 of generic neural arrays, engines, and processing units, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, memory. and processing units for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 11,
Claim 11 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 11 is directed to an integrated knowledge graph system, which is directed to a machine, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 10. The limitations of claim 6 are only additional elements to the abstract ideas of claim 10.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the one or more memory layers comprise a first dynamic memory layer coupled to the CPU and a second non-volatile storage array layer interconnected to the dynamic memory layer and to the plurality of neural arrays”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 10 of generic neural arrays, engines, memory, and processing units, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “pass …” amounts to no more than insignificant extra-solution activity for passing/transmitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engines, memory, and processing units for applying the abstract ideas) or insignificant extra-solution activity (i.e. passing/transmitting data). Furthermore, the “pass …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 12,
Claim 12 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 12 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“identifying elements within the data including entity-level characteristics, size, entity- type, and functional requirements”
“determining one or more neural arrays having capabilities suited for mapping of the identified elements”
“mapping the elements onto the suited neural arrays”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass identifying elements within the data including characteristics, size, type, and functional requirements (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can identify elements within the data); determining neural arrays having capabilities suited for mapping the identified elements (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can determine neural array with capabilities suited for mapping the identified elements); and mapping the elements onto the suited neural arrays (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can map the elements to suited neural arrays).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the neural arrays contain circuits that represent neurons and synapses, each of the neurons and synapses having processing, communication, learning and storage capability”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“receiving data targeted for mapping onto the knowledge graph”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving data). Furthermore, the “receiving …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 13,
Claim 13 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 13 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“process the identified elements within the data”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass processing the identified elements within the data (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can process the identified elements in the data).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“the neural array includes or is connected to functional block components”
“wherein the functional block components comprise at least one of a specialized accelerator and an application-specific functional unit”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 12 of generic neural arrays, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “receiving …” amounts to no more than insignificant extra-solution activity for receiving data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and functional block components for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving data). Furthermore, the “receiving …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 14,
Claim 14 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 14 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 12. The limitations of claim 14 are only additional elements to the abstract ideas of claim 12.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the one or more neural arrays are implemented on a dedicated hardware device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 12 of generic neural arrays, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “receiving …” amounts to no more than insignificant extra-solution activity for receiving data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and a dedicated hardware device for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving data). Furthermore, the “receiving …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 15,
Claim 15 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 15 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 14. The limitations of claim 15 are only additional elements to the abstract ideas of claim 14.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“wherein the one or more neural arrays are implemented on a neuromorphic chip device”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). In addition, the recitation of additional elements in claim 14 of generic neural arrays and a dedicated hardware device, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional element of “receiving …” amounts to no more than insignificant extra-solution activity for receiving data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays and a neuromorphic chip device for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving data). Furthermore, the “receiving …” limitation is insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 16,
Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 16 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“determining whether the query meets requirements for compliance”
“after the determining step, when requirements for compliance are not met: restricting access to one or more components of the knowledge graph”
“adjusting the query to accommodate for the restricted access”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass determining if the query meets requirements for compliance (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can determine whether the query meeting the requirements for compliance); when the requirements are not met, restricting access to components of the knowledge graph (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can restrict access to components of the knowledge graph when requirements are not met) and adjusting the query to accommodate for the restricted access (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can adjust the query to accommodate the restricted access).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“a plurality of neural arrays comprising circuits that represent neurons and synapses, each of the neurons and synapses having processing, communication, learning and storage capability”
“a policy/compliance engine that is coupled to the plurality of neural arrays”
“an input/output system”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“receiving a query for obtaining or updating information in a knowledge graph”
“submitting the adjusted query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engine, and I/O system for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving and transmitting/submitting data). Furthermore, the “receiving …” and “submitting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 17,
Claim 17 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 17 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 16. The limitations of claim 17 are only additional elements to the abstract ideas of claim 16.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“an input/output system”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“after the determining step, when requirements for compliance are met, submitting the query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). In addition, the recitation of additional elements in claim 16 of generic neural arrays, engine, and I/O system, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional elements of “receiving …” and “submitting …” amount to no more than insignificant extra-solution activity for receiving and transmitting/submitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engine, and I/O system for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving and transmitting/submitting data). Furthermore, the “receiving …” and “submitting …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 18,
Claim 18 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 18 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: The limitations:
“determining whether the results of the query meet with compliance requirements”
As drafted, under their broadest reasonable interpretations, cover mental processes (concepts performed in the human mind (including an observation, evaluation, judgement, opinion)) but for the recitation of mere instructions to apply language (See MPEP 2106.05(f)) and insignificant extra-solution activity (See MPEP 2106.05(g)). The above limitations in the context of this claim encompass determining if the results of the query meet with compliance requirements (corresponds to evaluation and judgement; in particular, a human, with the assistance of pen and paper, can determine whether the query results meet compliance requirements).
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“sending results of the query including obtained or updated information to the policy compliance engine”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). In addition, the recitation of additional elements in claim 16 of generic neural arrays, engine, and I/O system, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional elements of “receiving …” and “submitting …” amount to no more than insignificant extra-solution activity for receiving and transmitting/submitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engine, and I/O system for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving and transmitting/submitting data). Furthermore, the “receiving …”, “submitting …”, and “sending …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Regarding Claim 19,
Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claim 19 is directed to a method, which is directed to a process, one of the statutory categories.
Step 2A Prong One Analysis: Please see the analysis of claim 16. The limitations of claim 19 are only additional elements to the abstract ideas of claim 16.
Step 2A Prong Two Analysis: The judicial exceptions are not integrated into a practical application. In particular, the claim recites additional elements that are mere instructions to apply (See MPEP 2106.05(f)) or insignificant extra-solution activity (See MPEP 2106.05(g)). The limitations:
“the input/output system”
As drafted, are additional elements that amount to no more than mere instructions to apply the exception for the abstract ideas. See MPEP 2106.05(f). The limitations:
“wherein the input/output system submits multiple queries to the knowledge graph in parallel and the knowledge graph processes the queries in parallel”
As drafted, are additional elements that correspond to insignificant extra-solution activity. In particular, the additional elements are merely directed towards mere data gathering. See MPEP 2106.05(g). In addition, the recitation of additional elements in claim 16 of generic neural arrays, engine, and I/O system, as drafted, are reciting mere instructions to apply language such that it amounts to no more than mere instructions to apply the exceptions. In addition, the additional elements of “receiving …” and “submitting …” amount to no more than insignificant extra-solution activity for receiving and transmitting/submitting data. Therefore, the additional elements do not integrate the abstract ideas into a practical application.
Step 2B Analysis: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, all of the additional elements are “mere instructions to apply an exception” (I.e. the additional elements describe a generic neural arrays, engine, and I/O system for applying the abstract ideas) or insignificant extra-solution activity (i.e. receiving and transmitting/submitting data). Furthermore, the “receiving …”, “submitting …”, and “… submits …” limitations are insignificant extra-solution activity that is well-understood, routine, and conventional according to MPEP 2106.05(d) (“The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity… i. Receiving or transmitting data over a network). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0135659 A1) in view of Dingwall et al. (US 2018/0121546 A1).
Regarding claim 1,
Wu teaches an integrated knowledge graph system (Fig. 8; Fig. 9; [0144]: "FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships" teaches a neural network circuit implementing a knowledge graph (integrated knowledge graph) for performing a question-answering (QA) method) comprising:
a plurality of neural arrays, each of the neural arrays containing circuits that represent neurons and synapses, each of the neurons and synapses having processing, communication, learning and storage capability, wherein entities and relationships of the knowledge graph are configured within the plurality of neural arrays (Fig. 8; Fig. 9; [0144]: "FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships" teaches a neural network circuit implementing a knowledge graph (integrated knowledge graph) for performing a question-answering (QA) method, the knowledge graph mapping entities and relationships. Fig. 29; [0449]-[0454]: "FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908. … In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. … For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip, or with dedicated connections. … In at least one embodiment, at least one component shown or described with respect to FIG. 29 is used to implement techniques and/or functions described in connection with FIGS. 1-10. … In at least one embodiment, neuromorphic processor 2900 of FIG. 29 is utilized to implement techniques and/or functions described in connection with FIGS. 1-10" teaches a neuromorphic processor for implementing the neural network knowledge graph of Figs. 8-9 (e.g. configuring the entities and relationships within the neural arrays) that comprises a plurality of neural arrays comprising neuron and synapses interconnected for processing, inference, and training (having processing, communication, learning and storage capability));
a query processing engine coupled in parallel to the plurality of neural arrays and configured to process incoming queries and to pass process queries to targeted entities and relationships representing the plurality of neural arrays (Fig. 8; Fig. 9; [0144]-[0147]: " FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships … In at least one embodiment, one or more circuits retrieve questions 902 from users of a question-answering application. … In at least one embodiment, one or more circuits detect entities 908. … In at least one embodiment, following the detection of entities 908, one or more circuits perform entity linking 912, which is further discussed in conjunction with FIG. 3. In at least one embodiment, one or more circuits perform entity linking 912 by using one or more neural networks of TimeBERT, which is further discussed in conjunction with at least FIGS. 1-5. In at least one embodiment, entity linking 912 is based, at least in part, on a time-sensitive knowledge graph, discussed further in conjunction with FIG. 8" teaches a circuit (a query processing engine) for retrieving questions (incoming queries) from a user for processing and passing the queries to detected (target) entities in a knowledge graph (neural arrays)).
Wu does not appear to explicitly teach a policy/compliance engine coupled to the plurality of neural arrays and configured to set policies for processing in the neurons and synapses of the plurality of neural arrays.
However, Dingwall et al. teaches a policy/compliance engine coupled to the plurality of neural arrays and configured to set policies for processing in the neurons and synapses of the plurality of neural arrays (Fig. 2; Fig. 5; [0056]-[0058]: "In operation 520, the receiver component 210 identifies an access permission within the query. In some embodiments, the access permission corresponds to nodes of the plurality of node clusters available to the query. For example, where a user is associated with a company, the user may have access permissions, included in the query, indicating that the user has permission to access database records associated with the company. Similarly, the access permissions may be negative permissions, preventing users from accessing nodes unless explicitly authorized. As described above, the access permission may also correspond to a computing device or a user associated with the query. … In operation 530, the modeling component 240 identifies a first portion of nodes excluded from the access permission. In some embodiments, the first portion of nodes may be identified within the data access model. The first portion of nodes may also be identified within the interconnected database or connected knowledge graph. The first portion of nodes may be identified based on access permission information contained in the node, in database records associated with the nodes, within metadata associated with the nodes, or any other suitable source. … In operation 540, the linking component 230 removes the edges of the first portion of nodes prior to execution of the query by the data access model" teaches a receiver component 210 (policy/compliance engine) coupled to a modeling component 240 modeling the nodes of the knowledge graph (neurons and synapses of the neural arrays) that determines whether the query meets the requirements for access permission and restricts or permits (sets policies) processing in the nodes for the query based on the access permissions).
Wu and Dingwall et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate a policy/compliance engine coupled to the plurality of neural arrays and configured to set policies for processing in the neurons and synapses of the plurality of neural arrays as taught by Dingwall et al. to the disclosed invention of Wu.
One of ordinary skill in the art would have been motivated to make this modification to remove nodes and edges of the knowledge graph that the query does not have permission to access because "removal or suspension of edges within the data access model may enable interaction with the interconnected database or the connected knowledge graph without modifying the underlying database or knowledge graph" (Dingwall et al. [0047]).
Regarding claim 4,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 1.
In addition, Dingwall et al. further teaches wherein the policy/compliance engine is configured to permit or restrict access to data represented in one or more parts of the knowledge graph represented in the plurality of neural arrays based on the set policies (Fig. 2; Fig. 5; [0056]-[0058]: "In operation 520, the receiver component 210 identifies an access permission within the query. In some embodiments, the access permission corresponds to nodes of the plurality of node clusters available to the query. For example, where a user is associated with a company, the user may have access permissions, included in the query, indicating that the user has permission to access database records associated with the company. Similarly, the access permissions may be negative permissions, preventing users from accessing nodes unless explicitly authorized. As described above, the access permission may also correspond to a computing device or a user associated with the query. … In operation 530, the modeling component 240 identifies a first portion of nodes excluded from the access permission. In some embodiments, the first portion of nodes may be identified within the data access model. The first portion of nodes may also be identified within the interconnected database or connected knowledge graph. The first portion of nodes may be identified based on access permission information contained in the node, in database records associated with the nodes, within metadata associated with the nodes, or any other suitable source. … In operation 540, the linking component 230 removes the edges of the first portion of nodes prior to execution of the query by the data access model" teaches that when access requirements are not met, access to nodes of the knowledge graph where access is not permissible is restricted, whereas when access requirements are met, access to nodes of the knowledge graph where access is permissible is permitted).
Wu and Dingwall et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate wherein the policy/compliance engine is configured to permit or restrict access to data represented in one or more parts of the knowledge graph represented in the plurality of neural arrays based on the set policies as taught by Dingwall et al. to the disclosed invention of Wu.
One of ordinary skill in the art would have been motivated to make this modification to remove nodes and edges of the knowledge graph that the query does not have permission to access because "removal or suspension of edges within the data access model may enable interaction with the interconnected database or the connected knowledge graph without modifying the underlying database or knowledge graph" (Dingwall et al. [0047]).
Regarding claim 5,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 1.
In addition, Wu further teaches further comprising one or more non- volatile memory storage units coupled to the plurality of neural arrays (Fig. 29; [0449]: "FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using inference and/or training logic 1115 to process the inputs. Fig. 11a; [0152]-[0153]: "inference and/or training logic 1115 may include, without limitation, code and/or data storage 1101 to store forward and/or output weight and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. … In at least one embodiment, any portion of code and/or data storage 1101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and/or code and/or data storage 1101 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) comprise non-volatile memory storage).
Regarding claim 6,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 1.
In addition, Wu further teaches further comprising: a central processing unit (CPU) coupled to the plurality of neural arrays, the query processing engine and the policy/compliance engine (Fig. 29; [0449]: "FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using inference and/or training logic 1115 to process the inputs. Fig. 11a; [0160]: "inference and/or training logic 1115 illustrated in FIG. 11A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”)" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) can be used in conjunction with a CPU); and
one or more vector processing units coupled to the CPU, the plurality of neural arrays, the query processing engine and the policy/compliance engine (Fig. 29; [0449]: "FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using inference and/or training logic 1115 to process the inputs. Fig. 11a; [0157]-[0160]: "inference and/or training logic 1115 may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”) 1110 … ALU(s) 1110 are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 1110 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALUs 1110 may be included within a processor's execution units or otherwise within a bank of ALUs accessible by a processor's execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.) … inference and/or training logic 1115 illustrated in FIG. 11A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”)" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) comprise ALUs that may be included in other processors and that inference and/or training logic 1115can be used in conjunction with a CPU. [0225]: "In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities" teaches that vector processors may be used to implement an embodiment (e.g. ALUs could be part of a vector processing unit)).
Regarding claim 7,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 1.
In addition, Wu further teaches wherein the plurality of neural arrays, the query processing engine, and the policy/compliance engine are implemented on a dedicated hardware device (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using dedicated hard-wired interconnects (e.g. dedicated hardware device)).
Regarding claim 8,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 7.
In addition, Wu further teaches wherein the plurality of neural arrays, query processing and policy/compliance engine are implemented on neuromorphic chip device (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using network-on-chip (e.g. neuromorphic chip device)).
Regarding claim 9,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 1.
In addition, Wu further teaches wherein the plurality of neural arrays, query processing and policy/compliance engine are implemented using a customizable hardware device (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using a reconfigurable interconnect architecture (e.g. customizable hardware device)).
Regarding claim 10,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 6.
In addition, Wu further teaches further comprising a three-dimensional architecture including one or more memory layers and wherein the CPU constitutes one layer of the three-dimensional architecture, wherein the CPU is interconnected to the one or more memory layers and the one or more memory layers are further interconnected to the plurality of neural arrays, which constitutes another distinct layer (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using network-on-chip (e.g. neuromorphic chip device) and using inference and/or training logic 1115 to process the inputs (e.g. the chip has a neural array layer that is interconnected to inference and/or training logic 1115). Fig. 11a; [0152]-[0153]: "inference and/or training logic 1115 may include, without limitation, code and/or data storage 1101 to store forward and/or output weight and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. … In at least one embodiment, any portion of code and/or data storage 1101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and/or code and/or data storage 1101 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) can comprise dynamic randomly addressable memory (DRAM) and non-volatile memory storage (memory layer). Fig. 11a; [0160]: "inference and/or training logic 1115 illustrated in FIG. 11A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”)" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) can be used in conjunction with a CPU (CPU layer)).
Regarding claim 11,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 10.
In addition, Wu further teaches wherein the one or more memory layers comprise a first dynamic memory layer coupled to the CPU and a second non-volatile storage array layer interconnected to the dynamic memory layer and to the plurality of neural arrays (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using network-on-chip (e.g. neuromorphic chip device) and using inference and/or training logic 1115 to process the inputs (e.g. the chip has a neural array layer that is interconnected to inference and/or training logic 1115). Fig. 11a; [0152]-[0153]: "inference and/or training logic 1115 may include, without limitation, code and/or data storage 1101 to store forward and/or output weight and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. … In at least one embodiment, any portion of code and/or data storage 1101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and/or code and/or data storage 1101 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) can comprise dynamic randomly addressable memory (dynamic memory layer) and non-volatile memory storage (non-volatile storage array layer). Fig. 11a; [0160]: "inference and/or training logic 1115 illustrated in FIG. 11A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”)" teaches that the inference and/or training logic 1115 (coupled to the neural arrays) can be used in conjunction with a CPU (CPU layer)).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0135659 A1) in view of Dingwall et al. (US 2018/0121546 A1) and further in view of Parasrampuria et al. (US 2020/0160121 A1).
Regarding claim 2,
Wu in view of Dingwall et al. teaches the integrated knowledge graph system of claim 1.
Wu in view of Dingwall et al. does not appear to explicitly teach wherein the query processing engine is configured to: locate an entity represented in the knowledge graph within the plurality of neural arrays; and pool neighbors of the entity in the knowledge graph as represented in the plurality of neural arrays.
However, Parasrampuria et al. teaches wherein the query processing engine is configured to: locate an entity represented in the knowledge graph within the plurality of neural arrays (Fig. 1; Table 2; [0050]: "Referring to the pseudocode illustrated at Table 2, based on block 1, the scoring engine 120 may take as input an identification of one or more features 206 for analysis and output a list of entities 202 that are associated with the one or more features 206. The one or more features 206 may be inputted by a user as a graph analysis configuration 103 so that the user may obtain an assessment of entities 202 with respect to the one or more features 206. The scoring engine 120 may query the graph database 104 to identify entities 202 in the graph 200 that are associated with the one or more features 206. For example, the scoring engine 120 may query the graph database 104 to identify entities 202 associated with are features 206 such as a sanction tag or crime tag, which may respectively indicate that an entity has been sanctioned or convicted of a crime. The scoring engine 120 may query other types and numbers of features 206 as well" teaches that an entity within the knowledge graph with associated features with the query may be identified (located). [0003]: "The disclosure relates to systems and methods that improve an ability to assess and analyze network effects of entities in a network modeled in a knowledge graph (hereinafter, “graph” for convenience)" teaches that the entities in a network modeled as a graph represent a knowledge graph); and
pool neighbors of the entity in the knowledge graph as represented in the plurality of neural arrays (Fig. 1; Table 2; [0051]: "Based on block 2, the scoring engine 120 may take as input the list of entities 202 identified at block 1 and output subgraphs, such as a subgraph 201 illustrated in FIG. 2A. A “subgraph” may refer to a portion of a larger graph, such as graph 200, that includes an entity 202 and its neighbor entities (immediate and/or non-immediate neighbors). Each subgraph may correspond to a respective one of the identified entities 202 and corresponding adjacency lists of the entities. The scoring engine 120 may extract, for each identified entity 202, a subgraph from the graph database 104. In some examples, each subgraph may be stored in a data mart 106 for further interrogation and analysis. Each identified entity 202 may be associated with an adjacency list. An “adjacency list” may refer to a listing of neighbor entities (whether immediate or non-immediate) of the identified entity 202, the connections among the neighbor entities to one another and to the identified entity, and corresponding types of relationships among the neighbor entities and to the identified entity" teaches that the identified (located) entity is pooled with connected neighbor entities in the knowledge graph).
Wu, Dingwall et al., and Parasrampuria et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate wherein the query processing engine is configured to: locate an entity represented in the knowledge graph within the plurality of neural arrays; and pool neighbors of the entity in the knowledge graph as represented in the plurality of neural arrays as taught by Parasrampuria et al. to the disclosed invention of Wu in view of Dingwall et al.
One of ordinary skill in the art would have been motivated to make this modification to "improve an ability to assess and analyze network effects of entities in a network modeled in a knowledge graph" (Parasrampuria et al. [0003]).
Regarding claim 3,
Wu in view of Dingwall et al. and further in view of Parasrampuria et al. teaches the integrated knowledge graph system of claim 2.
In addition, Parasrampuria et al. further teaches wherein the pooled neighbors in the plurality of neural arrays are configured to perform accelerated risk calculations (Fig. 1; Table 2; [0052]: "Based on block 3, the scoring engine 120 may take as input the subgraph list and adjacency lists from block 2 and output the association score. For example, based on block 3b, the scoring engine 120 may, for each subgraph in the subgraph list, determine a centrality metric for each entity in an adjacency list for the subgraph. Such centrality metric may be based on the closeness metric, degree metric, and betweenness metric (and corresponding weights) described with respect to FIG. 2B. The scoring engine 120 may generate a list of centralities that includes the closeness metric, degree metric, and betweenness metric for each entity in the subgraph. Based on block 3c, the scoring engine 120 may determine a weight for each of the closeness metric, degree metric, and betweenness metric for each entity to generate an aggregated centrality for each entity. Such aggregated (or weighted) centrality metric may be stored in a centrality map. Based on block 3d, the scoring engine 120 may determine the influence of an entity that is associated with one or more features 206 on neighbor entities. For example, the scoring engine 120 may access predefined and/or configurable relationship weights and the weighted centrality metric from the centrality map to generate a respective association score for each of the one or more features 206. For example, an association score may be generated that assesses a level of association to risk of a neighbor entity will be (or has been) sanctioned or will (or has) committed a crime such as a financial crime. Thus, the scoring engine 120 may determine an association score for each entity that neighbors an entity that is associated with an inputted feature 206" teaches calculating metrics for the identified entity and its neighbor entities (pooled neighbors) to determine a risk associated with the entities (perform accelerated risk calculations). Fig. 5; [0075]: "the method 500 may include accessing a request to assess a risk associated with an entity identified by an entity identifier, and providing a quantitative feature value determined for the entity (such as a neighbor of an entity that is associated with the feature(s) of interest) identified by the entity identifier" teaches assessing risk for the identified entity and the entity neighbors).
Wu, Dingwall et al., and Parasrampuria et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate wherein the pooled neighbors in the plurality of neural arrays are configured to perform accelerated risk calculations as taught by Parasrampuria et al. to the disclosed invention of Wu in view of Dingwall et al.
One of ordinary skill in the art would have been motivated to make this modification to "improve an ability to assess and analyze network effects of entities in a network modeled in a knowledge graph" (Parasrampuria et al. [0003]).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0135659 A1) in view of Wang et al. (US 20210064932 A1).
Regarding claim 12,
Wu teaches a method for mapping data onto a knowledge graph (Fig. 8; [0134]: "FIG. 8 depicts a block diagram of a process 800 of one or more circuits of one or more processors using one or more neural networks to output a time-sensitive financial knowledge graph 818 (e.g., a representation of a network of financial entities and their relationships between them). In at least one embodiment, a time-sensitive financial knowledge graph 818 comprises relationships between entities (e.g., corporations, individuals, government agencies) and events (e.g., bull market, stock market downturn, declining unemployment rates). In at least one embodiment, a financial knowledge graph 818 comprises representations of entities (e.g., objects, events, situations, concepts). In at least one embodiment, a process 800 comprises one or more neural networks to perform one or more of steps comprising: retrieving financial news 802 (e.g., financial news articles, financial opinion articles, historical stock market prices, quarterly reports, U.S. Securities and Exchange Commission) retrieved from a network (e.g., internet); … retrieving files 808 (e.g., text files, pdf documents, transcripts, scanned documents); … outputting a time-sensitive knowledge graph 818, or some combination thereof" teaches a process (method) for generating a knowledge graph from retrieved data (e.g. mapping data onto a knowledge graph)) comprising:
receiving data targeted for mapping onto the knowledge graph (Fig. 8; Fig. 9; [0134]-[0144]: "FIG. 8 depicts a block diagram of a process 800 of one or more circuits of one or more processors using one or more neural networks to output a time-sensitive financial knowledge graph 818 (e.g., a representation of a network of financial entities and their relationships between them) … retrieving financial news 802 (e.g., financial news articles, financial opinion articles, historical stock market prices, quarterly reports, U.S. Securities and Exchange Commission) retrieved from a network (e.g., internet); … retrieving files 808 (e.g., text files, pdf documents, transcripts, scanned documents); … outputting a time-sensitive knowledge graph 818 … In at least one embodiment, one or more circuits of one or more processors retrieve financial news 802 from the internet (e.g., downloading financially related news articles from financial news media outlets) … In at least one embodiment, one or more circuits retrieve files 808 (e.g., fetching electronic documents containing financial news or events from a local area network) … In at least one embodiment, one or more circuits index events and entities 818 (e.g., maps relationships between entities and events extracted from text). … once events and entities are indexed, one or more circuits output a time-sensitive knowledge graph 818 … FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships" teaches receiving news, files, and questions from users (targeted data) for indexing (mapping) onto the knowledge graph);
wherein the neural arrays contain circuits that represent neurons and synapses, each of the neurons and synapses having processing, communication, learning and storage capability (Fig. 8; Fig. 9; [0144]: "FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships" teaches a neural network circuit implementing a knowledge graph for performing a question-answering (QA) method, the knowledge graph mapping entities and relationships. Fig. 29; [0449]-[0454]: " FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908. … In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. … For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip, or with dedicated connections. … In at least one embodiment, at least one component shown or described with respect to FIG. 29 is used to implement techniques and/or functions described in connection with FIGS. 1-10. … In at least one embodiment, neuromorphic processor 2900 of FIG. 29 is utilized to implement techniques and/or functions described in connection with FIGS. 1-10" teaches a neuromorphic processor for implementing the neural network knowledge graph of Figs. 8-9 (e.g. configuring the entities and relationships within the neural arrays) that comprises a plurality of neural arrays comprising neuron and synapses interconnected for processing, inference, and training (having processing, communication, learning and storage capability)).
Wu does not appear to explicitly teach identifying elements within the data including entity-level characteristics, size, entity- type, and functional requirements; determining one or more neural arrays having capabilities suited for mapping of the identified elements; and mapping the elements onto the suited neural arrays.
However, Wang et al. teaches identifying elements within the data including entity-level characteristics, size, entity- type, and functional requirements (Fig. 2; [0038]: "Query 234 represents a natural language query. In addition, query 234 may represent any type of query or question. Data processing system 200 receives query 234 from a client device, such as client 110 in FIG. 1. Data processing system 200 utilizes chatbot 218 to identify and extract characteristics 236 of query 234. Characteristics 236 include, for example, one or more of keywords, key phrases, traits, features, properties, and the like, contained in query 234" teaches identifying characteristics (elements) within a received query (received data) including keywords, key phrases, traits, features, properties, and the like (e.g. characteristics, size, type, and requirements));
determining one or more neural arrays having capabilities suited for mapping of the identified elements (Fig. 2; [0035]-[0039]: "Chatbot 218 may be, for example, an artificial intelligence program or other type of machine learning program. … Chatbot 218 utilizes graph database 220, which comprises knowledge graph 222, to generate query results for received queries by defining base elements 224 in knowledge graph 222 that meet the needs of the received queries and generating query paths in knowledge graph 222 based on mapping characteristics of the received queries to base elements 224. … Base elements 224 are defined base query elements, which correspond to a graph query language that can be identified by graph database 220. In this example, base elements 224 include anchor element 226, jump element 228, filter element 230, and target element 232. … Anchor element 226 represents entities, such as, for example, people, places, objects, events, companies, and the like, in knowledge graph 222. … Data processing system 200 utilizes chatbot 218 to identify and extract characteristics 236 of query 234. Characteristics 236 include, for example, one or more of keywords, key phrases, traits, features, properties, and the like, contained in query 234. … After identifying and extracting characteristics 236 from query 234, chatbot 218 performs query characteristics to base element mapping 238. Query characteristics to base element mapping 238 represents a mapping between each of characteristics 236 of query 234 and a corresponding base element in base elements 224 of knowledge graph 222. Chatbot 218 utilizes query characteristics to base element mapping 238 to generate query paths 240 in knowledge graph 222. Query paths 240 represent a set of one or more possible paths in knowledge graph 222 to find the appropriate information for or answer to query 234" teaches determining knowledge graph base elements and paths (e.g. neural arrays) to map the identified characteristics (elements) to (i.e. having capable suitability)); and
mapping the elements onto the suited neural arrays (Fig. 2; [0038]-[0039]: " Query 234 represents a natural language query. In addition, query 234 may represent any type of query or question. Data processing system 200 receives query 234 from a client device, such as client 110 in FIG. 1. Data processing system 200 utilizes chatbot 218 to identify and extract characteristics 236 of query 234. Characteristics 236 include, for example, one or more of keywords, key phrases, traits, features, properties, and the like, contained in query 234. … After identifying and extracting characteristics 236 from query 234, chatbot 218 performs query characteristics to base element mapping 238. Query characteristics to base element mapping 238 represents a mapping between each of characteristics 236 of query 234 and a corresponding base element in base elements 224 of knowledge graph 222. Chatbot 218 utilizes query characteristics to base element mapping 238 to generate query paths 240 in knowledge graph 222. Query paths 240 represent a set of one or more possible paths in knowledge graph 222 to find the appropriate information for or answer to query 234" teaches mapping the identified characteristics (elements) onto suited knowledge graph base elements and paths (e.g. neural arrays)).
Wu and Wang et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate identifying elements within the data including entity-level characteristics, size, entity- type, and functional requirements; determining one or more neural arrays having capabilities suited for mapping of the identified elements; and mapping the elements onto the suited neural arrays as taught by Wang et al. to the disclosed invention of Wu.
One of ordinary skill in the art would have been motivated to make this modification to "enable more flexible user queries and provides more comprehensive and reasonable answers to those user queries" (Wang et al. [0051]).
Regarding claim 13,
Wu in view of Wang et al. teaches the method of claim 12.
In addition, Wu further teaches wherein, the neural array includes or is connected to functional block components configured to process the identified elements within the data, wherein the functional block components comprise at least one of a specialized accelerator and an application-specific functional unit (Fig. 29; [0449]: "FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using inference and/or training logic 1115 to process the inputs (functional block components configured to process the identified elements within the data). Fig. 11a; [0160]: "inference and/or training logic 1115 illustrated in FIG. 11A may be used in conjunction with an application-specific integrated circuit (“ASIC”)" teaches that the inference and/or training logic 1115 (functional block components) comprise an application-specific integrated circuit (application-specific functional unit)).
Regarding claim 14,
Wu in view of Wang et al. teaches the method of claim 12.
In addition, Wu further teaches wherein the one or more neural arrays are implemented on a dedicated hardware device (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using dedicated hard-wired interconnects (e.g. dedicated hardware device)).
Regarding claim 15,
Wu in view of Wang et al. teaches the method of claim 14.
In addition, Wu further teaches wherein the one or more neural arrays are implemented on a neuromorphic chip device (Fig. 29; [0453]: "In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip" teaches the neuromorphic processor comprising a plurality of neural arrays comprising neuron and synapses being implemented using network-on-chip (e.g. neuromorphic chip device)).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0135659 A1) in view of Dingwall et al. (US 2018/0121546 A1) and further in view of Du (US 2021/0160230 A1).
Regarding claim 16,
Wu teaches a method for querying a financial services knowledge graph comprising entity and relationship components that are configured and represented in a plurality of neural arrays comprising circuits that represent neurons and synapses, each of the neurons and synapses having processing, communication, learning and storage capability (Fig. 8; Fig. 9; [0144]: "FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships" teaches a question-answering (QA) method using a neural network circuit implementing a financial knowledge graph (financial services knowledge graph) for performing financial QA tasks (e.g. method for querying financial services knowledge graph), the knowledge graph mapping entities and relationships. Fig. 29; [0449]-[0454]: "FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2900 may receive one or more inputs from sources external to neuromorphic processor 2900. In at least one embodiment, these inputs may be transmitted to one or more neurons 2902 within neuromorphic processor 2900. In at least one embodiment, neurons 2902 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2900 comprises inference and/or training logic 1115, which further comprises one or more circuits to train one or more neural networks based, at least in part, on one or more indications of when one or more prior events occurred. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, but any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, neurons 2902 may generate outputs that may be transmitted to inputs of other instances of neurons 2902. For example, in at least one embodiment, neuron inputs 2904 and neuron outputs 2906 may be interconnected via synapses 2908. … In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapse 2908 to neurons 2902. … For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as network-on-chip, or with dedicated connections. … In at least one embodiment, at least one component shown or described with respect to FIG. 29 is used to implement techniques and/or functions described in connection with FIGS. 1-10. … In at least one embodiment, neuromorphic processor 2900 of FIG. 29 is utilized to implement techniques and/or functions described in connection with FIGS. 1-10" teaches a neuromorphic processor for implementing the neural network knowledge graph of Figs. 8-9 (e.g. configuring the entities and relationships within the neural arrays) that comprises a plurality of neural arrays comprising neuron and synapses interconnected for processing, inference, and training (having processing, communication, learning and storage capability)), the method comprising:
receiving a query for obtaining or updating information in a knowledge graph (Fig. 8; Fig. 9; [0144]: "FIG. 9 depicts a question-answering (QA) method 900 to be performed, at least in part, by one or more circuits using one or more neural networks for financial QA tasks. In at least one embodiment, QA method 900 is performed by inferencing 110, as discussed further in conjunction with FIG. 1. In at least one embodiment, a QA method 900 includes steps comprising: retrieving questions 902 from users of a QA application (e.g., virtual assistant, chatbot), segmenting text 904 (e.g., words, sentences, paragraphs), tagging positions of text segments 904, detecting entities 908, parsing dependencies 910, linking entities 912, determining candidate relationships 914, predicting answers 916, or some combination thereof. In at least one embodiment, a time-sensitive financial knowledge graph 818 may be used in one or more steps of method 900, for example, with step 912—linking entities and step 914—determining candidate relationships" teaches receiving a question (query) for obtaining information in a knowledge graph).
Wu does not appear to explicitly teach determining whether the query meets requirements for compliance by consulting a policy/compliance engine that is coupled to the plurality of neural arrays; after the determining step, when requirements for compliance are not met: restricting access to one or more components of the knowledge graph; and adjusting the query to accommodate for the restricted access; submitting the adjusted query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph.
However, Dingwall et al. teaches determining whether the query meets requirements for compliance by consulting a policy/compliance engine that is coupled to the plurality of neural arrays (Fig. 2; Fig. 5; [0056]-[0057]: "In operation 520, the receiver component 210 identifies an access permission within the query. In some embodiments, the access permission corresponds to nodes of the plurality of node clusters available to the query. For example, where a user is associated with a company, the user may have access permissions, included in the query, indicating that the user has permission to access database records associated with the company. Similarly, the access permissions may be negative permissions, preventing users from accessing nodes unless explicitly authorized. As described above, the access permission may also correspond to a computing device or a user associated with the query. … In operation 530, the modeling component 240 identifies a first portion of nodes excluded from the access permission. In some embodiments, the first portion of nodes may be identified within the data access model. The first portion of nodes may also be identified within the interconnected database or connected knowledge graph. The first portion of nodes may be identified based on access permission information contained in the node, in database records associated with the nodes, within metadata associated with the nodes, or any other suitable source" teaches a receiver component 210 (policy/compliance engine) coupled to a modeling component 240 modeling the nodes of the knowledge graph (neural arrays) that determines whether the query meets the requirements for access permission (requirements for compliance));
after the determining step, when requirements for compliance are not met: restricting access to one or more components of the knowledge graph (Fig. 2; Fig. 5; [0056]-[0058]: "In operation 520, the receiver component 210 identifies an access permission within the query. In some embodiments, the access permission corresponds to nodes of the plurality of node clusters available to the query. For example, where a user is associated with a company, the user may have access permissions, included in the query, indicating that the user has permission to access database records associated with the company. Similarly, the access permissions may be negative permissions, preventing users from accessing nodes unless explicitly authorized. As described above, the access permission may also correspond to a computing device or a user associated with the query. … In operation 530, the modeling component 240 identifies a first portion of nodes excluded from the access permission. In some embodiments, the first portion of nodes may be identified within the data access model. The first portion of nodes may also be identified within the interconnected database or connected knowledge graph. The first portion of nodes may be identified based on access permission information contained in the node, in database records associated with the nodes, within metadata associated with the nodes, or any other suitable source. … In operation 540, the linking component 230 removes the edges of the first portion of nodes prior to execution of the query by the data access model" teaches that when access requirements (requirements for compliance) are not met, access to nodes of the knowledge graph is prevented (restricted)).
Wu and Dingwall et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate determining whether the query meets requirements for compliance by consulting a policy/compliance engine that is coupled to the plurality of neural arrays; after the determining step, when requirements for compliance are not met: restricting access to one or more components of the knowledge graph as taught by Dingwall et al. to the disclosed invention of Wu.
One of ordinary skill in the art would have been motivated to make this modification to remove nodes and edges of the knowledge graph that the query does not have permission to access because "removal or suspension of edges within the data access model may enable interaction with the interconnected database or the connected knowledge graph without modifying the underlying database or knowledge graph" (Dingwall et al. [0047]).
Wu in view of Dingwall et al. does not appear to explicitly teach adjusting the query to accommodate for the restricted access; submitting the adjusted query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph.
However, Du teaches adjusting the query to accommodate for the restricted access (Fig. 3; [0121]: "At step 306, search query extracted from user input using artificial intelligence can be modified based on user accessible information (e.g., at processing module 140 and/or processing module 150). Any information accessible by a user via the user device can be used, including but not limited to, for example, user biometric data, user personal data, other people's information that the user has permission to access, existing search records, information stored in the user device, system information of the user device, information that is extracted through real-time network communication at the time when a search query is modified, or combinations thereof" teaches that the query is modified based on the restricted access (e.g. adjusted to accommodate the restricted access). [0149]: "In some embodiments, all the above input is in the machine language format. In some embodiments, the AI fusion engine uses artificial intelligent mechanisms to process a query based all or part of the available information. As disclosed herein, the AI engine may apply … a knowledge graph" teaches that the query is processed using a knowledge graph);
submitting the adjusted query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph (Fig. 3; [0121]: "At step 306, search query extracted from user input using artificial intelligence can be modified based on user accessible information (e.g., at processing module 140 and/or processing module 150). Any information accessible by a user via the user device can be used, including but not limited to, for example, user biometric data, user personal data, other people's information that the user has permission to access, existing search records, information stored in the user device, system information of the user device, information that is extracted through real-time network communication at the time when a search query is modified, or combinations thereof" teaches that the query is modified based on the restricted access (e.g. adjusted to accommodate the restricted access). Fig. 3; [0132]-[0133]: "At step 308, a modified query is communicated from user device 102 to a remote server via network communication module 120. … At step 310, a user received search results from a search using the modified query from step 308. As disclosed hereinabove, searches can be performed on the remote server or at a third party search engine" teaches that the modified (adjusted) query is sent, via network communication module 120 (input/output system), to a remote server for processing. Fig. 4; [0147]-[0149]: "steps 404 and 406 are combined in a functionality that can be called an AI fusion engine where a multitude of information is applied to refine/process a search query on the server in one method step. To achieve this purpose, the server system will have following input: query information from one or more of the processing modules on user device 102, the user information (either received from user database 114 on user device 102 or received from a local database on the server), date/time, geolocation-related information, the big data output from big data database (either as accessible online information or from a local database on the server). … In some embodiments, all the above input is in the machine language format. In some embodiments, the AI fusion engine uses artificial intelligent mechanisms to process a query based all or part of the available information. As disclosed herein, the AI engine may apply … a knowledge graph" teaches that the query is processed using an AI fusion engine applying a knowledge graph on the server (i.e. modified query is sent to a knowledge graph to obtain search results for the query)).
Wu, Dingwall et al., and Du are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate adjusting the query to accommodate for the restricted access; submitting the adjusted query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph as taught by Du to the disclosed invention of Wu in view of Dingwall et al.
One of ordinary skill in the art would have been motivated to make this modification to "refine the search results based on user information, date/time, geolocation-related info, and big data to dramatically improve the search accuracy, efficiency and convenience" (Du [0237]).
Regarding claim 17,
Wu in view of Dingwall et al. and further in view of Du teaches the method of claim 16.
In addition, Dingwall et al. further teaches further comprising after the determining step, when requirements for compliance are met, submitting the query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph (Fig. 2; Fig. 5; [0056]-[0058]: "In operation 520, the receiver component 210 identifies an access permission within the query. In some embodiments, the access permission corresponds to nodes of the plurality of node clusters available to the query. For example, where a user is associated with a company, the user may have access permissions, included in the query, indicating that the user has permission to access database records associated with the company. Similarly, the access permissions may be negative permissions, preventing users from accessing nodes unless explicitly authorized. As described above, the access permission may also correspond to a computing device or a user associated with the query. … In operation 530, the modeling component 240 identifies a first portion of nodes excluded from the access permission. In some embodiments, the first portion of nodes may be identified within the data access model. The first portion of nodes may also be identified within the interconnected database or connected knowledge graph. The first portion of nodes may be identified based on access permission information contained in the node, in database records associated with the nodes, within metadata associated with the nodes, or any other suitable source. … In operation 540, the linking component 230 removes the edges of the first portion of nodes prior to execution of the query by the data access model" teaches that when access requirements (requirements for compliance) are met, access to nodes of the knowledge graph where access is permissible is permitted to obtain information for executing the submitted query).
Wu, Dingwall et al., and Du are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate further comprising after the determining step, when requirements for compliance are met, submitting the query, via an input/output system, to the knowledge graph to obtain or update the information in the knowledge graph as taught by Dingwall et al. to the disclosed invention of Wu in view of Du.
One of ordinary skill in the art would have been motivated to make this modification to remove nodes and edges of the knowledge graph that the query does not have permission to access because "removal or suspension of edges within the data access model may enable interaction with the interconnected database or the connected knowledge graph without modifying the underlying database or knowledge graph" (Dingwall et al. [0047]).
Regarding claim 18,
Wu in view of Dingwall et al. and further in view of Du teaches the method of claim 16.
In addition, Dingwall et al. further teaches further comprising: sending results of the query including obtained or updated information to the policy compliance engine (Fig. 2; Fig. 5; [0054]-[0055]: "In operation 510, the receiver component 210 receives a query. The query containing one or more attributes, features, values, or other information to be compared to nodes within node clusters of a database. In some embodiments, the attributes, features, values, and other information may be provided by a user generating the query. The information provided by the user may be formatted, such as by selection of icons or specified query options from a menu, or free form, such as text entered via a text entry box. The one or more attributes may comprise an access permission. Access permissions may be selected by a user generating the query, based on access permissions associated with the user (e.g., databases or records the user is allowed to access), based on access permissions associated with a computing device or network in use by the user in generating the query, or any other suitably defined access permission. … In some embodiments, the query contains a confidence threshold. The confidence threshold may indicate a user selected confidence value for edges used by the data access module to source populate a result set responsive to the query. The confidence threshold may also be automatically determined or initially set. In some instances, where the data access model does not provide or locate suitable information responsive to the query, the specified confidence threshold may be modified and the query performed again" teaches a receiver component 210 (policy/compliance engine) the receives a query and determines access permissions based on features of the query including a confidence threshold, the results of the query being sent back to modify the confidence threshold of the query based on not getting suitable information (obtained information) in response to the query (i.e. the query results are sent back and the confidence threshold determined at the receiver component is modified to get a modified query)); and
determining whether the results of the query meet with compliance requirements (Fig. 2; Fig. 5; [0054]-[0055]: "In operation 510, the receiver component 210 receives a query. The query containing one or more attributes, features, values, or other information to be compared to nodes within node clusters of a database. In some embodiments, the attributes, features, values, and other information may be provided by a user generating the query. The information provided by the user may be formatted, such as by selection of icons or specified query options from a menu, or free form, such as text entered via a text entry box. The one or more attributes may comprise an access permission. Access permissions may be selected by a user generating the query, based on access permissions associated with the user (e.g., databases or records the user is allowed to access), based on access permissions associated with a computing device or network in use by the user in generating the query, or any other suitably defined access permission. … In some embodiments, the query contains a confidence threshold. The confidence threshold may indicate a user selected confidence value for edges used by the data access module to source populate a result set responsive to the query. The confidence threshold may also be automatically determined or initially set. In some instances, where the data access model does not provide or locate suitable information responsive to the query, the specified confidence threshold may be modified and the query performed again" teaches a receiver component 210 (policy/compliance engine) the receives a query and determines access permissions based on features of the query including a confidence threshold, the results of the query being sent back and modified based on if the results are suitable (i.e. based on if results meet compliance requirements)).
Wu, Dingwall et al., and Du are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate further comprising: sending results of the query including obtained or updated information to the policy compliance engine; and determining whether the results of the query meet with compliance requirements as taught by Dingwall et al. to the disclosed invention of Wu in view of Du.
One of ordinary skill in the art would have been motivated to make this modification to remove nodes and edges of the knowledge graph that the query does not have permission to access because "removal or suspension of edges within the data access model may enable interaction with the interconnected database or the connected knowledge graph without modifying the underlying database or knowledge graph" (Dingwall et al. [0047]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0135659 A1) in view of Dingwall et al. (US 2018/0121546 A1) in view of Du (US 2021/0160230 A1) and further in view of Brown et al. (US 2019/0042988 A1).
Regarding claim 19,
Wu in view of Dingwall et al. and further in view of Du teaches the method of claim 16.
Wu in view of Dingwall et al. and further in view of Du does not appear to explicitly teach wherein the input/output system submits multiple queries to the knowledge graph in parallel and the knowledge graph processes the queries in parallel.
However, Brown et al. teaches wherein the input/output system submits multiple queries to the knowledge graph in parallel and the knowledge graph processes the queries in parallel (Fig. 2A; [0098]: "There are several results of distributed data query and re-unification. For example, taking one or more queries (e.g., looking for piece of information), breaking a query into subqueries (e.g., based on a linked-data catalog and information stored in the integration engine itself), determining which query sources need to be hit, processing queries in parallel, recombining results, and producing semantically-consistent responses back" teaches that the AI agent system can submit and process multiple queries from client systems (input/output system) in parallel. [0051]: "The AI agent system 10 may generally function as an omni-channel, intelligent, proactive virtual agent with respect to the client system 12. The AI agent system 10 may receive queries, commands, or other requests from the client system 12 via a variety of communication channels. The AI agent system 10 may use the world model 16 to respond to the queries, commands, or other requests from the client system 12. For example, with queries, the AI agent system 10 can refer to or look to the world model 16 in order to obtain answers to the queries" teaches that the AI agent comprises a knowledge graph for processing the queries).
Wu, Dingwall et al., Du, and Brown et al. are analogous to the claimed invention because they are directed towards knowledge graph implementation for query processing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate wherein the input/output system submits multiple queries to the knowledge graph in parallel and the knowledge graph processes the queries in parallel as taught by Brown et al. to the disclosed invention of Wu in view of Dingwall et al. and further in view of Du.
One of ordinary skill in the art would have been motivated to make this modification to "facilitate improving a content of the response and a form of the response or both" and "improve query classification and the like ... through facilitating breaking down the query into a plurality of sub-queries based, for example, on the collected context" (Brown et al. [0215]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN J HALES whose telephone number is (571)272-0878. The examiner can normally be reached M-F 9:00am - 5:00pm.
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/BRIAN J HALES/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
