DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
The replacement fig. 2A is not accepted. With regard to the original objection to the subject matter of claim 15 (second semiconductor structure/PIC and second EIC), the replacement fig. 2A shows these features as two rectangles sitting on package substrate 222. The claim recites “a semiconductor structure electrically coupled to the package substrate and including a second semiconductor layer having electrically conductive structures therein”. The two rectangles does not show how the semiconductor structure is electrically coupled to the package substrate. It does not show a semiconductor layer having electrically conductive structures therein. It is noted that this feature is not described anywhere in the specification, or shown in the drawings. It is simply recited in a single claim (and recitation of the claim labeled “Example 33”. Because of the lack of description, it would be very difficult for one skilled in the art to understand the disclosed and claimed invention without further description and a representative figure. The associated text in the amended specification is also not accepted.
With regard to the inserted reference number 235 pointing to a “heating element” of claim 2, this would be accepted, as it is understood that heating elements could be integrated into optical components, such as those shown at 212.
With regard to the added boundary 216 and associated text, this would be understood by one skilled in the art coinciding with the subject matter of claim 9. This addition to the fig. 2B and associated text is accepted.
The objections to the drawings remain below until fully acceptable replacement sheets showing the amended figures are submitted.
The amendment to claim 3 is acknowledged. The 112(b) rejection of this claim is withdrawn.
Response to Arguments
Applicant as traversed each of the prior art rejections under both cited references, Sayyah et al., U.S. Patent Application Publication No. 2021/0124048 A1 and Kamineni et al., U.S. Patent Application Publication No. 2023/0123000 A1. Before addressing specific arguments, the Examiner would like to point out how little claim 1 describes the device structurally. It describes exactly three components, a substrate, a semiconductor layer and an optical component. It only require that the “substrate defines an air cavity” which must be in registration with the optical component.
With regard to Sayyah, Applicant argues that because it discloses substrate 154 and semiconductor layer 154 as two separate distinct components, this results in “foreclosing any reading of substrate 154 as encompassing substrate 150”. How does this argument relate to claim 1? Sayyah shows all three claimed components including the air cavity in the substrate. Applicant points out that Sayyah does not expressly label the air cavity a “air cavity”, however Applicant does not explain why one skilled in the art would not recognize the Sayyah an air cavity. There is clearly a gap or cavity in the Sayyah substrate 154. Applicant argues “An unlabeled feature appearing only in a schematic cutaway figure, with no corresponding textual description locating it in the structure the Office identified, cannot establish anticipation.” What is the legal grounds for this argument. The MPEP is clear in section 2125 that drawings can be used as prior art, so long as the invention and features that they convey can be understood by the skilled artisan, and Applicant has not presented any argument supporting that the skilled artisan would not understand the figures of Sayyah. With regard to Applicant’s argument that the Sayyah trench 153 contradicts the claim requirement that the semiconductor layer 150 is free of any opening therethrough in communication with the air cavity, the Examiner points out that the trench 153 is described on the second side of the semiconductor layer 150, and is not described as passing “therethrough”. Each claim term is given is plain and ordinary meaning, and the word “therethrough” clearly means that the semiconductor layer cannot have an opening passing therethrough, or all the way through.
With regard to Kamineni, Applicant argues that it fails to teach that the air cavity “extending in a direction from a bottom surface of the substrate toward and in registration with the optical component”. The claim says “extending in a direction from a bottom surface of the substrate toward… the optical component”. It does not say “extending from a bottom surface of the substrate”. The claim language describes a direction. It does not require the air cavity to extend to the bottom surface of the substrate. With this in mind, Applicant’s argument “Kamineni discloses no basis for treating undercut structure 2105 as originating at, or extending from, a bottom exterior surface of substrate 2017” is based on an misunderstanding of the claim language. It does not require the air cavity to “originate at” or “extend from” anything. It only requires that it extend in a specific direction.
The examiner thanks applicant for pointing out the incorrect citation number “150 in the Kamineni rejection. This has been corrected.
Applicant’s argument with respect to the Kamineni rejection of claim 3 is dependent on how “substantially perpendicularly” with respect to the bottom surface of the substrate, is defined. Again this is seen as a description of direction. The Kamineni air cavity extends in this direction (perpendicular to the bottom surface of the substrate) and perpendicular would anticipate “substantially perpendicularly” given the plain and ordinary meaning of this term. For these reasons, applicant’s arguments are not found convincing.
Claim Objections
The claims are objected to because of the following informalities:
Claim 1 recites “an” semiconductor layer instead of “a” semiconductor layer.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the heating element of claim 2 must be shown or the feature(s) canceled from the claim(s). Also, the arrangement of claim 9 must be shown having a plurality of optical components and a singular air cavity must be shown. The embodiments in the drawings show a separate air cavity for each of the plurality of optical components (for example in fig. 2A). Further, the embodiment of claim 15 having a second semiconductor structure/PIC and second EIC must be shown. Further, page 3/9 of the submitted drawings has label “FIG. 2B” on the top of the page not associated with any figure. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sayyah et al., U.S. Patent Application Publication No. 2021/0124048 A1.
With regard to claim 1, Sayyah, in fig. 3 discloses a semiconductor structure, comprising: a substrate (154); and an semiconductor layer (150) on a top surface of the substrate and including a semiconductor material and an optical component (MRR 132), wherein: the substrate defines an air cavity (unlabeled, shown in fig. 3) therein extending in a direction from a bottom surface of the substrate (154) toward and in registration with the optical component (132); and the semiconductor layer (150) is free of any opening therethrough in communication with the air cavity [0047-0052].
With regard to claim 2, Sayyah, in fig. 3 discloses that the optical component includes a heating element 134 [0047-0052].
With regard to claim 3, Sayyah, in fig. 3 discloses that the air cavity is a trench extending substantially perpendicularly with respect to the bottom surface of the substrate [0047-0052].
With regard to claim 7, Sayyah, in fig. 3 discloses that the air cavity extends to a bottom surface of the semiconductor layer [0047-0052].
With regard to claim 8, Sayyah, in fig. 3 discloses that the air cavity extends to a bottom surface of the substrate.
Claims 1-3 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamineni et al., U.S. Patent Application Publication No. 2023/0123000 A1.
With regard to claim 1, Kamineni, in fig. 21 discloses a semiconductor structure, comprising: a substrate (2107); and an semiconductor layer (unlabeled) on a top surface of the substrate (2107 and including a semiconductor material and an optical component (2109), wherein: the substrate defines an air cavity (2105) therein extending in a direction from a bottom surface of the substrate (2107) toward and in registration with the optical component (2109); and the semiconductor layer (unlabeled) is free of any opening therethrough in communication with the air cavity [0094].
With regard to claim 2, Kamineni, in fig. 21 discloses that the optical component includes a heating element (2103) [0094].
With regard to claim 3, Kamineni, in fig. 21 discloses that the air cavity (2105) is a trench extending substantially perpendicularly with respect to the bottom surface of the substrate [0094].
With regard to claim 8, Kamineni, in fig. 21 discloses that the air cavity extends to a bottom surface of the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sayyah.
With regard to claims 4-6, Sayyah all of the limitations of the parent claim, however it does not expressly disclose that the trench has sidewalls having a scalloped profile or that the sidewalls define an angle smaller than 90 degrees with respect to the bottom surface of the substrate or that the trench has a concave end surface nearest the optical component.
One skilled in the art would understand that the shape and profile or the trench walls is a matter of design choice, which can be chosen to best provide thermal management of the micro ring resonator, which are highly sensitive to thermal changes. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the Sayyah trench where the trench has sidewalls having a scalloped profile and/or the sidewalls define an angle smaller than 90 degrees with respect to the bottom surface of the substrate and/or that the trench has a concave end surface nearest the optical component, to provide thermal management of the micro ring resonator.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kamineni.
With regard to claims 4-6, Kamineni all of the limitations of the parent claim, however it does not expressly disclose that the trench has sidewalls having a scalloped profile or that the sidewalls define an angle smaller than 90 degrees with respect to the bottom surface of the substrate or that the trench has a concave end surface nearest the optical component.
One skilled in the art would understand that the shape and profile or the trench walls is a matter of design choice, which can be chosen to best provide thermal management of the micro ring resonator, which are highly sensitive to thermal changes. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the Kamineni trench where the trench has sidewalls having a scalloped profile and/or the sidewalls define an angle smaller than 90 degrees with respect to the bottom surface of the substrate and/or that the trench has a concave end surface nearest the optical component, to provide thermal management of the micro ring resonator.
With regard to claims 9-11, Kamineni all of the limitations of the parent claim, however fig. 21, showing a single component does not also show a plurality of optical components where the air cavity is in registration with the plurality of optical components, or where individual air cavities are associated with each component. Kamineni, in figs. 15-20 and 22-28 show that the PIC has several optical components (1505, 1507, 1511, 1513, 1515, etc.) and shows air cavities (1903, 2003, etc.) for isolating and thermally managing each of the components [0092-0094].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cause the air cavities to be in thermal registration with any or all of the optical components, or to provide a plurality of air cavities, each associated with a single optical component extending through the substrates, to provide thermal management to any or all of the optical components, based on the teachings of Kamineni that thermal management is needed and can be achieved with a plurality of air cavities.
Claims 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hochberg et al., U.S. Patent Application Publication No. 20160116688 A1, in view of Kamineni.
With regard to claim 12, Hochberg, in figs. 1A and 1B, discloses a semiconductor assembly including: a package substrate (160); a photonic integrated circuit (PIC) (104) on the package substrate, the PIC including: a PIC substrate; and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component (106), an electronic integrated circuit (EIC) component (102) on the package substrate, the EIC having electrically conductive structures at a bottom surface thereof , the electrically conductive structures electrically coupled to at least one of the PIC (104) and the package substrate (160) (via traces 164) [0036-0042].
Hochberg does not expressly disclose an air cavity in the PIC substrate.
The Hochberg PIC 104 includes various optical components (modulator 106, SOA 109, photodetector 110). Kamineni in figs. 15-28, teaches air cavities (1903, 2003, 2105) for isolating and thermally managing optical components [0092-0094].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate air cavities, as taught by Kamineni, into the PIC chip of Hochberg such that the PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component; and the semiconductor layer is free of any opening therethrough in communication with the air cavity, to isolate and thermally manage the optical components.
With regard to claim 13, Hochberg discloses that the PIC substrate (104) includes silicon [0037].
With regard to claim 14, the Hochberg/Kamineni modified device described in the rejection of claim 12 above discloses the air cavity extends to a bottom surface of the semiconductor layer.
With regard to claim 15, Hochberg, in figs. 1A and 1B, discloses a multi-chip package including a package substrate (160); a photonic integrated circuit (PIC) (104) on the package substrate, the PIC including: a PIC substrate; and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component (106), a fiber array unit (FAU) (120, 131, 132) coupled to the PIC (104); an electronic integrated circuit (EIC) component (102) on the package substrate, the EIC having electrically conductive structures at a bottom surface thereof , the electrically conductive structures electrically coupled to the PIC (104) and the package substrate (160) (via traces 164) [0036-0042].
Hochberg does not expressly disclose an air cavity in the PIC substrate or a second PIC and second EIC.
The Hochberg PIC 104 includes various optical components (modulator 106, SOA 109, photodetector 110). Kamineni in figs. 15-28, teaches air cavities (1903, 2003, 2105) for isolating and thermally managing optical components [0092-0094].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate air cavities, as taught by Kamineni, into the PIC chip of Hochberg such that the PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component; and the semiconductor layer is free of any opening therethrough in communication with the air cavity, to isolate and thermally manage the optical components.
Further including a second PIC and second EIC in view of the teachings of Hochberg seen as merely an obvious duplication of parts (In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP 2144.04 IV). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a second PIC/semiconductor structure electrically coupled to the package substrate and including a second semiconductor layer having electrically conductive structures therein, and a second EIC electrically coupled to the second semiconductor layer, as a duplication in parts to provide further electrooptic capabilities to the semiconductor package.
With regard to claim 16, the Hochberg/Kamineni modified device described in the rejection of claim 15 above discloses that the PIC substrate includes a crystalline material (Kamineni [0093]).
With regard to claim 17, the Hochberg/Kamineni modified device described in the rejection of claim 15 above discloses that the optical component includes a micro-ring resonator (MRR) or a Mach-Zehnder interferometer (MZI).
With regard to claims 18-20, the Hochberg/Kamineni modified device described in the rejections of claim 12 and 15 show the structure which is a result of the methods claimed in claims 18-20. Thus the methods of forming these structures would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, including providing a PIC substrate; and providing a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component; and forming an air cavity from a bottom surface of the PIC substrate and extending in a direction toward and in registration with the optical component without providing any opening through the semiconductor layer in communication with the air cavity, further including: providing a wafer including a PIC substrate stratum and a semiconductor layer stratum on the PIC substrate stratum, the semiconductor layer stratum including a plurality of optical components one of which is the optical component; from an exposed bottom surface of the PIC substrate stratum, forming a plurality of cavities one of which is the air cavity, individual ones of the cavities extending in a direction toward and in registration with one or more corresponding ones the optical components; and singulating a plurality of PICs from the wafer, the plurality of PICs including the PIC, wherein at least one of forming the air cavity and singulating includes plasma etching, as claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas A Hollweg whose telephone number is (571)270-1739. The examiner can normally be reached M-F 8-4.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kiesha R Bryant can be reached at (571)272-3606. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
