DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Examiner acknowledges Applicant’s election without traverse regarding claims 1, 4-6, 11, 14-16, 20. Examiner agrees with Applicant that these claims should be grouped, and will be examined below.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Examiner notes that the claims are viewed to not invoke 112(f) and the claims are being interpreted under a broadest reasonable interpretation.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-6, 11, 14-16, 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. With respect to Claims 1, 11, 20 the limitations identifying a kernel of a computation as a candidate for execution in a computational storage circuit; and evaluating the kernel as a candidate for execution in the computational storage circuit, the identifying comprising estimating a working set size of the kernel, and the evaluating comprising estimating an expected performance of the kernel in the computational storage circuit. This limitation is directed to an abstract idea and would fall within the “Mathematical Concept” or “Mental Process” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. This judicial exception is not integrated into a practical application. Claim 1 does not recite any additional elements and claims 11, 20 recite A system, comprising: a processing circuit; and memory, operatively connected to the processing circuit and storing instructions that, executed by the processing circuit, cause the system to perform a method, the method comprising: These limitations are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. As such Examiner does NOT view that the claims -Improve the functioning of a computer, or to any other technology or technical field
-Apply the judicial exception with, or by use of, a particular machine - see MPEP 2106.05(b)
-Effect a transformation or reduction of a particular article to a different state or thing - see MPEP 2106.05(c)
-Apply or use the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception - see MPEP 2106.05(e) and Vanda Memo The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Examiner further notes that such additional elements are viewed to be well known routine and conventional as evidenced by ChoFleming (US 2022/0222177 A1) Memon (US 2020/0257553 A1) ChoFleming (US 2023/0367640 A1) Malaya (US 2019/0391850 A1) Kachare (US 2020/0201692 A1) Considering the claim as a whole, one of ordinary skill in the art would not know the practical application of the present invention since the claims do not apply or use the judicial exception in some meaningful way. As currently claimed, Examiner views that the additional elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, because the claims fails to recite clearly how the judicial exception is applied in a manner that does not monopolize the exception and does not impose a meaningful limitation describing what problem is being remedied or solved. Dependent claims 4-6, 14-16 when analyzed as a whole are held to be patent ineligible under 35 U.S.C. 101 because the additional recited limitation(s) fail(s) to establish that the claim(s) is/are not directed to an abstract idea, as detailed below: there is no additional element(s) in the dependent claims that adds a meaningful limitation to the abstract idea to make the claim significantly more than the judicial exception (abstract idea). Claims 4-6, 14-16 further limit the abstract idea with an abstract idea and thus the claims are still directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 11, 14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ChoFleming (US 2022/0222177 A1).Herein ChoFleming (US 2022/0222177 A1) will be referred to as ChoFleming'177
With respect to Claim 1 ChoFleming’177 teaches A method, comprising: identifying a kernel of a computation as a candidate for execution in a computational storage circuit (See Fig 8 and Para[0010] FIG. 8 is a table including mappings of example kernels to example target hardware and example memory objects to be accessed during execution of the kernels.) and identifying comprising estimating a working set size of the kernel (See Para[0058] To account for this, the accelerator cache model 236 can employ an algorithm that removes some memory access traffic by tracking a set of recent memory accesses equal in size to an amount of in-accelerator storage (e.g., registers). The reduced memory stream can be used to drive the accelerator cache model 236 to provide high fidelity modeling of accelerator cache behavior.), and the evaluating comprising estimating an expected performance of the kernel in the computational storage circuit. (See Para[0058] In some examples, the accelerator cache model 236 models the performance of the memory hierarchy available to the accelerator on the target electronic system 217. The accelerator cache model 236 can model the cache memories (e.g., L1, L2, L3, last level cache (LLC), etc.) and can additionally model one or more levels of system memory (that is, one or more levels of memory below the lowest level of cache memory in the memory hierarchy, such as a first level of (embedded or non-embedded) DRAM).) However ChoFleming’177 is silent to the language of evaluating the kernel as a candidate for execution in the computational storage circuit Nevertheless it would have been obvious to one of ordinary skill in the art evaluating the kernel as a candidate for execution in the computational storage circuit because ChoFleming’177 teaches a table including mappings of example kernels to example target hardware and example memory objects to be accessed during execution of the kernels. (See Para[0010] and Fig. 8). The preference as a candidate would depend on the an intended purpose and ChoFleming’177 teaches the consequence of such kernels with varying target hardware and memory objects. With respect to Claim 4 ChoFleming’177 teaches The method of claim 1, wherein the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the working set size of the kernel is less than a size of a buffer of the computational storage circuit. (See Para[0123]) With respect to Claim 11 ChoFleming’177 teaches A system, comprising: (See Fig 1) a processing circuit; and (See Fig 1) memory, operatively connected to the processing circuit and storing instructions that, executed by the processing circuit, cause the system to perform a method, the method comprising: (See Fig 1) identifying a kernel of a computation as a candidate for execution in a computational storage circuit; and (See Fig 8 and Para[0010] FIG. 8 is a table including mappings of example kernels to example target hardware and example memory objects to be accessed during execution of the kernels.) identifying comprising estimating a working set size of the kernel, (See Para[0058] To account for this, the accelerator cache model 236 can employ an algorithm that removes some memory access traffic by tracking a set of recent memory accesses equal in size to an amount of in-accelerator storage (e.g., registers). The reduced memory stream can be used to drive the accelerator cache model 236 to provide high fidelity modeling of accelerator cache behavior.), and the evaluating comprising estimating an expected performance of the kernel in the computational storage circuit (See Para[0058] In some examples, the accelerator cache model 236 models the performance of the memory hierarchy available to the accelerator on the target electronic system 217. The accelerator cache model 236 can model the cache memories (e.g., L1, L2, L3, last level cache (LLC), etc.) and can additionally model one or more levels of system memory (that is, one or more levels of memory below the lowest level of cache memory in the memory hierarchy, such as a first level of (embedded or non-embedded) DRAM).). However ChoFleming’177 is silent to the language of evaluating the kernel as a candidate for execution in the computational storage circuit Nevertheless it would have been obvious to one of ordinary skill in the art evaluating the kernel as a candidate for execution in the computational storage circuit because ChoFleming’177 teaches a table including mappings of example kernels to example target hardware and example memory objects to be accessed during execution of the kernels. (See Para[0010] and Fig. 8). The preference as a candidate would depend on the an intended purpose and ChoFleming’177 teaches the consequence of such kernels with varying target hardware and memory objects. With respect to Claim 14 ChoFleming’177 teaches The system of claim 11, wherein the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the working set size of the kernel is less than a size of a buffer of the computational storage circuit. (See Para[0123]) With respect to Claim 20 ChoFleming’177 teaches A system, comprising: (See Fig 1) means for processing; and (See Fig 1) memory, operatively connected to the means for processing and storing instructions that, executed by the means for processing, cause the system to perform a method, the method comprising: (See Fig 1) identifying a kernel of a computation as a candidate for execution in a computational storage circuit; and (See Fig 8 and Para[0010] FIG. 8 is a table including mappings of example kernels to example target hardware and example memory objects to be accessed during execution of the kernels.) the identifying comprising estimating a working set size of the kernel(See Para[0058] To account for this, the accelerator cache model 236 can employ an algorithm that removes some memory access traffic by tracking a set of recent memory accesses equal in size to an amount of in-accelerator storage (e.g., registers). The reduced memory stream can be used to drive the accelerator cache model 236 to provide high fidelity modeling of accelerator cache behavior.), and the evaluating comprising estimating an expected performance of the kernel in the computational storage circuit. (See Para[0058] In some examples, the accelerator cache model 236 models the performance of the memory hierarchy available to the accelerator on the target electronic system 217. The accelerator cache model 236 can model the cache memories (e.g., L1, L2, L3, last level cache (LLC), etc.) and can additionally model one or more levels of system memory (that is, one or more levels of memory below the lowest level of cache memory in the memory hierarchy, such as a first level of (embedded or non-embedded) DRAM).) However ChoFleming’177 is silent to the language of evaluating the kernel as a candidate for execution in the computational storage circuit Nevertheless it would have been obvious to one of ordinary skill in the art evaluating the kernel as a candidate for execution in the computational storage circuit because ChoFleming’177 teaches a table including mappings of example kernels to example target hardware and example memory objects to be accessed during execution of the kernels. (See Para[0010] and Fig. 8). The preference as a candidate would depend on the an intended purpose and ChoFleming’177 teaches the consequence of such kernels with varying target hardware and memory objects.
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Claim(s) 5, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over ChoFleming (US 2022/0222177 A1) further in view of Memon (US 2020/0257553 A1).
With respect to Claim 5 ChoFleming’177 is silent to the language of The method of claim 1, wherein the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel within the computation. Nevertheless Memon teaches wherein the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel within the computation. (See Para[0042]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify ChoFleming’177 determine that the kernel is an independent kernel within the computation such as that of Memon. One of ordinary skill would have been motivated to modify ChoFleming’177, because a single kernel can be decomposed into separate sub-sections, these sub-sections could be assigned to different co-processors for either parallel (if no data dependency) or serial (with data dependency) computation, where each co-processor is chosen to increase the overall efficiency (such as minimum completion time) of the execution of the kernel.
With respect to Claim 15 ChoFleming’177 is silent to the language of The system of claim 11, wherein the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel within the computation. Nevertheless Memon teaches wherein the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel within the computation. (See Para[0042]) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify ChoFleming’177 determine that the kernel is an independent kernel within the computation such as that of Memon. One of ordinary skill would have been motivated to modify ChoFleming’177, because a single kernel can be decomposed into separate sub-sections, these sub-sections could be assigned to different co-processors for either parallel (if no data dependency) or serial (with data dependency) computation, where each co-processor is chosen to increase the overall efficiency (such as minimum completion time) of the execution of the kernel.
Claim(s) 6, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over ChoFleming (US 2022/0222177 A1) further in view of Memon (US 2020/0257553 A1) and ChoFleming (US 2023/0367640 A1).
Herein ChoFleming (US 2023/0367640 A1) will be referred to as ChoFleming’640 With respect to Claim 6 ChoFleming’177 is silent to the language of The method of claim 1, wherein: the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel; and the determining that the kernel is an independent kernel comprises generating a dynamic call graph for the computation. Nevertheless Memon teaches the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel; and (See Para[0042]) However Memon is silent to the language of the determining that the kernel is an independent kernel comprises generating a dynamic call graph for the computation. Nevertheless ChoFleming’640 teaches the determining that the kernel is an independent kernel comprises generating a dynamic call graph for the computation. (See Para[0019] ] In some embodiments, the offload advisor uses the following approach to account for the sharing of data structures by multiple loops to improve the offload strategy. In a call tree (or call graph) of a program (in which an individual node has an associated code object), beginning with its leaf nodes, the offloading of a code object associated with a parent node is analyzed for possible offloading with and without the code objects associated with its children nodes. To analyze the offloading of a combined loop nest, the memory footprint of each loop (e.g., the amount of memory used and which data structures are used by the loop) is used to determine data sharing patterns and modify the estimated accelerated time for the loops according to the increased or decreased memory use. The loop nest offload is compared to the best offload strategies of its child loops. The better of offloading the whole loop nest (parent loop plus child loops), or not offloading the parent and following the best offload strategies for the children loops is selected and the process proceeds up to the root of the call tree.) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify ChoFleming’177 determine that the kernel is an independent kernel within the computation such as that of Memon. One of ordinary skill would have been motivated to modify ChoFleming’177, because a single kernel can be decomposed into separate sub-sections, these sub-sections could be assigned to different co-processors for either parallel (if no data dependency) or serial (with data dependency) computation, where each co-processor is chosen to increase the overall efficiency (such as minimum completion time) of the execution of the kernel. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify ChoFleming’177 generating a dynamic call graph for the computation such as that of ChoFleming’640. One of ordinary skill would have been motivated to modify ChoFleming’177, because generating a dynamic call graph would improve memory usage and efficiency.
With respect to Claim 16 ChoFleming’177 is silent to the language of The system of claim 11, wherein: the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel; and the determining that the kernel is an independent kernel comprises generating a dynamic call graph for the computation. Nevertheless Memon teaches the identifying of the kernel as a candidate for execution in the computational storage circuit comprises determining that the kernel is an independent kernel; and (See Para[0042]) However Memon is silent to the language of the determining that the kernel is an independent kernel comprises generating a dynamic call graph for the computation. Nevertheless ChoFleming’640 teaches the determining that the kernel is an independent kernel comprises generating a dynamic call graph for the computation. (See Para[0019] ] In some embodiments, the offload advisor uses the following approach to account for the sharing of data structures by multiple loops to improve the offload strategy. In a call tree (or call graph) of a program (in which an individual node has an associated code object), beginning with its leaf nodes, the offloading of a code object associated with a parent node is analyzed for possible offloading with and without the code objects associated with its children nodes. To analyze the offloading of a combined loop nest, the memory footprint of each loop (e.g., the amount of memory used and which data structures are used by the loop) is used to determine data sharing patterns and modify the estimated accelerated time for the loops according to the increased or decreased memory use. The loop nest offload is compared to the best offload strategies of its child loops. The better of offloading the whole loop nest (parent loop plus child loops), or not offloading the parent and following the best offload strategies for the children loops is selected and the process proceeds up to the root of the call tree.) It would have been obvious to one of ordinary skill in the art before the effective filing date to modify ChoFleming’177 determine that the kernel is an independent kernel within the computation such as that of Memon. One of ordinary skill would have been motivated to modify ChoFleming’177, because a single kernel can be decomposed into separate sub-sections, these sub-sections could be assigned to different co-processors for either parallel (if no data dependency) or serial (with data dependency) computation, where each co-processor is chosen to increase the overall efficiency (such as minimum completion time) of the execution of the kernel. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify ChoFleming’177 generating a dynamic call graph for the computation such as that of ChoFleming’640. One of ordinary skill would have been motivated to modify ChoFleming’177, because generating a dynamic call graph would improve memory usage and efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Malaya (US 2019/0391850 A1) teaches systems for opportunistic load balancing in deep neural networks (DNNs) using metadata. Representative computational costs are captured, obtained or determined for a given architectural, functional or computational aspect of a DNN system. Kachare (US 2020/0201692 A1) teaches a system including a host device; a storage device including an embedded processor; and a bridge kernel device including a bridge kernel hardware and a bridge kernel firmware, wherein the bridge kernel device is configured to receive a plurality of arguments from the host device and transfer the plurality of arguments to the embedded processor for data processing
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YOSHIHISA . ISHIZUKA
Examiner
Art Unit 2857
/YOSHIHISA ISHIZUKA/Primary Examiner, Art Unit 2857
Prosecution Insights