DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA and is in response to the amendments filed on 02/11/2026. Claims 1-20 are pending.
In the interest of facilitating compact prosecution the examiner invites the applicant to contact the examiner to discuss ways to better focus the instant application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Regarding claims 1-20, under Step 2A claims 1-11 recite a judicial exception (abstract idea) that is not integrated into a practical application and does not provide significantly more.
Under Step 2A (prong 1), and taking claim 1 as representative, claim 1 recites a “ activate a number of idle compute circuits to process the data, wherein no more than a threshold number of the idle compute circuits are permitted to be activated simultaneously (mental process of a person making a judgement on how many compute circuits to activate);
These limitations, as drafted in such high level of generality, are processes that, under its broadest reasonable interpretation, covers performance of the limitations in the human mind with aid of a computer (see: MPEP 2106.04(a)(2), subsection III.c). For example, as mapped by the examiner above, the various limitations in the context of this claim encompasses a person performing the limitations with the aid of a generic computer. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind, then it falls with the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Step 2A (prong 2) and Step 2B claim 1 does contain additional elements of:
“An apparatus comprising: a plurality of compute circuits, each comprising circuitry configured to process a work block; and circuitry configured to receive data to be assigned to one or more compute circuits of the plurality of compute circuits for processing.”
However, when evaluated either individually or in combination, they do not integrate the above-mentioned abstract idea into practical application nor do they amount to significantly more than the exception itself. In particular the additional element of “an apparatus comprising: a plurality of compute circuits, each comprising circuitry configured to process a work block; and circuitry configured to” cited above are recited in high level of generality (i.e. as a generic computer in a generic computing environment) such that, either alone or in combination, it amounts to nothing more than generally linking the use of a judicial exception to a particular technological environment (MPEP 2106.05(h)). The additional elements of “receive data for assignment to one or more compute circuits of the plurality of compute circuits for processing” are recited, in high level of generality (i.e. extra-solution activity of data gathering). A such, either alone or in combination, they amount to nothing more than generally linking the use of a judicial exception/abstract idea to a particular technological environment and insignificant extra solution activity and thus does not integrate the judicial exception/abstract idea into a practical application nor do they provide significantly more than the abstract idea itself - see MPEP 2106.05(g). Therefore, the judicial exception/abstract idea, identified above, is not integrated into a practical application nor does the claim include any additional elements that are sufficient to amount to significantly more than the judicial exception/abstract idea. As such, the claim is not patent eligible.
Claims 2-7 are also not patent eligible because they recite more complexities descriptive of the abstract idea itself, and at least inherit the abstract idea of claim 1. As such, claims 2-7 are understood to recite an abstract idea under step 2A (prong 1) for at least similar reasons as discussed above. In particular, claims 2-6 merely provided recitations, in high level of generality, on some additional mental process considerations that a person is able perform with the aid of a generic computer (i.e. for claims 2-5: additional mental consideration for judging/determining threshold number of idle compute circuits; for claim 6: mental evaluation that involves a comparison using threshold number of idle compute circuits). Under step 2A (prong 2) and 2B, Claims 3-5 recites additional limitations of “receiving an indication…” And claim 7 recites additional limitations of “each of the plurality of compute circuits is a single instruction multiple data (SIMD)circuit comprising a plurality of lanes of execution; and each work block is a wavefront comprising a plurality of work items”. The additional elements of claims 3-5 are recited, in high level of generality (i.e. extra-solution activity of data gathering). The additional elements of claim 7 are recited in high level of generality (i.e. as a type of generic computer) such that they amount to nothing more than the mere instructions to implement or apply the abstract idea on generic computing hardware (or, merely uses a computer as a tool to perform an abstract idea), see details in MPEP 2106.05(f). A such, either alone or in combination, they amount to nothing more than generally linking the use of a judicial exception/abstract idea to a particular technological environment and insignificant extra solution activity and thus does not integrate the judicial exception/abstract idea into a practical application nor do they provide significantly more than the abstract idea itself - see MPEP 2106.05(g). Therefore, the judicial exception/abstract idea, identified above, is not integrated into a practical application nor do the claims include any additional elements that are sufficient to amount to significantly more than the judicial exception/abstract idea. As such, these dependent claims are not patent eligible.
Claims 8-14 are method versions of system claims 1-7 and they recite at least substantially similar concepts and elements as recited in claims 1-7 such that similar step 2A (prong 1) analysis of the claims would be readily apparent to one of ordinary skill in the art. Under step 2A (prong 2) and 2B these claims recites additional elements of “a scheduler”. These further additional elements are recited in high level of generality (i.e. as a generic computer component) such that they amount to nothing more than the mere instructions to implement or apply the abstract idea on generic computing hardware (or, merely uses a computer as a tool to perform an abstract idea), see details in MPEP 2106.05(f). Therefore, the abstract idea, identified above, is not integrated into a practical application in any of the claims, nor do the claims include any additional elements that are sufficient to amount to significantly more than the judicial exception. Accordingly, these dependent claims are not patent eligible.
Claims 15-20 are reworded system versions of system claims 1-7 and they recite at least substantially similar concepts and elements as recited in claims 1-7 such that similar step 2A (prong 1) analysis of the claims would be readily apparent to one of ordinary skill in the art. Under step 2A (prong 2) and 2B, these claims recite additional elements of an “a computing system comprising: a processor; a plurality of chiplets, each comprising one or more compute circuits comprising circuitry configured to process a work block; and a scheduler comprising circuitry”. These further additional elements are recited in high level of generality (i.e. as a type of generic computer) such that they amount to nothing more than the mere instructions to implement or apply the abstract idea on generic computing hardware (or, merely uses a computer as a tool to perform an abstract idea), see details in MPEP 2106.05(f). Therefore, the abstract idea, identified above, is not integrated into a practical application in any of the claims, nor do the claims include any additional elements that are sufficient to amount to significantly more than the judicial exception. Accordingly, these dependent claims are not patent eligible.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
The following claim languages are not clear and indefinite:
As per claim 1, 8 and 15 it is not clear what the “data” can be, since in computer science, any software can be considered to be data.
The dependent claims do not cure the 112(b) issues of their respective parent claims. Therefore, they are rejected for the same reasons as those presented for their respective parent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-11, 13, 15-18 and 20 are rejected under 103 as being unpatentable over Tajima (U.S. Pat. 8689229) in view of Elnozahy et al (U.S. Pub. 2011/0154348).
Tajima and Elnozahy has been previously cited.
As per claim 1 Tajima teaches the invention substantially as claimed including an apparatus comprising: a plurality of compute circuits, each comprising circuitry configured to process data (Fig. 2, col 5 lines 33-60 CPU resource provider provides a plurality of executing nodes for execution of different jobs, jobs are data, i.e. code, to be processed); and circuitry configured to:
receive data to be assigned to one or more compute circuits of the plurality of compute circuits for processing (col 7 lines 38-43, col 8 43-63 jobs request arrives at the CPU resource provider and they are queued for execution);
activate a number of idle compute circuits to process the data, wherein no more than a threshold number of the idle compute circuits are activated simultaneously (col 8 lines 41-67, col 9 lines 1-48, col 10 lines 4-29: a maximum number of available nodes Navailable is determined, and Nrequired number of the available nodes can be immediately assigned to a job; col 9 lines 1-48, col 10 lines 4-29 only Nrequired number of nodes out of the Navailable number of nodes are assigned to a job); and
Tajima does not explicitly teach that the threshold number is a permission that indicated a number of idle compute circuits that are permitted to be activated.
However, Elnozahy teaches that the threshold number is a permission that indicated a number of idle compute circuits that are permitted to be activated ([0030], [0036], [0037] of jobs/tasks that are waiting to be executed, only a number, no more than a number of licensed cores, can be concurrently assigned on idle cores).
It would have been obvious to one with ordinary skill in the prior to the effective filling date of the invention to combine the teachings of Tajima and Elnozahy because both are directed towards allocation of distributed processing resources for job execution. One with ordinary skill in the art would be motivated to incorporate the teachings of Elnozahy into that of Tajima because Elnozahy further improves power efficiency towards allocation of distributed processing resources for job execution ([0002]-[0004]).
As per claim 2 Tajima teaches wherein the circuitry is further configured to determine the threshold number of idle compute circuits permitted to be simultaneously activated based on a comparison of the number of idle compute circuits to a number of the plurality of compute circuits (col 8 line 65 – col 9 line 11, 34-52 how many nodes that are available to be used by a job is determined by a number of free nodes and number of nodes that are used by different jobs currently).
As per claim 3 Tajima teaches wherein the circuitry is further configured to: receive an indication of a number of compute circuits that have not begun execution of a previously assigned work block; and determine the threshold number of idle compute circuits permitted to be simultaneously activated based at least in part on the indication (col 8 lines 42-63 Nrequired is updated for jobs that are queued, the jobs that are queued are jobs that have been assigned to processing nodes for execution but have not begun execution yet).
As per claim 4 Tajima teaches wherein the circuitry is further configured to: receive an indication of a number of compute circuits that have completed execution of previously assigned data; and determine the threshold number of idle compute circuits permitted to be simultaneously activated based at least in part on the indication (col 8 lines 30-63 when a job ends it would trigger Nrequired to be updated).
As per claim 6 Tajima teaches wherein the circuitry is further configured to compare the threshold number of idle compute circuits that can be simultaneously activated to the number of idle compute circuits, in response to expiration of a period of time since a most recent scheduling window (col 7 lines 45-50 queue reevaluation process can be done at a preset time period).
As per claims 8-11 and 13, they are reworded method versions of claims 1-4 and 6. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 1-4 and 6, respectively. In particular, for claim 8 Tajima teaches a scheduler that performs the steps of the claim (col 7 lines 36-38).
As per claims 15-18 and 20, they are reworded system versions of claims 1-4 and 6. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claims 1-4 and 6, respectively. In particular, Tajima as modified by Elnozahy teaches plurality chiplets (Tajima col 5 lines 33-56, Elnozahy [0030]) and a scheduler that performs the steps of the claim (Tajima col 7 lines 36-38).
Claims 5, 12 and 19 are rejected under 103 as being unpatentable over Tajima (U.S. Pat. 8689229) in view of Elnozahy et al (U.S. Pub. 2011/0154348) and in further view of Allen-ware et al (U.S. Pub. 2016/0132096).
Tajima, Elnozahy and Allen-ware has been previously cited.
As per claim 5 Tajima as modified by Elnozahy does not explicitly teach wherein the circuitry is further configured to reduce the threshold number of idle compute circuits that can be simultaneously activated, in response to receiving an indication of a non-zero voltage droop measurement.
However Allen-ware teaches wherein the circuitry is further configured to reduce the threshold number of idle compute circuits that can be simultaneously activated, in response to receiving an indication of a non-zero voltage droop measurement (abstract, [0021]-[0023] only a threshold number of processors can exit idle state in order to avoid any positive voltage droop).
It would have been obvious to one with ordinary skill in the prior to the effective filling date of the invention to combine the teachings of Allen-ware and Tajima as modified by Elnozahy because both are directed towards allocation of idle processing resources. One with ordinary skill in the art would be motivated to incorporate the teachings of Allen-ware into that of Tajima as modified by Elnozahy because Allen-ware further improves performance of allocation of idle processing resources ([0005]-[0007]).
As per claims 12 and 19, they are reworded method and system versions of claim 5. Therefore, they are rejected for the same reasons, mutatis mutandis, as those presented for claim 5.
Claims 7 and 14 are rejected under 103 as being unpatentable over Tajima (U.S. Pat. 8689229) in view of Elnozahy et al (U.S. Pub. 2011/0154348) and in further view of Orr et al (U.S. Pat. 10360652).
Tajima, Elnozahy and Orr has been previously cited.
As per claim 7 Tajima as modified by Elnozahy does not explicitly teach wherein: each of the plurality of compute circuits is a single instruction multiple data (SIMD)circuit comprising a plurality of lanes of execution; and the data comprises one or more work blocks, each work block comprising a plurality of work items.
However Orr teaches wherein: each of the plurality of compute circuits is a single instruction multiple data (SIMD) circuit comprising a plurality of lanes of execution; and the data comprises one or more work blocks, each work block comprising a plurality of work items (col 4 lines 1-16, 24-44).
It would have been obvious to one with ordinary skill in the prior to the effective filling date of the invention to combine the teachings of Orr and Tajima as modified by Elnozahy because both are directed towards efficient allocation of available processing resources. One with ordinary skill in the art would be motivated to incorporate the teachings of Orr into that of Tajima as modified by Elnozahy because Orr further improves efficiency and flexibility of allocation of available processing resources (col 1 lines 19-23).
As per claim 14, it is a reworded system version of claim 7. Therefore, it is rejected for the same reasons, mutatis mutandis, as those presented for claim 7.
Response to Arguments
Applicant’s arguments Applicant's arguments filed on 02/11/2026 have been considered but they are not persuasive.
Response for arguments for 35 U.S.C. 101 issues:
With regard to applicant’s argument for claim 1 that:
"Humans cannot “activate idle compute circuits,” let alone regulate their simultaneous activation”.
The examiner respectfully disagrees.
As MPEP 2106.04(a)(2).III clearly states:
Nor do the courts distinguish between claims that recite mental processes performed by humans and claims that recite mental processes performed on a computer. As the Federal Circuit has explained, “[c]ourts have examined claims that required the use of a computer and still found that the underlying, patent-ineligible invention could be performed via pen and paper or in a person’s mind.” Versata Dev. Group v. SAP Am., Inc., 793 F.3d 1306, 1335, 115 USPQ2d 1681, 1702 (Fed. Cir. 2015). See also Intellectual Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1318, 120 USPQ2d 1353, 1360 (Fed. Cir. 2016) (‘‘[W]ith the exception of generic computer-implemented steps, there is nothing in the claims themselves that foreclose them from being performed by a human, mentally or with pen and paper.’’); Mortgage Grader, Inc. v. First Choice Loan Servs. Inc., 811 F.3d 1314, 1324, 117 USPQ2d 1693, 1699 (Fed. Cir. 2016) (holding that computer-implemented method for "anonymous loan shopping" was an abstract idea because it could be "performed by humans without a computer").
This means that a mental process that is performed on a computer is still a mental process. In particular, a human could mentally decide to activate X number of idle compute circuits of a computer, and send command to the computer to activate the X number of idle compute circuits at once. As such, human can, in fact, activate idle compute circuits and regulate simultaneous activation.
With regard to applicant’s argument for claim 1 that:
" In addition, claim 1 improves computer operation. Limiting the number of compute circuits that may be activated at the same time directly affects power behavior, stability, and hardware operation of a processing device. This is an example of an improvement to the functioning of a computer itself, not an abstract idea implemented on a computer.”
The examiner respectfully disagrees.
As MPEP 2106.05(a) clearly states:
If it is asserted that the invention improves upon conventional functioning of a computer, or upon conventional technology or technological processes, a technical explanation as to how to implement the invention should be present in the specification. That is, the disclosure must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement. The specification need not explicitly set forth the improvement, but it must describe the invention such that the improvement would be apparent to one of ordinary skill in the art. Conversely, if the specification explicitly sets forth an improvement but in a conclusory manner (i.e., a bare assertion of an improvement without the detail necessary to be apparent to a person of ordinary skill in the art), the examiner should not determine the claim improves technology.
This means that the disclosure must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement. Merely setting forth an improvement in a conclusory manner, as the applicant has done (see applicant’s argument cited above), does not provide such sufficient details to the examiner. As such, the above cited argument is not persuasive.
Response for arguments for 35 U.S.C. 103 issues:
With regard to applicant’s argument for claim 1 that:
" Tajima describes receiving jobs, determining how many execution nodes should be allocated to a job, and assigning those jobs to available nodes (see, e.g., Tajima, Abstract; col. 3, lines 10-35; col. 6, lines 20-45). Tajima repeatedly uses the term "available nodes" to mean nodes that are not currently assigned to another job, not nodes that are inactive or powered down (see, e.g., col. 4, lines 5-20; col. 7, lines 1-15). There is no disclosure in Tajima of nodes being in an idle hardware state awaiting activation, nor of transitioning nodes from an idle or inactive state to an active state. Further, Tajima's scheduling logic determines how many nodes a job should be assigned based on job requirements and system availability (e.g., col. 5, lines 30-55). Tajima does not disclose any mechanism that limits how many idle compute circuits may be activated simultaneously, nor does it describe activation events at all. Assignment of work to an already-available node is not equivalent to activating an idle compute circuit. (emphasis added by examiner).
The examiner respectfully disagrees.
Under Broadest Reasonable Interpretation (BRI), the claims do not restrict the “idle-ness” of nodes to mean that the nodes are nodes that are “powered down”, since the claims does not state that the nodes are “powered down”, instead the claims only stated that the nodes are “idle”. Under BRI, an idle node not have to be “power down” because it can be considered to be idle as long as it is not actively being used, or that it is free to be used, in another words that it is available. This is exactly what Tajima teaches as the examiner has previously pointed out in his mapping of col 9 lines1-48: Navailable corresponds to free nodes. As such, the “available nodes” of Tajima are idle nodes. When the available or free nodes of Tajima are assigned to a job and used for execution of the job (Tajima col 9 lines 9-25), the free nodes are, in effect, “transitioned from an idle or inactive state to an active state”. The selection and utilization of previously available/free nodes for immediate execution of a job is, in itself and also contains therein, “activation events” for the available/free nodes of Tajima. Furthermore, as seen in col 9 lines 1-48 of Tajima only Nrequired of Navailable nodes are assigned immediately to a particular job. So Tajima, in fact, also teaches a “mechanism that limits how many idle compute circuits may be activated simultaneously”. As such, Tajima teaches every aspects (as emphasized by the examiner above) of applicant’s arguments cited above.
With regard to applicant’s argument for claim 1 that:
" Elnozahy describes activating additional processor cores under certain conditions, such as when workload demand increases or when licensed cores are available (see, e.g., Elnozahy, Abstract; paras. [0008]-[0015]; paras. [0035]-[0045]). However, Elnozahy's disclosure focuses on whether additional cores should be enabled and on managing voltage/frequency operating points (e.g., paras. [0020]-[0030]). Elnozahy does not disclose enforcing a numerical cap on the number of idle cores that may be activated simultaneously, nor does it recognize simultaneous activation as a control problem. (emphasis added by examiner).
The examiner respectfully disagrees.
As the examiner has previously presented, paragraph [0037] of Elnozahy teaches that user can not assign tasks concurrently on more than the number of licensed cores. The number of licensed cores is a “numerical cap” on the number of cores that may be concurrently activated. Elnozahy explicitly controls the number of idle cores that can be used by limiting that number to the number of licensed cores ([0036], [0037]). As such, Elnozahy explicitly teaches what the applicant has alleged that it does not teach, in emphasized portion of applicants arguments cited above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BING ZHAO whose telephone number is (571)270-1745. The examiner can normally be reached 9:30am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached on (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BING ZHAO/Primary Examiner, Art Unit 2151