Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites columns and line numbers in the references as applied to the claims below for convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that in preparing responses, the applicant fully consider the references cited in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 10-15 recite the limitations "a thread scheduler to determine an optimal processing engine ..." (claim 10) and "a power manager to determine current power constraints ..." (claim 11), which are being interpreted under 35 U.S.C. 112(f) because they meet the three-prong test set forth in MPEP § 2181(I):
(A) The claims use the terms "thread scheduler" and "power manager" in a manner that invokes 35 U.S.C. 112(f). Although the terms do not use the word "means," they are non-structural terms that name the function performed (scheduling threads; managing power) rather than a specific structure, and are therefore analogous to a generic placeholder term such as "mechanism," "module," or "unit for" performing a function. See Williamson v. Citrix Online, LLC, 792 F.3d 1339 (Fed. Cir. 2015) (a nonce term coupled with functional language, without more, can invoke § 112(f) even without the word "means"). Neither "thread scheduler" nor "power manager" is understood in the art, standing alone, to denote a specific structure for performing the recited functions; each is understood by its function.
(B) The terms "thread scheduler" and "power manager" are each modified by functional language: "to determine an optimal processing engine of the first processing engine and the second processing engine to perform a workload" (claim 10) and "to determine current power constraints, to determine available power budgets for each of the current power constraints, to select a most constraining power budget from the available power budgets, to determine an achievable frequency for the most constraining power budget, and to determine the first achievable capability based on the achievable frequency" (claim 11).
(C) Neither term is modified by sufficient structure, material, or acts for performing the claimed function. "Thread scheduler" and "power manager" do not recite any specific circuitry, algorithm, or component structure; they are recited only by the result they achieve.
Accordingly, claims 10-15 are interpreted under 35 U.S.C. 112(f), and "thread scheduler" and "power manager" are construed to cover the corresponding structure described in the specification for performing the claimed functions, and equivalents thereof. Because the specification was not available for this analysis, Examiner has not been able to identify the corresponding structure and has examined claims 10-15 based on the plain meaning of "thread scheduler" and "power manager," as best understood, for purposes of the prior-art rejections below. Applicant should review the specification to confirm that adequate corresponding structure (e.g., a disclosed algorithm for the scheduler's engine-selection function, and for the power manager's budget-determination and frequency-determination functions) is disclosed for each recited function; the absence of such disclosed structure renders the claim indefinite under 35 U.S.C. 112(b) for failure to disclose adequate corresponding structure. See MPEP § 2181(II). Examiner reserves the right to reject claims 10-15 under § 112(b) on this additional basis upon locating and reviewing the specification.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 16 is directed to "At least one machine-readable medium comprising a plurality of instructions." The claim is not limited to non-transitory media. Under the broadest reasonable interpretation, in light of the ordinary meaning of "machine-readable medium" absent an express limitation to a non-transitory medium, the claim encompasses transitory, propagating signals per se (e.g., a carrier wave transmitting the recited instructions). A claim that covers a signal per se is not a process, machine, manufacture, or composition of matter, and therefore does not fall within any of the four statutory categories of invention (MPEP 2106.03(II); In re Nuijten, 500 F.3d 1346 (Fed. Cir. 2007)). Claim 16 therefore is rejected as being directed to non-statutory subject matter. Claims 17-20 depend from claim 16, incorporate its non-transitory-media deficiency, and are rejected for the same reason.
Claims [1-20] rejected under 35 U.S.C. 101 because the claimed invention is directed to a mental process without significantly more.
Step 1:
Claim 1 is directed to "A method comprising:" a method, and is therefore directed to a process, which is one of the statutory categories.
Claim 10 is directed to "An apparatus comprising:" and is therefore directed to a machine, which is one of the statutory categories.
Claim 16 is directed to "At least one machine-readable medium comprising a plurality of instructions." The claim is not limited to non-transitory media. Under the broadest reasonable interpretation, in light of the ordinary meaning of "machine-readable medium," the claim encompasses transitory propagating signals per se, which are not a process, machine, manufacture, or composition of matter (MPEP 2106.03(II)). Claim 16 therefore fails Step 1. Claims 17-20 depend from claim 16 and inherit the deficiency.
Step 2A Prong One:
Claim 1 recites the limitations:
determining a first achievable capability for a first processing engine based on current operating conditions;
determining a second achievable capability for a second processing engine based on the current operating conditions, wherein the first achievable capability is different in magnitude from the second achievable capability; and
selecting one of the first processing engine and the second processing engine to perform a workload; wherein the selecting is based on the first achievable capability and the second achievable capability.
All of which can be performed in the human mind through observation, evaluation, judgement, and opinion, with the aid of pen and paper, and therefore reciting a mental process. A person can observe the operating conditions (for example, a power limit), estimate how much work each of two processors could achieve under those conditions, compare the two estimates, and choose the processor with the better estimate. To the extent the "determining" steps require computing a value from the operating conditions, they also recite a mathematical calculation. Accordingly, claim 1 recites a judicial exception (i.e. an abstract idea).
Step 2A Prong Two:
The additional elements recited in claim 1 include:
A first processing engine, a second processing engine, current operating conditions, and a workload.
Claim 1 fails to recite a specific improvement to how a processor executes, schedules, or manages power, and no measurable technical improvement (MPEP 2106.05(a)). The processing engines are recited at a high level of generality and are invoked merely as tools to be chosen between, which amounts to no more than instructions to apply the exception using generic computer components (MPEP 2106.05(f)). Notably, the claim never requires that the workload actually be executed on the selected engine, and never requires any hardware to be configured or controlled as a result of the selection, so the selection is not tied to any particular machine or transformation (MPEP 2106.05(b), (c)). The limitation "based on current operating conditions" merely limits the abstract idea to a particular technological field (MPEP 2106.05(h)).
Step 2B:
The additional elements, "a first processing engine," "a second processing engine," and "a workload," simply arrange generic computing components to perform the abstract idea in their ordinary, expected manner: evaluating alternatives and picking one, without any unconventional technical arrangement that would make it an inventive concept. Therefore, the additional elements, when considered individually and in combination, fail to add an inventive concept to the claim. Consequently, claim 1 does not amount to significantly more than the recited judicial exception and the claim is not eligible.
Claim 2 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 2 recites storing the first achievable capability in an achievable capability table if it differs more than a threshold amount from a previous achievable capability, which comprises a comparison that can be performed in the human mind through observation, evaluation, judgement, and opinion, with the aid of pen, paper, or a computer, and therefore recites a mental process. The recited storing in a table is insignificant extra-solution activity, and storing and retrieving information in memory is a well-understood, routine and conventional computer function (MPEP 2106.05(d)(II), 2106.05(g)).
Claim 3 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 3 recites re-determining the first and second achievable capabilities based on new operating conditions, which is merely repeating the mental process of claim 1 with new inputs and can be performed in the human mind with the aid of pen, paper, or a computer, and therefore recites a mental process.
Claim 4 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 4 recites that the determining is performed periodically during operation of a system, which merely specifies how often the mental process is performed and links it to a generic system (MPEP 2106.05(h)), and therefore adds no meaningful limit.
Claim 5 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 5 recites that the determining is performed upon a change in available power budget, which merely specifies the trigger for the mental process and can be performed in the human mind through observation, evaluation, judgement, and opinion, and therefore recites a mental process.
Claim 6 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 6 recites determining current power constraints, determining available power budgets for each, selecting a most constraining power budget, determining an achievable frequency for that budget, and determining the achievable capability from the frequency, all of which are observations, comparisons, and calculations that can be performed in the human mind through observation, evaluation, judgement, and opinion, with the aid of pen, paper, or a computer, and therefore recite a mental process and/or a mathematical calculation.
Claim 7 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 7 recites that the determination is made for multiple classes of workloads, which merely repeats the mental process for additional categories of data and therefore recites a mental process.
Claim 8 is dependent on claim 7, and therefore inherits the same judicial exception. Further, claim 8 recites that the classes include integer, floating point, or vector instruction workloads, which merely labels the data being evaluated and limits the abstract idea to a particular technological field (MPEP 2106.05(h)).
Claim 9 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Further, claim 9 recites that the capability includes a performance, energy efficiency, or memory bandwidth capability, which merely describes the type of information evaluated and does not change the mental nature of the evaluation.
Claim 10 recites "a first processing engine," "a second processing engine," and "a thread scheduler to determine an optimal processing engine." The scheduler performs the same evaluation and selection recited in claim 1, and therefore recites a mental process under Step 2A Prong One. Under Prong Two and Step 2B, the processing engines and the thread scheduler are recited at a high level of generality and function only as generic components used to apply the abstract idea (MPEP 2106.05(f)), and the claim recites no particular improvement to the operation of the engines or the scheduler. Claim 10 therefore does not amount to significantly more than the judicial exception.
Claim 11 is dependent on claim 10, and therefore inherits the same judicial exception. Further, claim 11 recites a "power manager" performing the determining, selecting and calculating steps recited in claim 6, which can be performed in the human mind for the reasons given for claim 6. Reciting a generic "power manager" to perform them merely applies the exception on a computer (MPEP 2106.05(f)).
Claim 12 is dependent on claim 10, and therefore inherits the same judicial exception. Further, claim 12 recites periodically updating the capabilities upon a change in power constraints, which is merely repeating the mental process of claim 10 and therefore recites a mental process.
Claims 13-15 are dependent on claim 10, and therefore inherit the same judicial exception. Further, claims 13 and 14 recite that the capability comprises a data value for each of multiple workload classes, and claim 15 recites the type of capability, all of which merely describe the content of the data evaluated and limit the abstract idea to a particular technological field (MPEP 2106.05(h)).
Claims 16-20, though pointing towards a manufacture, are rejected for the same reasons mentioned in claims 1-9. The recitation of instructions "executed on a computing device" merely instructs a generic computer to apply the abstract idea (MPEP 2106.05(f)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-15, 18 and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claims 8, 9, 14, 15 and 20, the phrase "at least one of…”is ambiguous as to whether the list is conjunctive (requiring each item) or disjunctive (requiring only one). See SuperGuide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870 (Fed. Cir. 2004). For purposes of examination, the phrase is interpreted disjunctively (any one of the listed items satisfies the limitation). Applicant is advised to use "at least one of A, B, or C" or "one or more of" to remove the ambiguity.
Regarding claim 10, the term "optimal processing engine" is a subjective term. The claim provides no objective standard for what makes an engine "optimal" (for example, best performance, lowest energy, or some balance), so the metes and bounds cannot be determined. Claims 11-15 depend from claim 10 and are rejected for the same reason.
Regarding claim 12, the limitation "the power manager" lacks antecedent basis, because claim 10, from which claim 12 depends, does not recite a power manager (it is introduced in claim 11). In addition, the claim recites that the manager is to "periodically update" the capabilities "upon a change in the current power constraints," and it is unclear whether the updating is periodic, event-driven, or both, since a periodic update and an update triggered by a change are different conditions.
Regarding claim 14, claim 13 requires that the capability comprise a value "for each of multiple classes of workloads," but claim 14 then recites that the multiple classes "comprise one of" an integer, floating-point, and vector workload. It is unclear how "multiple classes" can comprise only "one of" three listed classes, or whether all three are required.
Regarding claim 18, the limitation "wherein to determine the first achievable capability occurs periodically" is grammatically unclear as to what performs the determining and what occurs periodically. For examination, the claim is interpreted as the instructions causing the computing device to determine the first achievable capability periodically.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 9, 10, 12, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shanbhogue et al. (US 2019/0042280 A1),
Regarding claim 1, Shanbhogue teaches
A method comprising, by disclosing a method performed by a processor and a scheduler for scheduling threads on a heterogeneous processor (Abstract; FIG. 16, scheduling method 1600; FIG. 21). Here, showing a method of dynamically determining core capabilities and using them to schedule work.
determining a first achievable capability for a first processing engine based on current operating conditions, by teaching that a power control unit (PCU 138; feedback control circuit 256 of FIG. 2) dynamically determines hardware feedback information for each core, namely a performance capability and an energy efficiency capability, with each entry specifying the relative capability of a logical processor "given current system workload and power and thermal constraints." The capability is stored per core in the hardware feedback structure (FIG. 19, structure 1900, core entries 1920 with performance capability 1924 and energy efficiency capability 1926). The cores are also described as compute engines, and additional processing engines such as a graphics unit and image signal processor are present in the same processor (FIG. 9, units 920, 925; FIG. 3, feedback control circuit 356 determining feedback information for the cores and other execution engines; see also ¶¶ [0041]-[0042]), so a core or other compute engine reads on the recited processing engine.
determining a second achievable capability for a second processing engine based on the current operating conditions, wherein the first achievable capability is different in magnitude from the second achievable capability, by teaching that the same feedback is determined for each of the plurality of cores, including a large core and one or more smaller, lower-power cores (FIGS. 10 and 15; FIG. 16, blocks 1620/1670), and that the resulting values differ between cores, for example an 8-bit relative value where higher values indicate higher capability (FIG. 19). Shanbhogue further explains that under power or thermal constraints a smaller core can have higher performance than a larger core (FIG. 17, regions 1750-1770), i.e., the determined capabilities differ in magnitude between the engines.
and selecting one of the first processing engine and the second processing engine to perform a workload; wherein the selecting is based on the first achievable capability and the second achievable capability, by teaching that the operating system scheduler reads the hardware feedback information, updates its scheduling structure, and uses it to schedule a thread to a selected core type (FIG. 16, blocks 1650-1670 and 1620; FIGS. 22-23, updating OS data structures used by the scheduler). Shanbhogue expressly describes the scheduler using the current capabilities of the logical processors to choose the more appropriate core for a thread. Shanbhogue further teaches a scheduler that places a first thread on a second core when the second core's current performance capability and current energy efficiency capability both exceed those of the first core (Summary, system example). The selection is therefore expressly based on comparing the capabilities of both candidate engines.
Regarding claim 3, Shanbhogue teaches
further comprising re-determining the first achievable capability and the second achievable capability based on new operating conditions, by teaching that the power controller continuously computes the capability information and updates the structure whenever a meaningful change occurs due to changes in workload and power/thermal limits, and notifies the OS (FIG. 22, blocks 2210-2230; FIG. 19, change indicators 1914, 1916).
Regarding claim 4, Shanbhogue teaches
wherein the determining the first achievable capability is performed periodically during operation of a system, by teaching that the capabilities are recomputed on an ongoing basis while the system operates, that updates may be limited to no more than once per given interval (e.g., on the order of 10 ms), and that the OS may poll for new information on a periodic basis (e.g., every 30 ms) (FIG. 23, method 2300).
Regarding claim 5, Shanbhogue teaches
wherein the determining the first achievable capability is performed upon a change in available power budget, by teaching that the feedback is computed from power and thermal constraints (including power delivery and thermal headroom), and that a hardware feedback notification is generated when a change occurs due to power or thermal limits (Table 3, package thermal interrupt MSR; FIG. 22). A change in the power/thermal headroom available to the cores therefore triggers a new determination and update.
Regarding claim 9, Shanbhogue teaches
wherein the first achievable capability includes at least one of a performance capability, an energy efficiency capability, and a memory bandwidth capability, by teaching a performance capability and an energy efficiency capability for each core (FIG. 19, fields 1924 and 1926). Under the disjunctive interpretation adopted above, this satisfies the claim.
Regarding claim 10, Shanbhogue teaches
An apparatus comprising: a first processing engine with a first achievable capability; a second processing engine with a second achievable capability, wherein the first achievable capability is different in magnitude than the second achievable capability, by teaching a heterogeneous multicore processor with a first (large) core and second (smaller) cores, each having dynamically determined performance and efficiency capabilities of differing magnitude (FIG. 10, core domains 1010/1020; FIG. 15; FIG. 19; FIG. 17), for the reasons given for claim 1;
and a thread scheduler to determine an optimal processing engine of the first processing engine and the second processing engine to perform a workload, wherein the thread scheduler to determine the optimal processing engine based on the first achievable capability and the second achievable capability, by teaching an OS scheduler executing on the processor (FIG. 20, OS 2070 on processor 2010) that uses the hardware feedback capabilities to make scheduling decisions, described as enabling optimal or better scheduling of threads to the most appropriate core (FIG. 16; FIGS. 22-23). Shanbhogue's scheduler determines the better-suited core from the capabilities of the candidate cores, which meets the claimed determination of an "optimal" engine as best understood.
Regarding claim 12, Shanbhogue teaches,
wherein the power manager to periodically update the first achievable capability and the second achievable capability upon a change in the current power constraints, by teaching that the PCU (power manager 940 of FIG. 9; PCU 138/255/355) updates the capabilities when power or thermal constraints change and writes the update to the feedback structure, subject to a minimum update interval (FIGS. 19-23; Table 3).
Regarding claim 15, Shanbhogue teaches
wherein the first achievable capability includes at least one of a performance capability, an energy efficiency capability, and a memory bandwidth capability, for the reasons given for claim 9.
Regarding claim 16, Shanbhogue teaches
At least one machine-readable medium comprising a plurality of instructions which, when executed on a computing device cause the computing device to: [perform the steps of claim 1], by teaching that the OS scheduler and the PCU microcode/firmware are software and firmware stored in memory and executed on the processor (FIG. 15, data storage 1528 with code 1530; FIG. 20, microcode of core 2020), and by teaching a computer readable medium including instructions to perform the disclosed methods. The determining and selecting steps are met for the reasons given for claim 1.
Regarding claim 17, Shanbhogue teaches
further comprising further instructions which, when executed on the computing device cause the computing device to re-determine the first achievable capability and the second achievable capability based on new operating conditions, for the reasons given for claim 3.
Regarding claim 18, Shanbhogue teaches,
wherein to determine the first achievable capability occurs periodically during operation of a system, for the reasons given for claim 4.
Regarding claim 20, Shanbhogue teaches
wherein the first achievable capability includes at least one of a performance capability, an energy efficiency capability, and a memory bandwidth capability, for the reasons given for claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue (US 2019/0042280 A1), in view of Gupta et al. (US 2021/0064426 A1)
Regarding claim 2, Shanbhogue teaches
further comprising storing the first achievable capability in an achievable capability table, by teaching a table structure (FIG. 19, structure 1900) in which the per-core capabilities are stored, and that updates are written only when the feedback has meaningfully changed since the last update, tracked by change indicators (FIG. 19, indicators 1914/1916). Shanbhogue also limits update frequency so that the OS is not overwhelmed by too-frequent updates. However, Shanbhogue fails to explicitly state that the storing occurs if the capability differs more than a threshold amount from a previous capability, as it describes only a meaningful-change test. Gupta picks up this teaching, by describing that the power controller determines, from the per-core performance and efficiency values and one or more threshold values, whether a hardware state change of one or more cores "exceeds a threshold," and reports the change to the OS scheduler only if it does (FIG. 21, diamond 2170; FIGS. 22-23, efficiency and idling thresholds). Gupta further teaches hysteresis-based bidirectional thresholds, timers, and averaging to keep frequent transient changes from triggering OS updates.
A person of ordinary skill in the art having Shanbhogue's meaningful-change updating available would have been motivated to implement the change test as an explicit threshold comparison as taught by Gupta, because a threshold is the ordinary way of deciding whether a change is significant, and it would predictably avoid needless table writes and OS notifications, a concern both references address (Shanbhogue, minimum update interval and OS flow control; Gupta, FIGS. 21-23). Thus, this is an application of a known technique, to a known system, to yield a predictable result.
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue, in view of Gupta, and further in view of Naffziger et al. (US 2012/0159198 A1)
Regarding claim 6, Shanbhogue teaches
wherein the determining the first achievable capability comprises: determining current power constraints, by teaching that the capability computation is based on power and thermal constraints on the processor, such as power delivery and thermal headroom; and determining the first achievable capability based on a frequency-related operating state, by teaching that the performance capability is a relative value based in part on the performance state (P-state) of the core.
However, Shanbhogue fails to explicitly detail determining available power budgets for each of multiple power constraints, selecting a most constraining budget, and determining an achievable frequency for that budget. Naffziger picks up this teaching, by describing multiple concurrent power limits on a processor: a chip limit set by the cooling solution and voltage regulator capability, a limit set by operating-system software, and a limit set by an external agent such as a data center power manager (Naffziger, Table 1; FIG. 2, programmable locations 32). These correspond to the recited available power budgets for each power constraint. Naffziger further teaches that the "lowest value of the three power targets" is selected as the processor power target, which is the recited most constraining power budget. Naffziger then teaches that the power controller adjusts core voltage and/or frequency, per core if needed, so that measured power stays below that target (FIG. 4, blocks 70-72), which yields the highest frequency achievable under the binding limit, i.e., the recited achievable frequency.
A person of ordinary skill in the art having Shanbhogue's constraint-based capability computation available would have been motivated to determine the capability from the frequency achievable under the tightest of the applicable power limits as taught by Naffziger, because a core cannot exceed the frequency permitted by the most restrictive limit, so the capability reported to the scheduler would otherwise overstate what the core can deliver. Thus, this is an application of a known technique, to a known system, to yield a predictable result, namely capability values that reflect the actual power-limited performance of each core.
Gupta likewise teaches determining the capability from the frequency achievable under a power budget. Gupta calculates a processor power budget from current-sensor information compared against a configured limit such as a thermal design power level (FIG. 21, blocks 2110-2120), allocates and scales the budget across the cores (blocks 2130-2140), and uses a power-to-performance lookup table indexed by the scaled budget to identify an operating frequency for each core type (FIG. 24, table 2400; block 2150). Gupta then converts the per-core operating points into per-core performance and efficiency values that are reported to the OS scheduler (block 2160), and teaches that the final operating point is further bounded by platform constraints such as temperature, current limits and a shared voltage rail (FIGS. 27-28). Applying Gupta's budget-to-frequency-to-capability derivation within Shanbhogue's constraint-based capability computation would have been obvious for the same reasons given above: the reported capability then reflects what each core can actually deliver under its binding limit, a predictable result.
Regarding claim 11, Shanbhogue teaches
The apparatus of claim 10, further comprising a power manager to determine current power constraints, by teaching the PCU / power manager (PCU 138, 255, 355; power manager 940) that computes capabilities from power and thermal constraints and from the core performance state; and Naffziger teaches the remaining determinations of available power budgets for each constraint, selection of the most constraining budget, and determination of an achievable frequency under it (Table 1; FIG. 2, power controller 36; FIG. 4), while Gupta teaches deriving the per-core capability from the frequency achievable under the power budget (FIG. 21, blocks 2110-2160; FIG. 24), which is then used, in Shanbhogue's power manager, to determine the capability, for the same reasons and with the same motivation as given for claim 6.
Claims 7, 8, 13, 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue, in view of Weissmann et al. (US 2021/0240475 A1),
Regarding claim 7, Shanbhogue teaches the method of claim 1, and further teaches that the capabilities depend on the workload and thread type, and that the characteristics of the workloads executing on the logical processors are considered in scheduling (FIG. 18, workload-dependent performance scalability between large and small cores). However, Shanbhogue fails to explicitly teach determining the capability separately for multiple classes of workloads. Weissmann picks up this teaching, by describing a hardware guide scheduler that characterizes the running thread by weighting counts of classes of performance monitoring events, with a separate programmable weight for each class (FIG. 2, weights register 220, work counter 230; ¶¶ [0082]-[0083]). Weissmann explains that the weights may reflect a performance ratio, for example a higher weight for an instruction class that executes about twice as fast on a big core than for other instruction classes (¶ [0082]), i.e., a per-class measure of how much more capable one core type is than another. Weissmann further teaches that the resulting hardware guide scheduler class is used by a hybrid scaling predictor to predict performance scaling between big and little cores and to hint the OS which core type to schedule the thread on (FIG. 2, predictor 240 and OS 242; ¶ [0084]). Weissmann places this mechanism in the same hardware feedback framework as Shanbhogue, describing it as feeding the enhanced hardware feedback interface, also referred to as HGS or HGS plus (¶ [0099]).
A person of ordinary skill in the art having Shanbhogue's per-core capabilities available would have been motivated to determine and report them separately for each workload class as taught by Weissmann, because the relative advantage of a large core over a small core varies with the instruction mix (as Shanbhogue itself acknowledges in FIG. 18 and as Weissmann quantifies with per-class performance ratios), so per-class capability values would let the scheduler place a thread on the core best suited to its instruction mix under the current power and thermal limits. Because both references feed the same kind of hardware feedback to an OS scheduler on a heterogeneous processor, the combination is an application of a known technique, to a known system, to yield a predictable result.
Regarding claim 8, Weissmann teaches
wherein the multiple classes of workloads includes at least one of an integer instruction workload, a floating point instruction workload, and a vector instruction workload, by teaching that the classes of events counted may be sub-classes of the instruction set architecture, such as "AVX floating-point, AVX2 integer" (¶ [0082]), and that the counted events include arithmetic floating-point vector instructions, arithmetic integer vector instructions, and integer vector neural-network instructions (¶ [0083]). Under the disjunctive interpretation adopted above, this satisfies the claim. Even if the claim were read conjunctively, Weissmann describes classes for integer, floating-point and vector instructions, so all three are taught.
Regarding claim 13, Shanbhogue teaches
the apparatus of claim 10 with a per-core capability data value (FIG. 19, fields 1924/1926), and Weissmann teaches wherein the first achievable capability comprises a data value for each of multiple classes of workloads, by teaching a distinct weight value stored for each class of instruction event, where the weights reflect the performance ratio of that class between core types (FIG. 2, weights register 220; ¶ [0082]), for the reasons and with the motivation given for claim 7.
Regarding claim 14, Weissmann teaches
wherein the multiple classes of workloads comprise one of an integer instruction workload, a floating-point instruction workload, and a vector instruction workload, for the reasons given for claim 8.
Regarding claim 19, Shanbhogue teaches
the medium of claim 16, and Weissmann teaches wherein the first achievable capability includes capabilities for multiple classes of workloads, for the reasons and with the motivation given for claims 7 and 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL NWUHA whose telephone number is (571)272-9367. The examiner can normally be reached Monday-Friday; 7:30 am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMUEL OBINNA NNAJI NWUHA/
Examiner, Art Unit 2194
/KEVIN L YOUNG/ Supervisory Patent Examiner, Art Unit 2194
