DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the claims filed 6/16/2023.
Claims 1-5 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted 6/16/2023 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ANALOGUE CIRCUIT FOR ACTIVATION FUNCTION COMPUTATION IN NEUROMORPHIC SYSTEMS"
Reasoning: Corrects the typo “NUROMORPHIC” and specifies the type of arithmetic (activation functions), and defines the system context clearly.
Claim Objections
Claims 1-5 are objected to because of the following informalities:
Claim 1, line 5, “a voltage/current conversion circuit” should be --a voltage to current conversion circuit-- to prevent this from being mistakenly interpreted as “and/or”.
Claim 1, line 10, “a current/voltage conversion circuit” should be --a current to voltage conversion circuit-- to prevent this from being mistakenly interpreted as “and/or”.
Claim 1, line 12, “calculates a ratio of the voltage obtained” should be --calculates a ration of a voltage obtained-- as otherwise there is lack of antecedent basis for the claim limitation.
Claim 2, line 1, “wherein the voltage/current” should be --wherein voltage to current-- to prevent this from being mistakenly interpreted as “and/or”.
Claim 3, line 2, “the current/voltage” should be --the current to voltage-- to prevent this from being mistakenly interpreted as “and/or”.
Claim 4, line 3, “the voltage/current” should be --the voltage to current-- to prevent this from being mistakenly interpreted as “and/or”.
Claim 5, line 1, “A nuromorphic” should be -- A neuromorphic-- to correct for typographical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Vatalaro et al. (hereinafter Vatalaro), “A low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks” (2021) pages 1-11, in view of Anson et al. (hereinafter Anson), “Versatile precision source ratioing system for fast kinetic spectroscopy” (1976) pages 370-373.
Regarding independent claim 1, Vatalaro teaches an analogue arithmetic unit (Abstract describes a low-power analog implementation of softmax function), comprising: a plurality of input terminals (Abstract, pages 2-3 circuit is designed to handle multiple inputs (M elements, e.g., M=10)); a voltage to current conversion circuit which exponentially converts each input voltage applied to each of the plurality of input terminals and outputs the converted input voltage as a current (Abstract, page 4 Figure 3(a) 2nd stage “Exponential” of Conversion Block uses transistor M5 operating below the threshold voltage regime to implement the required exponential function, converting a voltage signal into an exponential current I_EXP. This satisfies the requirement for a voltage to current conversion circuit which exponentially converts input voltages into currents); a current addition circuit which obtains a sum of the currents converted by the voltage to current conversion circuit (page 3-5 requires summing all exponential currents I_B =sum I_{EXP(k) in Figure 3(b) Divider to form the denominator for the normalization step Equation (10). This satisfies the requirement for a current addition circuit which obtains a sum of the currents).
Vatalaro does not expressly teach a current to voltage conversion circuit which converts each of the currents and the sum of the currents into voltages; and a division circuit which calculates a ratio of a voltage obtained by converting each of the currents to a total voltage obtained by converting the sum of the currents.
However, Anson teaches a current to voltage conversion circuit which converts each of currents and a sum of the currents into voltages (page 371 Section II B incorporating operational amplifiers in a virtual earth configuration (a current to voltage conversion circuit) to amplify input currents (each of the currents and the sum of the currents) and convert them to separate voltage signals for the numerator (N) and denominator (D) channels); and a division circuit which calculates a ratio of a voltage obtained by converting each of the currents to a total voltage obtained by converting the sum of the currents (page 371 Section II B utilizes a specialized electronic analog divider module, e.g., Burr Brown Corp. no. 4290 (and a division circuit), that operates on the converted voltage signals (N and D) to perform high-precision linear division to output voltage, e.g. ‘maximum output > 11V’).
Because Vatalaro and Anson address the issue of current to voltage conversion in a divider sub-circuit, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of a current to voltage conversion circuit which converts each of currents and a sum of the currents into voltages; and a division circuit which calculates a ratio of a voltage obtained by converting each of the currents to a total voltage obtained by converting the sum of the currents as suggested by Anson into Vatalaro’s analogue arithmetic unit, with a reasonable expectation of success, such that Anson’s current to voltage conversion mechanism of the numerator and denominator current N and D, respectively, are applied to Vatalaro’s individual currents and the sum of the currents generating the exponential currents and further providing the specialized electronic analog divider module to operate on the converted voltage signals of the individual currents and the sum of the currents for performing voltage division to teach a current to voltage conversion circuit which converts each of the currents and the sum of the currents into voltages; and a division circuit which calculates a ratio of a voltage obtained by converting each of the currents to a total voltage obtained by converting the sum of the currents. This modification would have been motivated by the desire to achieve high precision and accuracy over a wide operating range (Anson page 371 left column). In addition this address potential drawbacks of Vatalaro's simple, subthreshold current-mode loop in terms of high precision and accuracy over a wide operating range.
Regarding dependent claim 5, Vatalaro, in view of Anson, teach a neuromorphic device, comprising: the analogue arithmetic unit according to claim 1 (see Vatalaro Abstract, Section 1 Introduction explicitly states that the analogue arithmetic unit (the softmax circuit) is a "low-power analog implementation of softmax function" designed for Analog Neural Networks. The softmax function is a standard activation function used to mimic neuron output in multi-class problems within Deep Neural Networks (DNNs), which are the core component of neuromorphic systems. Since Vatalaro's entire purpose is to provide hardware for Analog Neural Networks, the incorporation of the claimed unit into a neuromorphic device is clearly taught and suggested).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Vatalaro in view of Anson, as applied in the rejection of claim 1 above, and further in view of NEWNS et al. (hereinafter NEWNS), US 2020/0167402 A1.
Regarding dependent claim 2, Vatalaro, in view of Anson, teach all the elements of claim 1.
Vatalaro and Anson do not expressly teach wherein the voltage to current conversion circuit includes a diode.
However, NEWNS teaches a voltage to current conversion circuit includes a diode ([0019]-[0021], [0024] describes an adder 104 comprising a voltage input Z_i is placed across a plurality of diodes to form a channel current. This relies on the diode's current/voltage characteristics to achieve the exponential conversion).
Because Vatalaro, in view of Anson, and NEWNS address an analog softmax circuit, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings wherein a voltage to current conversion circuit includes a diode as suggested by NEWNS into Vatalaro and Anson’s analogue arithmetic unit, with a reasonable expectation of success, such that the analog softmax circuit includes an adder comprising a voltage input is placed across a plurality of diodes to form a channel current to teach wherein the voltage to current conversion circuit includes a diode. This modification would have been motivated by the desire to provide further embodiment for implementing the softmax function in an analog circuit (NEWNS [0003]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Vatalaro in view of Anson, as applied in the rejection of claim 1 above, and further in view of Rankin et al. (hereinafter Rankin), US 2003/0168335 A1.
Regarding dependent claim 3, Vatalaro, in view of Anson, teach all the elements of claim 1.
Vatalaro and Anson do not expressly teach further comprising: a switch which controls the current flowing through the current to voltage conversion circuit.
However, Rankin teaches a switch which controls the current flowing through a current to voltage conversion circuit ([0006], [0020], [0023]-[0025] describes a transfer gate (TG) inserted into the circuitry of the I/V converter as shown in FIG. 3. The TG includes parasitic resistance but is structurally a switch. [0020] The transfer gate's primary function is to act as a switch which can be turned on and off to either electrically include or isolate the I/V converter. When the TG is open, it prevents the current I_S from flowing through the external resistor (R) that defines the current-to-voltage conversion).
Because Vatalaro, in view of Anson, and Rankin address CMOS integrated circuits, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of a switch which controls the current flowing through a current to voltage conversion circuit as suggested by Rankin into Vatalaro and Anson’s analogue arithmetic unit, with a reasonable expectation of success, such that the analog circuit includes a transfer gate switch which controls the current flowing through a current to voltage conversion circuit to teach further comprising: a switch which controls the current flowing through the current to voltage conversion circuit. This modification would have been motivated by the desire to allow the input terminal to be shared or multiplexed for multiple functions by isolating the C/V conversion when needed (Rankin [0006]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Vatalaro in view of Anson, as applied in the rejection of claim 1 above, and further in view of Mallinson, US 2004/0232950 A1.
Regarding dependent claim 4, Vatalaro, in view of Anson, teach all the elements of claim 1.
Vatalaro and Anson do not expressly teach wherein each of the plurality of input terminals has a first input terminal and a second input terminal, and a reference voltage of the voltage to current conversion circuit is applied to the second input terminal.
However, Mallinson teaches wherein each of a plurality of input terminals has a first input terminal and a second input terminal, and a reference voltage of a voltage to current conversion circuit is applied to the second input terminal (Abstract, [0003], [0018], [0020], FIG. 1 describes a voltage-to-current converter configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. This architecture is achieved using a plurality of comparators (long-tailed pairs) wherein receiving the input voltage V_in and a separate reference voltage means that the voltage to current conversion unit must inherently have a structure corresponding to a first input terminal for the signal V_in and a second input terminal for the reference voltage. The input voltage V_in is summed together with a corresponding reference voltage V_1, V_2, ... to serve as the input to the voltage to current conversion elements (comparators)).
Because Vatalaro, in view of Anson, and Mallinson address the issue of input terminals of a voltage to current conversion circuit, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings wherein each of a plurality of input terminals has a first input terminal and a second input terminal, and a reference voltage of a voltage to current conversion circuit is applied to the second input terminal as suggested by Mallinson into Vatalaro and Anson’s analogue arithmetic unit, with a reasonable expectation of success, to teach wherein each of the plurality of input terminals has a first input terminal and a second input terminal, and a reference voltage of the voltage to current conversion circuit is applied to the second input terminal. This modification would have been motivated by the desire to incorporate a known V/I input technique (Mallinson) into the Softmax circuit (Vatalaro/Anson) to control or calibrate the reference level of the exponential conversion, thereby increasing the system's accuracy and linearity over the operating range (Mallinson [0037]). This addresses the general need for high precision and stability in analog neural network components.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fujita et al. (US 6670903 B2) (Dec. 30, 2003) (ABSTRACT A signal from a photodiode (PD) is supplied to an A/D converter circuit (30) through an integrator (10) and a switch circuit (20). An amplifier circuit (40) amplifies a residue in A/D conversion, and the amplified residue (analog value) is supplied to the A/D converter circuit (30) through the switch circuit (20) and converted to a digital value by the A/D converter circuit (30)).
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/KC CHEN/Primary Patent Examiner, Art Unit 2143