DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA and is in response to the amendments filed on 02/05/2026. Claims 1-20 are pending.
In the interest of facilitating compact prosecution the examiner invites the applicant to contact the examiner to discuss ways to better focus the instant application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 103 as being unpatentable over Booth, Jr. et al. (U.S. Pat. 7038687) in view of Poisner et al (U.S. Pub. 2002/0199093).
Booth reference has been previously presented by examiner, and Poisner reference has been previously presented in IDS filed on 01/08/2026.
As per claim 1, Booth teaches the invention substantially as claimed including an apparatus comprising: a main system that includes at least a processing unit and a system memory; a sub-system that includes a chipset attached processing unit and a chipset attached memory (Fig. 2, col 3 lines 16-18, col 4 lines 5-29, col 5 lines 3-5, col 6 lines 19-26 processing system contains an application processor with its own dedicated on-die memory, which is attached to a coprocessor and associated local memory that may be part of a separate semiconductor device/chip),
wherein the chipset attached processing unit is configured to perform one or more tasks using the chipset attached memory (col 5 lines 48-66); and a chipset link that couples the main system to the sub-system (col 4 lines 27-29, 55-61, col 5 lines 6-14).
Booth does not explicitly teach that there is a memory controller configured to manage access to the system memory; and a chipset attached memory controller configured to manage access to the chipset attached memory.
However, Poisoner teaches a memory controller configured to manage access to the system memory ([0015], Fig. 1A MCH); and a chipset attached memory controller configured to manage access to the chipset attached memory ([0016], [0019], Fig. 1A ICH is a I/O controller, which is similar to “I/O expander” of the instant application, that manages its own RAM).
It would be obvious to one with ordinary skill in the art prior to the effective filling date of the invention to combine the teachings of Booth and Poisner because both are directed towards internal processing details of a computing system. One with ordinary skill in the art would be motivated to incorporate the teachings of Poisoner into that of Booth because Poisner provide a way to improve internal processing using content stored in RAM of the computing system ([0001], [0005]-[0007]).
As per claim 2 Booth teaches wherein contents of the system memory are transferable to the chipset attached memory of the sub-system via the chipset link to enable the chipset attached processing unit to perform the one or more tasks using the contents from the chipset attached memory (col 4 lines 27-29, col 6 lines 1-5).
As per claim 3 Booth teaches wherein the main system further includes a memory controller, wherein the memory controller is configured to signal the system memory to transfer the contents to the chipset attached memory (col 4 lines 27-29 memory controller perform DMA transfer of data).
As per claim 4 Booth teaches wherein the processing unit and the system memory are power gated while the chipset attached processing unit performs the one or more tasks using the chipset attached memory (col 5 lines 55-58).
As per claim 5 Booth teaches wherein the power gating causes the main system to be completely shut off while the chipset attached processing unit performs the one or more tasks using the chipset attached memory (col 5 lines 55-58).
As per claim 6 Booth teaches wherein the power gating causes the main system to operate in a reduced power mode while the chipset attached processing unit performs the one or more tasks using the chipset attached memory (col 5 lines 55-58, 63-66).
As per claim 7 Booth teaches wherein the processing unit is configured to perform additional tasks using additional contents from the system memory while the chipset attached processing unit performs the one or more tasks using the chipset attached memory (col 5 lines 48-51, 60-67 application processor may be freed up to facilitate faster and more efficient processing by the application processor; or the application processor may be woken up to process data in response to result of monitoring of network connectivity by the coprocessor).
As per claim 8 Booth wherein the one or more tasks are allocated to the chipset attached processing unit and the chipset attached memory based on a power consumption of the one or more tasks (col 5 lines 48-67 tasks are offloaded to coprocessor in order to reduce power consumption).
As per claim 9 Booth teaches wherein the one or more tasks are allocated to the chipset attached processing unit and the chipset attached memory based on a computational complexity of the one or more tasks (col 5 lines 53-56, 64-65).
As per claim 10 Booth teaches wherein the one or more tasks are allocated to the chipset attached processing unit and the chipset attached memory based on a list which specifies types of tasks to be allocated to the chipset attached processing unit and the chipset attached memory (col 4 lines 10-17 coprocessor can be used to process 2D graphics operations, 3D graphics operations, multimedia encoding and decoding operations and display refresh operations; or other operations).
As per claim 11 Booth teaches further comprising at least one sub- system that includes at least an chipset attached processing unit and a chipset attached memory, wherein the chipset attached processing unit is configured to perform one or more additional tasks using the chipset attached memory (col 5 lines 63-67, col 6 lines 41-45 coprocessor could also be a wireless companion chip that perform wireless-specific tasks).
Booth does not explicitly teach that the sub-system and its components are additional components. However, it would be obvious to one with ordinary skill in the art prior to the effective filling date of the invention to combine the wireless device embodiment of Booth (see mappings for claim 11 above) with that of graphical processing embodiment of Booth (see mappings of claim 1 above) because Booth teaches a system that contains both graphical and wireless components (Fig. 1). One with ordinary skill in the art would be motivated to incorporate the wireless embodiment of Booth into that of graphical processing embodiment of Booth because it would improve over performance of the system (col 1 lines 13-31).
As per claim 12 Booth teaches transferring contents of a system memory to a chipset attached memory, the contents transferred over a chipset link from a source side of the chipset link that includes the system memory to a destination side of the chipset link that includes the chipset attached memory (col 4 lines 23-30, col 6 lines 1-5, 19-26);
performing, by a chipset attached processing unit on the destination side of the chipset link, one or more tasks using the contents transferred to the chipset attached memory; and while the one or more tasks are performed by the chipset attached processing unit on the destination side of the chipset link, power-gating the source side of the chipset link that includes the system memory (col 5 lines 48-67).
Poisner teaches wherein a memory controller of the system memory is configured to signal the system memory to transfer the contents to the chipset attached memory, and wherein the destination side includes a chipset attached memory controller configured to manage access to the chipset attached memory ([0015]-[0019], Fig. 1A MCH communicates with ICH to access RAM 106 that is managed by the ICH).
As per claim 13 Booth teaches further comprising: powering on the source side that includes the system memory; and performing, by a processing unit included on the source side, one or more additional tasks using the contents of the system memory (col 5 lines 60-63, 66-67).
As per claim 14 Booth teaches wherein performing the one or more tasks by the chipset attached processing unit on the destination side of the chipset link reduces power consumption (col 5 lines 55-58).
As per claims 15-20 they are broader reworded system versions of claims 3-5 and 8 or 9 (claims 15 and 19 corresponds to claim 3, claim 16 corresponds to claim 4, claim 17 corresponds to claim 5 and claim 20 corresponds to claims 8 or 9). As such, they are rejected for similar reasons as those presented for claims 3-5, respectively.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BING ZHAO whose telephone number is (571)270-1745. The examiner can normally be reached 9:30am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached on (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BING ZHAO/Primary Examiner, Art Unit 2151
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