FINAL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to claim(s) 1-3, 5-9, 11-13, 15-17, and 19-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
Claim(s) 1-3, 5, 6, 9, 11, 15-17, 19, 21, 25, 26 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poisner (US 20020199093) in view of Pelner.
Regarding claim 1, Poisner teaches an apparatus comprising: a system memory managed by an operating system of the apparatus; a chipset attached memory comprising dynamic random-access memory,(“ Usually, there is substantially more physical address space supported than is needed to address the actual physical memory (e.g., SIMM (single inline memory module) or DIMM (dual inline memory module) DRAM (dynamic RAM)) installed in a system” ¶12); the chipset attached memory being separate from the system memory and managed by an application running on the apparatus (“According to embodiments of the invention, RAM in devices separate from the main memory ("separate RAM") may be used for a stack and temporary storage during BIOS execution. The separate RAM is typically dedicated, in its normal usage, to one or more functional logic blocks of a chipset.” ¶11); and responsive to completion of the boot-up process for the apparatus, use the system memory as the main memory (“Once the BIOS program has executed past a certain point, for example, once main memory is fully configured, the stack in separate RAM is no longer needed and normal chipset operations are possible. Accordingly, the CPU's stack pointer may be re-programmed to point to main memory” ¶28). Poisner does not teach configured to: power down the apparatus and load a boot-up process in the chipset attached memory, the boot-up process configured to perform the boot-up process for the apparatus by the chipset attached memory use the chipset attached memory as a main memory during performance of of the boot up process for the apparatus by the chipset attached memory
Pelner teaches configured to: power down the apparatus (“The computer system is then automatically restarted” ¶36.) Powering down a system is a function inherent to restarting a system; and load a boot-up process in the chipset attached memory, the boot-up process configured to perform the boot-up process for the apparatus by the chipset attached memory. (“The term "boot", and associated terms such as "booting" and "boot up", as used herein, mean the process by which a computing device such as a computer system loads an operating system or operating system kernel into an operational memory, such as random access memory ("RAM") from a long-term storage memory, such as a read-only memory (ROM)“ ¶3, “Memory space 50 comprises software 100. Software 100 includes a bootloader 101, one or more component tests 102, an operating system (O/S) 103, and one or more applications 104” ¶25, “In FIG. 2, the software 100 can reside in any suitable machine-accessible media” ¶28, figures 4A-C, steps 320 ) use the chipset attached memory as a main memory during performance of (“Because ROM memory is typically slower than RAM, the BIOS is usually first loaded from ROM into RAM, and it is then executed from RAM… The BIOS may first test only the amount of RAM required to load the BIOS from ROM, and then check the remainder of RAM” ¶6). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the use of chipset attached RAM during boot up processes as taught by Poisner with the boot up processes described by Pelner. With this available temporary RAM, boot times would be improved because CPU cache would be allowed to function as a true code cache instead (Poisner ¶05).
Regarding claim 2, Pelner teaches The apparatus of claim 1 as described above, and wherein the boot-up process loads one or more memory testing applications (“A sequence of tests is performed when the computer system is first turned on. The operation of various components of the computer system, such as a chip set, a random access memory (RAM)…and the like, is tested by a test program stored in read only memory (ROM).” ¶13);
Regarding claim 3, Pelner teaches the apparatus of claim 2 as shown above, and wherein the one or more memory testing applications are configured to test the system memory (“The operation of various components of the computer system, such as a chip set, a random access memory (RAM)…and the like, is tested” ¶13).
Regarding claim 5, Pelner teaches The apparatus of claim 1, wherein the boot-up process is further configured to initialize one or more hardware components of the apparatus. (“The BIOS also typically initializes various of these components, which can include, but are not limited to, system busses;” ¶4).
Regarding claim 6, Pelner teaches The apparatus of claim 1, wherein the boot-up process is further configured to load an operating system. (“as used herein, mean the process by which a computing device such as a computer system loads an operating system” ¶3).
Regarding claim 9, Pelner teaches The apparatus of claim 1, wherein the memory controller loads the boot- up process in the chipset attached memory when the apparatus is in a bypass mode, () and the bypass mode configured to bypass the system memory. (“Before loading the BIOS into RAM, it may test a memory controller located, for example, in the chipset.” ¶6). BIOS is loaded from ROM to test system RAM, therefore bypassing RAM.
Regarding claim 11, Poisner teaches a method comprising: …a system that includes at least a system memory managed by an operating system; a chipset link, and a chipset attached memory comprising dynamic random-access memory,(“ Usually, there is substantially more physical address space supported than is needed to address the actual physical memory (e.g., SIMM (single inline memory module) or DIMM (dual inline memory module) DRAM (dynamic RAM)) installed in a system” ¶12); the chipset attached memory being separate from the system memory and managed by an application running on the apparatus (“According to embodiments of the invention, RAM in devices separate from the main memory ("separate RAM") may be used for a stack and temporary storage during BIOS execution. The separate RAM is typically dedicated, in its normal usage, to one or more functional logic blocks of a chipset.” ¶11); and responsive to completion of the boot-up process for the apparatus, use the system memory as the main memory (“Once the BIOS program has executed past a certain point, for example, once main memory is fully configured, the stack in separate RAM is no longer needed and normal chipset operations are possible. Accordingly, the CPU's stack pointer may be re-programmed to point to main memory” ¶28). Poisner does not teach configured to: power down the apparatus and load a boot-up process in the chipset attached memory, the boot-up process configured to perform the boot-up process for the apparatus by the chipset attached memory use the chipset attached memory as a main memory during performance of of the boot up process for the apparatus by the chipset attached memory
Pelner teaches configured to: powering down a system (“The computer system is then automatically restarted” ¶36.) Powering down a system is a function inherent to restarting a system; and load a boot-up process in the chipset attached memory, the boot-up process configured to perform the boot-up process for the apparatus by the chipset attached memory. (“The term "boot", and associated terms such as "booting" and "boot up", as used herein, mean the process by which a computing device such as a computer system loads an operating system or operating system kernel into an operational memory, such as random access memory ("RAM") from a long-term storage memory, such as a read-only memory (ROM)“ ¶3, “Memory space 50 comprises software 100. Software 100 includes a bootloader 101, one or more component tests 102, an operating system (O/S) 103, and one or more applications 104” ¶25, “In FIG. 2, the software 100 can reside in any suitable machine-accessible media” ¶28, figures 4A-C, steps 320 ) use the chipset attached memory as a main memory during performance of (“Because ROM memory is typically slower than RAM, the BIOS is usually first loaded from ROM into RAM, and it is then executed from RAM… The BIOS may first test only the amount of RAM required to load the BIOS from ROM, and then check the remainder of RAM” ¶6).
Regarding claims 15, and 16, Poisner and Pelner teach the method of claim 11 as shown above, and these claims further recite the same limitations as claims 5 and 6 respectively. Therefore, they are rejected for the same reasons.
Regarding claim 17, Pelner teaches wherein the boot-up process is loaded in the chipset attached memory when the system is in a bypass mode, the bypass mode configured to bypass the system memory. (“Before loading the BIOS into RAM, it may test a memory controller located, for example, in the chipset.” ¶6).
Regarding claim 19, Poisner teaches a system comprising: a system memory managed by an operating system of the apparatus; a chipset attached memory comprising dynamic random-access memory,(“ Usually, there is substantially more physical address space supported than is needed to address the actual physical memory (e.g., SIMM (single inline memory module) or DIMM (dual inline memory module) DRAM (dynamic RAM)) installed in a system” ¶12); the chipset attached memory being separate from the system memory and managed by an application running on the apparatus (“According to embodiments of the invention, RAM in devices separate from the main memory ("separate RAM") may be used for a stack and temporary storage during BIOS execution. The separate RAM is typically dedicated, in its normal usage, to one or more functional logic blocks of a chipset.” ¶11); and responsive to completion of the boot-up process for the apparatus, use the system memory as the main memory (“Once the BIOS program has executed past a certain point, for example, once main memory is fully configured, the stack in separate RAM is no longer needed and normal chipset operations are possible. Accordingly, the CPU's stack pointer may be re-programmed to point to main memory” ¶28). Poisner does not teach configured to: power down the apparatus and load a boot-up process in the chipset attached memory, the boot-up process configured to perform the boot-up process for the apparatus by the chipset attached memory use the chipset attached memory as a main memory during performance of of the boot up process for the apparatus by the chipset attached memory
Pelner teaches configured to: power down the apparatus (“The computer system is then automatically restarted” ¶36.) Powering down a system is a function inherent to restarting a system; and load a boot-up process in the chipset attached memory, the boot-up process configured to perform the boot-up process for the apparatus by the chipset attached memory. (“The term "boot", and associated terms such as "booting" and "boot up", as used herein, mean the process by which a computing device such as a computer system loads an operating system or operating system kernel into an operational memory, such as random access memory ("RAM") from a long-term storage memory, such as a read-only memory (ROM)“ ¶3, “Memory space 50 comprises software 100. Software 100 includes a bootloader 101, one or more component tests 102, an operating system (O/S) 103, and one or more applications 104” ¶25, “In FIG. 2, the software 100 can reside in any suitable machine-accessible media” ¶28, figures 4A-C, steps 320 ) use the chipset attached memory as a main memory during performance of (“Because ROM memory is typically slower than RAM, the BIOS is usually first loaded from ROM into RAM, and it is then executed from RAM… The BIOS may first test only the amount of RAM required to load the BIOS from ROM, and then check the remainder of RAM” ¶6).
Regarding claim 21, Pelner teaches wherein the boot-up process loads one or more memory testing applications and tests the system memory using the one or more memory testing applications. (“. A sequence of tests is performed when the computer system is first turned on. The operation of various components of the computer system, such as a chip set, a random access memory (RAM)” ¶13).
Regarding claim 25, Poisner teaches wherein the application is configured to manage the chipset attached memory by issuing at least one of a read request or a write request to the chipset attached memory during the boot up process (“According to this embodiment, subsequent instructions of the BIOS program may now include operations on a stack, such as "push" or "pop" instructions for calling subroutines, to write to or read from the stack pointed to by the CPU's stack pointer.” ¶14).
Regarding claim 26, Poisner teaches wherein the application is configured to manage the chipset attached memory by issuing at least one of a read request or a write request to the chipset attached memory during the boot up process (“According to this embodiment, subsequent instructions of the BIOS program may now include operations on a stack, such as "push" or "pop" instructions for calling subroutines, to write to or read from the stack pointed to by the CPU's stack pointer.” ¶14).
Regarding claim 27, Poisner teaches wherein the application is configured to manage the chipset attached memory by issuing at least one of a read request or a write request to the chipset attached memory during the boot up process (“According to this embodiment, subsequent instructions of the BIOS program may now include operations on a stack, such as "push" or "pop" instructions for calling subroutines, to write to or read from the stack pointed to by the CPU's stack pointer.” ¶14).
Claims 4, 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Pelner (US 20030154428) and Poisner in view of Lui (10691570).
Regarding claim 4, Pelner and Poisner teach The apparatus of claim 3. Pelner does not teach wherein the one or more memory testing applications are further configured to report results of the testing by presenting the results of the testing on a user interface or incorporating the results of the testing into a file.
Lui teaches wherein the one or more memory testing applications are further configured to report results of the testing by presenting the results of the testing on a user interface (“After performing the memory test, the IVN self-test device 308 may then update the test configuration file with results of the memory test.” Column 7 lines 53-55); or incorporating the results of the testing into a file. (“Performing the memory test may identify defects and/or reliability issues of the IVN device 302, as indicated by the test configuration file. If a defect and/or a reliability issue is identified, the IVN self-test 308 may perform various mitigation (remediation) actions, such as remediating against those issues, alarms, reports, displays (e.g., on a graphical user interface (GUI))” Column 7 lines 45-50).
It would have been obvious to one of ordinary skill in the art prior to the filing of the claimed invention to include displaying test results with a GUI and writing them into a file as disclosed by Lui with the power on self-testing methods taught by Pelner. This would indicate whether the memory is operating correctly or display the erroneous behavior (Column 6 lines 64-67).
Regarding claim 14, Pelner and Raisch teach the method of claim 11 as shown above, and the claim recites the same limitations as claim 4 and is rejected under the same rationale.
Regarding claim 22, Lui teaches wherein the one or more memory testing applications are configured to output results of testing the system memory (“After performing the memory test, the IVN self-test device 308 may then update the test configuration file with results of the memory test”).
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Poisner and Pelner in view of Lu (US 20090144585).
Regarding claim 23, Poisner and Pelner do not teach wherein the boot-up process comprises loading one or more debugging or logging applications from the chipset attached memory
Lu teaches wherein the boot-up process comprises loading one or more debugging or logging applications from the chipset attached memory (“Firstly, a debugging routine is edited in a boot program (S10). Next, the BIOS executes the boot program with the debugging routine (S12).” ¶21). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the bootup process using chipset attached RAM taught by Poisner and Pelner with the performing of a debugging or logging program as taught by Lu. A debugging program during the execution of the BIOS would reduce the time and work required to detect and debug a BIOS (Lu ¶14).
Regarding claim 24, Lu teaches , further comprising a processing unit that executes the one or more debugging or logging applications during the boot-up process. (“Firstly, a debugging routine is edited in a boot program (S10). Next, the BIOS executes the boot program with the debugging routine (S12).” ¶21).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN KEVIN MCNAMARA whose telephone number is (703)756-1884. The examiner can normally be reached Monday-Friday 7:30-5:00 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN KEVIN MCNAMARA/ Examiner, Art Unit 2113
/PHILIP GUYTON/ Primary Examiner, Art Unit 2113