The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 2/5/2026.
Claims 1 and 25 are amended. Claims 7-20 have been withdrawn, claim 30 is new.
Claims 1-6 and 21-30 are pending.
Claims 1-6 and 21-30 are rejected.
Response to Arguments
Applicant`s arguments filed February 5, 2026 have been fully considered and they are persuasive with respect to prior art rejection.
As per the 103 rejection of claims 1 and 25, Applicant argued Sharon fails to disclose or suggest the feature of " wherein the metadata comprises latency information about the first memory device and the second memory device; and manage, based on the stored metadata and the latency information, processes"; where examiner relies on a newly cited reference Dubeyko to disclose the claimed limitation.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 1/30/2026, 04/01/2026, and 04/15/2026. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
9.The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1, 3-6, 21-23, 25-28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over BAE et al. (US PGPUB 2020/0081848, hereinafter "Bae"), in view of Li et al. (US 10,078,453) (hereinafter ‘Li’) in view of Janik et al. (US PGPUB 2016/0188221) (hereinafter ‘Janik’), in view of Dubeyko et al. (US PGPUB 2020/0257562) (hereinafter ‘Dubeyko’) and further in view of Klein et al. (US PGPUB 2014/0025923) (hereinafter ‘Klein’).
As per independent claim 1, Bae discloses a system comprising: a first memory device; a second memory device; at least one processing device [(Paragraphs 0117-0120 and 0146; FIGs.14 and 18) where the storage region 275 of a storage device 265 may include a memory device 280 having a relatively large capacity and a buffer memory 285 having a relatively small capacity and a relatively fast access time. The memory device 280 may also be referred to herein as a memory element, which is capable of storing data. For example, the memory device 280 may have a relatively larger capacity compared to the capacity of the buffer memory 285, and the access time of the buffer memory 285 may be relatively faster compared to the access time of the memory device 280. The storage device 265 and the storage region 275 may be identical or similar to the storage device 200 and the storage region 210 illustrated in FIG. 3, respectively to correspond to the claimed limitation]; and memory containing instructions configured to instruct the at least one processing device to: access memory in an address space [(Paragraphs 0039-0043; FIG.1) where the memory management unit 104 translates virtual addresses into physical addresses, and may perform functions such as, for example, memory protection, cache management and bus arbitration. Further, in exemplary embodiments, the memory management unit 104 may be responsible for bank switching in an 8-bit architecture. A kernel 110 may allocate hardware resources among processes as required. A kernel 110 is a component that performs, for example, process control, memory control, a system call required by a program for an operating system, etc., and may be operated under control of the operating system. The kernel 110 may also manage memory devices such as a main memory device and an auxiliary memory device in a virtual address space within the system. For example, when the host 100 accesses the devices, the host 100 may access the devices using the virtual addresses provided by the kernel 110 instead of the physical addresses. The kernel 110 may be included in the host 100. The virtual addresses allow for the system to effectively create a virtual memory space that is larger than the actual physical memory space. The process in which the actual physical memory space is divided into the virtual memory spaces is referred to as paging. The kernel 110 may utilize the memory management unit 104 to perform the translation between the virtual addresses and the physical addresses. The kernel 110 may manage the mapping unit of the virtual address spaces as pages of 2.sup.n bit size, e.g., 4 KB, where n is a natural number. Some virtual pages may be associated with a single page of physical addresses. When the host 100 issues a request for access, the CPU 130 may send the virtual address to the memory management unit 104. To access the data stored in the memory 124, a virtual address has to be translated into a physical address. To do so, the page table 150, which is a translation table stored in the system memory, may be utilized. The page table 150 has a large volume, and thus, the page table 150 may be stored in the system memory (e.g., memory management unit 104). The memory management unit 104 may translate the virtual addresses into the physical addresses]; store metadata [(Paragraphs 0008, 0039-0043, 0062-0065, 0090-0093 and 0144-0146; FIGs.1, 4 and 6) where the address prediction module 830 may have a learning capability for patterns of requests to be accessed from the host 100. That is, in exemplary embodiments, the address prediction module 830 may be configured to learn patterns of requests to be accessed from the host 100. The address prediction module 830 may build a database for physical addresses of data accessed from the host 100 to provide the learning capability. For example, the address prediction module 830 can detect a rule between the physical address of the currently accessed data and the physical address of the data to be accessed next. For example, the address prediction module 830 can recognize the rule among the physical addresses of data accessed up to the k.sup.th data of the physical addresses of the data in the database (e.g., a rule that physical addresses are incremented by four, such as first, fifth, ninth, etc.). The address prediction module 830 can predict that the (k+1).sup.th data to be accessed by the host 100 has the recognized rule with the physical address of the k.sup.th data. The address prediction module 830 may prefetch data having the physical address of the (k+1).sup.th data into another storage device 850 (for example, the main memory device) via the prefetcher 810. As a result, the response speed of the host 100 accessing the storage device 820 can be improved. In exemplary embodiments, the address prediction module 830 may regard the data accesses up to the k.sup.th data as a bulk read, and may prefetch the (k+1).sup.th data into another storage space (operations S330 and 350 of FIG. 6). If contiguous accesses or random but regular accesses occur less than k times, the predicted data may not be prefetched. According to exemplary embodiments, the accuracy of the next predicted data can be increased only when the access of the host 100 is repeated more than a predetermined number of times, and the predicted data may be prefetched only for the accesses regarded as the bulk read. Referring back to FIG. 4, the memory controller 215 prefetches the data predicted in operation S300 into another storage device such as, for example, the main memory device (operation S400). For example, referring to FIG. 3, once the address prediction module 225 of the memory controller 215 predicts the data to be accessed next by the host 100, the prefetcher 220 of the memory controller 215 may prefetch the predicted data into an external storage device such as, for example, the main memory device, which has a faster speed than the storage device 200. Further the kernel manages the mapping unit of virtual address spaces to correspond to the claimed limitation ]; manage, based on the stored metadata, processes including a first process and a second process, wherein data for the first process is stored in the first memory device [(Paragraphs 0044, 0048-0050; FIGs. 1) wherein the page table 150 may be a data structure used in the paging technique. The page table 150 may store page information of processes. Every process may have a single page table 150. The page table 150 may include indices corresponding to the page numbers, respectively. In addition, the page table 150 may store information containing a physical memory address allocated to the page. The operation of the page table 150 may be different depending on the architecture and the operating system, where the host 100 accesses the memory 124. The CPU 130 may check whether the page table 150 containing the translation information used to translate the virtual addresses into the physical addresses is in the translation lookaside buffer 108, which can be accessed quickly by the memory management unit 104. If the page table 150 containing translation information is in the translation lookaside buffer 108, the host 100 may access the memory 124 using the physical address translated through the page table 150 to correspond to the claimed limitation].
Bae does not appear to explicitly disclose a first memory device; a second memory device separate from the first memory device; at least one processing device; and memory separate from the first and second memory devices, the memory containing instructions, store metadata in the memory.
However, Lin discloses a first memory device; a second memory device separate from the first memory device [(Column 3, lines 50-67 and Column 4, lines 1-10; FIG. 1) wherein FIG. 1 illustrates an embodiment of a system 100 having one or more processor cores 102 and a system memory 104. The system 100 may utilize a hybrid storage device 103 comprising a first memory device 106 and a second memory device 108. The memory 104 includes one or more applications 110 issuing requests to create, write, modify and read files maintained by a hybrid file system 112. A hybrid device block storage driver 114 manages access to the first 106 and second 108 memory devices in the hybrid storage device 103, to present as a single contiguous logical address storage space to the hybrid file system 112. The hybrid device block storage driver 114 includes a first memory device driver 116 to interface with the first memory device 106 and a second memory device driver 118 to interface with the second memory device 108. During system 100 initialization, the hybrid device block storage driver 114 discovers a first memory device physical address range 120 and a second memory device physical address range 122, and presents a single contiguous logical address space based on the physical address ranges 120 and 122 of the first 106 and second 108 memory devices. The logical memory device address information 400 provides information on a single logical address range corresponding to the first 120 and second 122 memory device physical address ranges. The hybrid device block storage driver 114 further includes an address translator 126 to translate between the logical addresses defining a contiguous space of logical addresses and the first 120 and second 122 ranges of physical addresses to correspond to the claimed limitation]; and memory separate from the first and second memory devices, the memory containing instructions, store metadata in the memory [(Column 4, lines 1-20, Column 8, lines 1-20; FIG. 1) wherein the first 106 and second 108 memory devices include controllers 128 and 130, respectively, to manage requests for the memory devices 106 and 108, respectively. The first memory device data blocks 134 store file system metadata 200 providing information to perform file management operations and the file/directory metadata generated to represent files and directories in the hybrid file system 112; FIG. 8 illustrates an embodiment of operations performed by the hybrid file system 112 or a combination of the hybrid file system 112 and the hybrid device block storage driver 114 to perform a write to a data block at a logical address identified in a directory or file inode. Upon receiving (at block 800) a write request to a data block at a logical address identified in a directory or file inode 210, the logical address is converted (at block 802) to a physical address in the secondary memory device 108. The hybrid file system 112 updates (at block 804) the data block validity data structure 208 to indicate that the block/physical address for the logical address is invalid. The hybrid file system 112 increments (at block 806) the invalid block count 304 for the defragmentation unit 300.sub.i having the physical address to update, as indicated in the data block addresses 302 of the defragmentation unit 300.sub.i. The hybrid file system 112 in conjunction with the hybrid device block storage driver 114 performs (at block 808) the operations in FIG. 6 to obtain a new logical address for an updated data block to which to write the data to correspond to the claimed limitation].
Bae and Lin are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae and Lin before him or her, to modify the method of Bae to include the multiple separate devices of Lin because it will improve performance of read/write operations of the data storage device.
The motivation for doing so would be to [improved techniques for managing file system data and performing read and write operations (Column 2, lines 26-28 by Lin)].
Therefore, it would have been obvious to combine Bae and Lin to obtain the invention as specified in the instant claim.
Bae does not appear to explicitly disclose store metadata that associates a first address range of the address space with the first memory device.
However, Janik discloses store metadata that associates a first address range of the address space with the first memory device [(Paragraphs 0071; FIGs. 1) wherein the metadata may be stored at the storage layer 110, volatile resources 103, non-volatile storage resources 104 and/or storage medium 150, where it will be obvious to store the metadata which may include, but is not limited to: a forward map 125 comprising any-to-any mappings between LIDs of the logical address space 121 and the storage address space 151, a reverse map or validity map 127 pertaining to the contents of particular storage units 152 and/or storage divisions 154, and/or profiling metadata 129 pertaining to wear level(s) of the storage divisions 154, storage division error rate, storage performance metrics (e.g., latencies of erase and/or write operations), and so on. Portions of the storage metadata 124 may be maintained within the volatile memory resources 103 of the computing system 100 to correspond to the claimed limitation].
Bae and Janik are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae and Janik before him or her, to modify the method of Bae to include the metadata storage of Janik because it will improve reliability, endurance and/or throughput performance of the data storage device.
The motivation for doing so would be to [prolong the usable lifetime of the storage system (Paragraph 0003 by Janik)].
Bae/Janik does not appear to explicitly disclose wherein the metadata comprises latency information about the first memory device and the second memory device; and manage, based on the stored metadata and the latency information, processes.
However, Dubeyko discloses wherein the metadata comprises latency information about the first memory device and the second memory device; and manage, based on the stored metadata and the latency information, processes [(Paragraphs 0068-0072; FIGs. 1) wherein the virtual address space 700 includes a plurality of supersets 705A-705F. Although six supersets are shown in the virtual address space 700, the number of supersets may vary to be greater or fewer than six in other embodiments. Each of the supersets 705A-705F may be allocated memory based upon a memory latency (also referred to herein as “latency”) requirement of the applications 130 for completing operations associated with those respective applications. Memory latency is a critical factor that impacts performance of data processing. While each of the applications 130 may ideally desire a lowest memory latency possible (such that their operations are executed as fast as possible), practically speaking, not all types of operations necessarily benefit from a fastest execution. Thus, the operating system 150 may be configured to allocate memory based on memory latency, particularly when a maximum performance power consumption is desired. In some embodiments, memory latency may be classified into multiple categories as follows: no latency, some latency, low latency, high latency, and huge latency. “No latency” means completing execution of an operation in the order of picoseconds-nanoseconds. “Some latency” means completing execution of an operation in the order of nanoseconds, while “low latency” means completing execution of an operation in the order of nanoseconds-microseconds. A “high latency” means completing execution of an operation in the order of microseconds-milliseconds, while a “huge latency” means completing execution of an operation in the order of seconds. It is to be understood that the time units that define each latency category above may vary in other embodiments to correspond to the claimed limitation].
Bae/Janik and Dubeyko are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae/Janik and Dubeyko before him or her, to modify the method of Bae to include the metadata storage of Dubeyko because it will improve reliability, endurance and/or throughput performance of the data storage device.
The motivation for doing so would be to [ “the operating system 150 and the address space of the present disclosure provides the capability of storing supersets persistently and improving data processing performance” (Paragraph 0098 by Dubeyko)].
Bae/Janik does not appear to explicitly disclose wherein data for the first process is stored in the first memory device.
However, Klein discloses wherein data for the first process is stored in the first memory device [(Paragraphs 0004, 0017 and 0026-0028; FIGs. 1) wherein FIG. 3 illustrates a block diagram of the TLB 40 that may store data relating to how frequently a particular virtual memory address and/or physical memory address are accessed, and may store data that identifies a type of memory device corresponding to the particular physical memory address. In certain embodiments, the TLB 40 may be a content-addressable memory (CAM) device or n-way associative memory device. Specifically, the TLB 40 stores a table 42 having rows 44 and columns (46-52). In the present embodiment, each row 44 relates to a separate table entry. As such, each row 44 includes a virtual memory address column 46, a physical memory address column 48, a least recently used (LRU) column 50, and a device identification (TYPE) column 52 to correspond to the claimed limitation].
Bae/Janik and Klein are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae/Janik and Klein before him or her, to modify the method of Bae to include the metadata storage of Janik because it will improve reliability, endurance and/or throughput performance of the data storage device.
The motivation for doing so would be to [the memory management system 18 may identify whether table entries with a greater amount of use (e.g., higher access rates) are allocated to better memory types (e.g., faster memory, improved endurance) than table entries with a lower amount of use (Paragraph 0035 by Klein)].
Therefore, it would have been obvious to combine Bae and Janik to obtain the invention as specified in the instant claim.
As per claim 3, Klein discloses wherein: the first process corresponds to a first application; the instructions are further configured to instruct the at least one processing device to receive a request from the first application that indicates a type of memory to use for storing data; and the first memory device is selected to store the data for the first process based on the indicated type of memory [(Paragraphs 0019-0020, 0026-0028 and 0035-0037; FIGs. 1, 3 and 4) wherein the TLB 40 that may store data relating to how frequently a particular virtual memory address and/or physical memory address are accessed, and may store data that identifies a type of memory device corresponding to the particular physical memory address. In certain embodiments, the TLB 40 may be a content-addressable memory (CAM) device or n-way associative memory device. Specifically, the TLB 40 stores a table 42 having rows 44 and colunms (46-52), where each row 44 includes a virtual memory address colunm 46, a physical memory address colunm 48, a least recently used (LRU) colunm 50, and a device identification (TYPE) colunm52, where TLB stores table 42 that includes allocation information of addresses as a dedicated memory storage type for the application such that the memory management system 18 may compare the type of memory devices that are allocated to the identified entries to available types of memory devices. For example, the memory management system 18 may identify whether table entries with a greater amount of use ( e.g., higher access rates) are allocated to better memory types ( e.g., faster memory, improved endurance) than table entries with a lower amount of use to correspond to the claimed limitation].
As per claim 4, Klein discloses a buffer to store the metadata, wherein an operating system receives a virtual address in the first address range from the first process, and accesses the buffer to determine a physical address of the first memory device corresponding to the virtual address [(Paragraphs 0019-0020, 0026-0028 and 0035-0037; FIGs. 1, 3 and 4) wherein the TLB 40 that may store data relating to how frequently a particular virtual memory address and/or physical memory address are accessed, and may store data that identifies a type of memory device corresponding to the particular physical memory address. In certain embodiments, the TLB 40 may be a content-addressable memory (CAM) device or n-way associative memory device. Specifically, the TLB 40 stores a table 42 having rows 44 and colunms (46-52), where each row 44 includes a virtual memory address colunm 46, a physical memory address colunm 48, a least recently used (LRU) colunm 50, and a device identification (TYPE) colunm52, where TLB stores table 42 that includes allocation information of addresses as a dedicated memory storage type for the application such that the memory management system 18 may compare the type of memory devices that are allocated to the identified entries to available types of memory devices. For example, the memory management system 18 may identify whether table entries with a greater amount of use ( e.g., higher access rates) are allocated to better memory types ( e.g., faster memory, improved endurance) than table entries with a lower amount of use to correspond to the claimed limitation].
As per claim 5, Klein discloses wherein a read latency of the first memory device is less than a read latency of the second memory device [(Paragraphs 0019-0020, 0026-0028 and 0035-0037; FIGs. 1, 3 and 4) wherein One or more of the memory devices 20, 22, and 24 may be volatile memory which may include Dynamic Random Access Memory (DRAM), or it can be non-volatile memory which has less latency then DRAM to correspond to the claimed limitation].
Janik teaches wherein the instructions are further configured to instruct the at least one processing device to store the metadata in the first memory device [(Paragraphs 0071; FIGs. 1) wherein the metadata may be stored at the storage layer 110, volatile resources 103, non-volatile storage resources 104 and/or storage medium 150, where it will be obvious to store the metadata in the first memory device to correspond to the claimed limitation].
As per claim 6, Klein discloses a memory management unit configured to, when accessing the stored data for the first process, map a virtual address in the first address range to a physical address in the first memory device [(Paragraphs 0019-0020, 0026-0028 and 0035-0037; FIGs. 1, 3 and 4) wherein the TLB 40 that may store data relating to how frequently a particular virtual memory address and/or physical memory address are accessed, and may store data that identifies a type of memory device corresponding to the particular physical memory address. In certain embodiments, the TLB 40 may be a content-addressable memory (CAM) device or n-way associative memory device. Specifically, the TLB 40 stores a table 42 having rows 44 and colunms (46-52), where each row 44 includes a virtual memory address colunm 46, a physical memory address colunm 48, a least recently used (LRU) colunm 50, and a device identification (TYPE) colunm52, where TLB stores table 42 that includes allocation information of addresses as a dedicated memory storage type for the application such that the memory management system 18 may compare the type of memory devices that are allocated to the identified entries to available types of memory devices. For example, the memory management system 18 may identify whether table entries with a greater amount of use ( e.g., higher access rates) are allocated to better memory types ( e.g., faster memory, improved endurance) than table entries with a lower amount of use to correspond to the claimed limitation].
As per claim 21, Bae discloses wherein the address space is maintained by an operating system, and the processes are managed by the operating system based on the stored metadata [(Paragraphs 0039-0043; FIG.1) where the memory management unit 104 translates virtual addresses into physical addresses, and may perform functions such as, for example, memory protection, cache management and bus arbitration. Further, in exemplary embodiments, the memory management unit 104 may be responsible for bank switching in an 8-bit architecture. A kernel 110 may allocate hardware resources among processes as required. A kernel 110 is a component that performs, for example, process control, memory control, a system call required by a program for an operating system, etc., and may be operated under control of the operating system. The kernel 110 may also manage memory devices such as a main memory device and an auxiliary memory device in a virtual address space within the system. For example, when the host 100 accesses the devices, the host 100 may access the devices using the virtual addresses provided by the kernel 110 instead of the physical addresses. The kernel 110 may be included in the host 100. The virtual addresses allow for the system to effectively create a virtual memory space that is larger than the actual physical memory space. The process in which the actual physical memory space is divided into the virtual memory spaces is referred to as paging. The kernel 110 may utilize the memory management unit 104 to perform the translation between the virtual addresses and the physical addresses. The kernel 110 may manage the mapping unit of the virtual address spaces as pages of 2.sup.n bit size, e.g., 4 KB, where n is a natural number. Some virtual pages may be associated with a single page of physical addresses. When the host 100 issues a request for access, the CPU 130 may send the virtual address to the memory management unit 104. To access the data stored in the memory 124, a virtual address has to be translated into a physical address. To do so, the page table 150, which is a translation table stored in the system memory, may be utilized. The page table 150 has a large volume, and thus, the page table 150 may be stored in the system memory (e.g., memory management unit 104). The memory management unit 104 may translate the virtual addresses into the physical addresses].
As per claim 22, Bae discloses wherein the accessing includes accessing the first memory device and the second memory device using addresses in the address space [(Paragraphs 0039-0043; FIG.1) where the memory management unit 104 translates virtual addresses into physical addresses, and may perform functions such as, for example, memory protection, cache management and bus arbitration. Further, in exemplary embodiments, the memory management unit 104 may be responsible for bank switching in an 8-bit architecture. A kernel 110 may allocate hardware resources among processes as required. A kernel 110 is a component that performs, for example, process control, memory control, a system call required by a program for an operating system, etc., and may be operated under control of the operating system. The kernel 110 may also manage memory devices such as a main memory device and an auxiliary memory device in a virtual address space within the system. For example, when the host 100 accesses the devices, the host 100 may access the devices using the virtual addresses provided by the kernel 110 instead of the physical addresses. The kernel 110 may be included in the host 100. The virtual addresses allow for the system to effectively create a virtual memory space that is larger than the actual physical memory space. The process in which the actual physical memory space is divided into the virtual memory spaces is referred to as paging. The kernel 110 may utilize the memory management unit 104 to perform the translation between the virtual addresses and the physical addresses. The kernel 110 may manage the mapping unit of the virtual address spaces as pages of 2.sup.n bit size, e.g., 4 KB, where n is a natural number. Some virtual pages may be associated with a single page of physical addresses. When the host 100 issues a request for access, the CPU 130 may send the virtual address to the memory management unit 104. To access the data stored in the memory 124, a virtual address has to be translated into a physical address. To do so, the page table 150, which is a translation table stored in the system memory, may be utilized. The page table 150 has a large volume, and thus, the page table 150 may be stored in the system memory (e.g., memory management unit 104). The memory management unit 104 may translate the virtual addresses into the physical addresses to correspond to the claimed limitations].
As per claim 23, Bae discloses wherein a second address range of the address space is associated with the second memory device [(Paragraphs 0044, 0048-0050; FIGs. 1) wherein the page table 150 may be a data structure used in the paging technique. The page table 150 may store page information of processes. Every process may have a single page table 150. The page table 150 may include indices corresponding to the page numbers, respectively. In addition, the page table 150 may store information containing a physical memory address allocated to the page. The operation of the page table 150 may be different depending on the architecture and the operating system, where the host 100 accesses the memory 124. The CPU 130 may check whether the page table 150 containing the translation information used to translate the virtual addresses into the physical addresses is in the translation lookaside buffer 108, which can be accessed quickly by the memory management unit 104. If the page table 150 containing translation information is in the translation lookaside buffer 108, the host 100 may access the memory 124 using the physical address translated through the page table 150 to correspond to the claimed limitation].
As per claim 25, Bae discloses method comprising: accessing memory in an address space [(Paragraphs 0039-0043; FIG.1) where the memory management unit 104 translates virtual addresses into physical addresses, and may perform functions such as, for example, memory protection, cache management and bus arbitration. Further, in exemplary embodiments, the memory management unit 104 may be responsible for bank switching in an 8-bit architecture. A kernel 110 may allocate hardware resources among processes as required. A kernel 110 is a component that performs, for example, process control, memory control, a system call required by a program for an operating system, etc., and may be operated under control of the operating system. The kernel 110 may also manage memory devices such as a main memory device and an auxiliary memory device in a virtual address space within the system. For example, when the host 100 accesses the devices, the host 100 may access the devices using the virtual addresses provided by the kernel 110 instead of the physical addresses. The kernel 110 may be included in the host 100. The virtual addresses allow for the system to effectively create a virtual memory space that is larger than the actual physical memory space. The process in which the actual physical memory space is divided into the virtual memory spaces is referred to as paging. The kernel 110 may utilize the memory management unit 104 to perform the translation between the virtual addresses and the physical addresses. The kernel 110 may manage the mapping unit of the virtual address spaces as pages of 2.sup.n bit size, e.g., 4 KB, where n is a natural number. Some virtual pages may be associated with a single page of physical addresses. When the host 100 issues a request for access, the CPU 130 may send the virtual address to the memory management unit 104. To access the data stored in the memory 124, a virtual address has to be translated into a physical address. To do so, the page table 150, which is a translation table stored in the system memory, may be utilized. The page table 150 has a large volume, and thus, the page table 150 may be stored in the system memory (e.g., memory management unit 104). The memory management unit 104 may translate the virtual addresses into the physical addresses]; storing metadata [(Paragraphs 0008, 0039-0043, 0062-0065, 0090-0093 and 0144-0146; FIGs.1, 4 and 6) where the address prediction module 830 may have a learning capability for patterns of requests to be accessed from the host 100. That is, in exemplary embodiments, the address prediction module 830 may be configured to learn patterns of requests to be accessed from the host 100. The address prediction module 830 may build a database for physical addresses of data accessed from the host 100 to provide the learning capability. For example, the address prediction module 830 can detect a rule between the physical address of the currently accessed data and the physical address of the data to be accessed next. For example, the address prediction module 830 can recognize the rule among the physical addresses of data accessed up to the k.sup.th data of the physical addresses of the data in the database (e.g., a rule that physical addresses are incremented by four, such as first, fifth, ninth, etc.). The address prediction module 830 can predict that the (k+1).sup.th data to be accessed by the host 100 has the recognized rule with the physical address of the k.sup.th data. The address prediction module 830 may prefetch data having the physical address of the (k+1).sup.th data into another storage device 850 (for example, the main memory device) via the prefetcher 810. As a result, the response speed of the host 100 accessing the storage device 820 can be improved. In exemplary embodiments, the address prediction module 830 may regard the data accesses up to the k.sup.th data as a bulk read, and may prefetch the (k+1).sup.th data into another storage space (operations S330 and 350 of FIG. 6). If contiguous accesses or random but regular accesses occur less than k times, the predicted data may not be prefetched. According to exemplary embodiments, the accuracy of the next predicted data can be increased only when the access of the host 100 is repeated more than a predetermined number of times, and the predicted data may be prefetched only for the accesses regarded as the bulk read. Referring back to FIG. 4, the memory controller 215 prefetches the data predicted in operation S300 into another storage device such as, for example, the main memory device (operation S400). For example, referring to FIG. 3, once the address prediction module 225 of the memory controller 215 predicts the data to be accessed next by the host 100, the prefetcher 220 of the memory controller 215 may prefetch the predicted data into an external storage device such as, for example, the main memory device, which has a faster speed than the storage device 200. Further the kernel manages the mapping unit of virtual address spaces to correspond to the claimed limitation].
Bae/Janik does not appear to explicitly disclose storing metadata in the memory, wherein information in the metadata associates an address range of the address space with at least two separate memory devices.
However, Lin discloses storing metadata in the memory, wherein information in the metadata associates an address range of the address space with at least two separate memory devices [(Column 3, lines 50-67 and Column 4, lines 1-10; FIG. 1) wherein FIG. 1 illustrates an embodiment of a system 100 having one or more processor cores 102 and a system memory 104. The system 100 may utilize a hybrid storage device 103 comprising a first memory device 106 and a second memory device 108. The memory 104 includes one or more applications 110 issuing requests to create, write, modify and read files maintained by a hybrid file system 112. A hybrid device block storage driver 114 manages access to the first 106 and second 108 memory devices in the hybrid storage device 103, to present as a single contiguous logical address storage space to the hybrid file system 112. The hybrid device block storage driver 114 includes a first memory device driver 116 to interface with the first memory device 106 and a second memory device driver 118 to interface with the second memory device 108. During system 100 initialization, the hybrid device block storage driver 114 discovers a first memory device physical address range 120 and a second memory device physical address range 122, and presents a single contiguous logical address space based on the physical address ranges 120 and 122 of the first 106 and second 108 memory devices. The logical memory device address information 400 provides information on a single logical address range corresponding to the first 120 and second 122 memory device physical address ranges. The hybrid device block storage driver 114 further includes an address translator 126 to translate between the logical addresses defining a contiguous space of logical addresses and the first 120 and second 122 ranges of physical addresses to correspond to the claimed limitation; (Column 4, lines 1-20, Column 8, lines 1-20; FIG. 1) wherein the first 106 and second 108 memory devices include controllers 128 and 130, respectively, to manage requests for the memory devices 106 and 108, respectively. The first memory device data blocks 134 store file system metadata 200 providing information to perform file management operations and the file/directory metadata generated to represent files and directories in the hybrid file system 112; FIG. 8 illustrates an embodiment of operations performed by the hybrid file system 112 or a combination of the hybrid file system 112 and the hybrid device block storage driver 114 to perform a write to a data block at a logical address identified in a directory or file inode. Upon receiving (at block 800) a write request to a data block at a logical address identified in a directory or file inode 210, the logical address is converted (at block 802) to a physical address in the secondary memory device 108. The hybrid file system 112 updates (at block 804) the data block validity data structure 208 to indicate that the block/physical address for the logical address is invalid. The hybrid file system 112 increments (at block 806) the invalid block count 304 for the defragmentation unit 300.sub.i having the physical address to update, as indicated in the data block addresses 302 of the defragmentation unit 300.sub.i. The hybrid file system 112 in conjunction with the hybrid device block storage driver 114 performs (at block 808) the operations in FIG. 6 to obtain a new logical address for an updated data block to which to write the data to correspond to the claimed limitation].
Bae/Janik/Klein and Lin are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae/Janik/Klein and Lin before him or her, to modify the method of Lin to include the multiple separate devices of Janik because it will improve performance of read/write operations of the data storage device.
The motivation for doing so would be to [improved techniques for managing file system data and performing read and write operations (Column 2, lines 26-28 by Lin)].
Therefore, it would have been obvious to combine Bae/Janik and Lin to obtain the invention as specified in the instant claim.
Bae does not appear to explicitly disclose store metadata that associates an address range of the address space with at least one memory device.
However, Janik discloses store metadata that associates an address range of the address space with at least one memory device [(Paragraphs 0071; FIGs. 1) wherein the metadata may be stored at the storage layer 110, volatile resources 103, non-volatile storage resources 104 and/or storage medium 150, where it will be obvious to store the metadata which may include, but is not limited to: a forward map 125 comprising any-to-any mappings between LIDs of the logical address space 121 and the storage address space 151, a reverse map or validity map 127 pertaining to the contents of particular storage units 152 and/or storage divisions 154, and/or profiling metadata 129 pertaining to wear level(s) of the storage divisions 154, storage division error rate, storage performance metrics (e.g., latencies of erase and/or write operations), and so on. Portions of the storage metadata 124 may be maintained within the volatile memory resources 103 of the computing system 100 to correspond to the claimed limitation].
Bae and Janik are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae and Janik before him or her, to modify the method of Bae to include the metadata storage of Janik because it will improve reliability, endurance and/or throughput performance of the data storage device.
The motivation for doing so would be to [prolong the usable lifetime of the storage system (Paragraph 0003 by Janik)].
Bae/Janik does not appear to explicitly disclose managing, based on the stored metadata, processes.
However, Klein discloses and managing, based on the stored metadata, processes [(Paragraphs 0004, 0017 and 0026-0028; FIGs. 1) wherein FIG. 3 illustrates a block diagram of the TLB 40 that may store data relating to how frequently a particular virtual memory address and/or physical memory address are accessed, and may store data that identifies a type of memory device corresponding to the particular physical memory address. In certain embodiments, the TLB 40 may be a content-addressable memory (CAM) device or n-way associative memory device. Specifically, the TLB 40 stores a table 42 having rows 44 and columns (46-52). In the present embodiment, each row 44 relates to a separate table entry. As such, each row 44 includes a virtual memory address column 46, a physical memory address column 48, a least recently used (LRU) column 50, and a device identification (TYPE) column 52 to correspond to the claimed limitation].
Bae/Janik and Klein are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae/Janik and Klein before him or her, to modify the method of Bae to include the metadata storage of Janik because it will improve reliability, endurance and/or throughput performance of the data storage device.
The motivation for doing so would be to [the memory management system 18 may identify whether table entries with a greater amount of use (e.g., higher access rates) are allocated to better memory types (e.g., faster memory, improved endurance) than table entries with a lower amount of use (Paragraph 0035 by Klein)].
Bae/Janik does not appear to explicitly disclose wherein the metadata comprises latency information about the at least two separate memory devices.
However, Dubeyko discloses wherein the metadata comprises latency information about the at least two separate memory devices [(Paragraphs 0068-0072; FIGs. 1) wherein the virtual address space 700 includes a plurality of supersets 705A-705F. Although six supersets are shown in the virtual address space 700, the number of supersets may vary to be greater or fewer than six in other embodiments. Each of the supersets 705A-705F may be allocated memory based upon a memory latency (also referred to herein as “latency”) requirement of the applications 130 for completing operations associated with those respective applications. Memory latency is a critical factor that impacts performance of data processing. While each of the applications 130 may ideally desire a lowest memory latency possible (such that their operations are executed as fast as possible), practically speaking, not all types of operations necessarily benefit from a fastest execution. Thus, the operating system 150 may be configured to allocate memory based on memory latency, particularly when a maximum performance power consumption is desired. In some embodiments, memory latency may be classified into multiple categories as follows: no latency, some latency, low latency, high latency, and huge latency. “No latency” means completing execution of an operation in the order of picoseconds-nanoseconds. “Some latency” means completing execution of an operation in the order of nanoseconds, while “low latency” means completing execution of an operation in the order of nanoseconds-microseconds. A “high latency” means completing execution of an operation in the order of microseconds-milliseconds, while a “huge latency” means completing execution of an operation in the order of seconds. It is to be understood that the time units that define each latency category above may vary in other embodiments to correspond to the claimed limitation].
Bae/Janik and Dubeyko are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae/Janik and Dubeyko before him or her, to modify the method of Bae to include the metadata storage of Dubeyko because it will improve reliability, endurance and/or throughput performance of the data storage device.
The motivation for doing so would be to [ “the operating system 150 and the address space of the present disclosure provides the capability of storing supersets persistently and improving data processing performance” (Paragraph 0098 by Dubeyko)].
Therefore, it would have been obvious to combine Bae and Janik to obtain the invention as specified in the instant claim.
As per claim 26, Klein discloses wherein the at least two separate memory device includes a non-volatile memory device and a volatile memory device [(Paragraphs 0019-0020, 0026-0028 and 0035-0037; FIGs. 1, 3 and 4) wherein One or more of the memory devices 20, 22, and 24 may be volatile memory which may include Dynamic Random Access Memory (DRAM), or it can be non-volatile memory which has less latency then DRAM to correspond to the claimed limitation; Bae further discloses [(Paragraphs 0117-0120 and 0146; FIGs.14 and 18) where the storage region 275 of a storage device 265 may include a memory device 280 having a relatively large capacity and a buffer memory 285 having a relatively small capacity and a relatively fast access time. The memory device 280 may also be referred to herein as a memory element, which is capable of storing data. For example, the memory device 280 may have a relatively larger capacity compared to the capacity of the buffer memory 285, and the access time of the buffer memory 285 may be relatively faster compared to the access time of the memory device 280. The storage device 265 and the storage region 275 may be identical or similar to the storage device 200 and the storage region 210 illustrated in FIG. 3].
As per claim 27, Bae discloses wherein the at least two separate memory device includes a first memory device and a second memory device, and the first memory device is faster than the second memory device [(Paragraphs 0117-0120 and 0146; FIGs.14 and 18) where the storage region 275 of a storage device 265 may include a memory device 280 having a relatively large capacity and a buffer memory 285 having a relatively small capacity and a relatively fast access time. The memory device 280 may also be referred to herein as a memory element, which is capable of storing data. For example, the memory device 280 may have a relatively larger capacity compared to the capacity of the buffer memory 285, and the access time of the buffer memory 285 may be relatively faster compared to the access time of the memory device 280. The storage device 265 and the storage region 275 may be identical or similar to the storage device 200 and the storage region 210 illustrated in FIG. 3, respectively to correspond to the claimed limitation].
As per claim 28, Janik discloses wherein the address range is a first address range associated with non-volatile memory, and the metadata further associates a second address range of the address space with volatile memory [(Paragraphs 0071; FIGs. 1) wherein the metadata may be stored at the storage layer 110, volatile resources 103, non-volatile storage resources 104 and/or storage medium 150, where it will be obvious to store the metadata which may include, but is not limited to: a forward map 125 comprising any-to-any mappings between LIDs of the logical address space 121 and the storage address space 151, a reverse map or validity map 127 pertaining to the contents of particular storage units 152 and/or storage divisions 154, and/or profiling metadata 129 pertaining to wear level(s) of the storage divisions 154, storage division error rate, storage performance metrics (e.g., latencies of erase and/or write operations), and so on. Portions of the storage metadata 124 may be maintained within the volatile memory resources 103 of the computing system 100 to correspond to the claimed limitation].
As per claim 30, Dubeyko discloses wherein the data for the first process is stored in the first memory device based on a determination, using the latency information by the at least one processing device that the first memory device has a lower latency than the second memory device [(Paragraphs 0068-0072; FIGs. 1) wherein the virtual address space 700 includes a plurality of supersets 705A-705F. Although six supersets are shown in the virtual address space 700, the number of supersets may vary to be greater or fewer than six in other embodiments. Each of the supersets 705A-705F may be allocated memory based upon a memory latency (also referred to herein as “latency”) requirement of the applications 130 for completing operations associated with those respective applications. Memory latency is a critical factor that impacts performance of data processing. While each of the applications 130 may ideally desire a lowest memory latency possible (such that their operations are executed as fast as possible), practically speaking, not all types of operations necessarily benefit from a fastest execution. Thus, the operating system 150 may be configured to allocate memory based on memory latency, particularly when a maximum performance power consumption is desired. In some embodiments, memory latency may be classified into multiple categories as follows: no latency, some latency, low latency, high latency, and huge latency. “No latency” means completing execution of an operation in the order of picoseconds-nanoseconds. “Some latency” means completing execution of an operation in the order of nanoseconds, while “low latency” means completing execution of an operation in the order of nanoseconds-microseconds. A “high latency” means completing execution of an operation in the order of microseconds-milliseconds, while a “huge latency” means completing execution of an operation in the order of seconds. It is to be understood that the time units that define each latency category above may vary in other embodiments to correspond to the claimed limitation].
Claims 2 and 29 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bae in view of Li in view of Janik in view of Klein, as applied to claims 1 above, and further in view of Talwar et al. (US PGPUB 2018/0004456) (hereinafter ‘Talwar’).
As per dependent claim 2, Bae/Janik discloses the method of claim 1.
Bae does not appear to explicitly disclose wherein the first process has a first priority, the second process has a second priority, and the first memory device is selected to store the data for the first process in response to determining that the first priority is higher than the second priority.
Talwar discloses wherein the first process has a first priority, the second process has a second priority [(Paragraphs 0011, 0040-0044; FIGs. 1 and 6) wherein the monitoring system 600 may track particular system values or parameters relevant to a particular application SLA requirement, such as available memory or processing bandwidth or according to any other metric specified by an application SLA requirement. The monitoring system 600 may receive a violation notification from application with a violated SLA requirement, as the application itself may monitor whether the computing system 601 is meeting its SLA requirements, where the monitoring system 600 may specify that memory access traffic from any application be assigned a non-elevated priority level, e.g., a best effort priority level. In that regard, the monitoring system 600 may instruct corresponding elements of the computing system 601 to label and process memory access requests at the non-elevated priority level. In this initial state, the memory network 100 may treat memory access requests from applications executing in the computing system 601 as best effort memory traffic and process the memory access requests accordingly. In this continuing illustration, the non-elevated priority level is referred to as priority P.sub.2, which may be the lowest memory access priority level supported by the computing system 601 and the monitoring system 600 may elevate the memory access priority level of an application, e.g., the particular application with a violated SLA requirement possibly caused by memory access contention for the shared memory 201 or in the memory network 100. The monitoring system 600 may assign an elevated priority for the affected application, which is referred to as P.sub.1 in this continuing illustration. To elevate the priority of the affected application, the monitoring system 600 may instruct elements of the computing system 601 to label memory access traffic for the affected application as elevated priority level P.sub.1. For example, the monitoring system 600 may identify the specific memory address range in the shared memory 201 used by the affected application as an elevated priority memory address range. The monitoring system 600 may further instruct memory controllers of the compute nodes, the memory network 100, and/or other elements of the computing system 601 to label memory access traffic with a target memory address in the elevated priority memory address range as elevated priority P.sub.1. Along similar lines, for node-based labeling schemes, the monitoring system 600 may identify and indicate elevated priority nodes to elements of the computing system 601, thus causing the computing system 601 treat memory access traffic involving the elevated priority nodes to be labeled as elevated priority P.sub.1. Thus, in the second state, the memory network 100 may prioritize handling of memory access traffic for the affected application, e.g., via a weighted round robin arbitration of selection of queues 320 in the memory network 100 to process memory access requests to correspond to the claimed limitation], and the first memory device is selected to store the data for the first process in response to determining that the first priority is higher than the second priority [(Paragraphs 0011, 0040-0047; FIGs. 1 and 6) wherein the monitoring system 600 may track particular system values or parameters relevant to a particular application SLA requirement, such as available memory or processing bandwidth or according to any other metric specified by an application SLA requirement. The monitoring system 600 may receive a violation notification from application with a violated SLA requirement, as the application itself may monitor whether the computing system 601 is meeting its SLA requirements, where the monitoring system 600 may specify that memory access traffic from any application be assigned a non-elevated priority level, e.g., a best effort priority level. In that regard, the monitoring system 600 may instruct corresponding elements of the computing system 601 to label and process memory access requests at the non-elevated priority level. In this initial state, the memory network 100 may treat memory access requests from applications executing in the computing system 601 as best effort memory traffic and process the memory access requests accordingly. In this continuing illustration, the non-elevated priority level is referred to as priority P.sub.2, which may be the lowest memory access priority level supported by the computing system 601 and the monitoring system 600 may elevate the memory access priority level of an application, e.g., the particular application with a violated SLA requirement possibly caused by memory access contention for the shared memory 201 or in the memory network 100. The monitoring system 600 may assign an elevated priority for the affected application, which is referred to as P.sub.1 in this continuing illustration. To elevate the priority of the affected application, the monitoring system 600 may instruct elements of the computing system 601 to label memory access traffic for the affected application as elevated priority level P.sub.1. For example, the monitoring system 600 may identify the specific memory address range in the shared memory 201 used by the affected application as an elevated priority memory address range. The monitoring system 600 may further instruct memory controllers of the compute nodes, the memory network 100, and/or other elements of the computing system 601 to label memory access traffic with a target memory address in the elevated priority memory address range as elevated priority P.sub.1. Along similar lines, for node-based labeling schemes, the monitoring system 600 may identify and indicate elevated priority nodes to elements of the computing system 601, thus causing the computing system 601 treat memory access traffic involving the elevated priority nodes to be labeled as elevated priority P.sub.1. Thus, in the second state, the memory network 100 may prioritize handling of memory access traffic for the affected application, e.g., via a weighted round robin arbitration of selection of queues 320 in the memory network 100 to process memory access requests to correspond to the claimed limitation].
Bae and Talwar are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae and Talwar before him or her, to modify the method of Bae to include the allocation of the process data based on priority of Talwar because it will increase efficiency and effectiveness in accessing a shared memory in a computing system.
The motivation for doing so would be to [increased efficiency and effectiveness in accessing a shared memory in a computing system and support differentiated memory access service to, for examples, applications requiring different service levels of memory access (Paragraph 0011 by Talwar)].
Therefore, it would have been obvious to combine Bae and Talwar to obtain the invention as specified in the instant claim.
As per claim 29, Talwar discloses receiving, from an application, a request for an indication of latency associated with the memory device [(Paragraphs 0011, 0040-0044; FIGs. 1 and 6) wherein the monitoring system 600 may track particular system values or parameters relevant to a particular application SLA requirement, such as available memory or processing bandwidth or according to any other metric specified by an application SLA requirement. The monitoring system 600 may receive a violation notification from application with a violated SLA requirement, as the application itself may monitor whether the computing system 601 is meeting its SLA requirements, where the monitoring system 600 may specify that memory access traffic from any application be assigned a non-elevated priority level, e.g., a best effort priority level, where the monitoring and tracking by the monitoring system 600 to provide the application with proper SLA requirement to allocate the best-suited address range to the application to correspond to the claimed limitation. In that regard, the monitoring system 600 may instruct corresponding elements of the computing system 601 to label and process memory access requests at the non-elevated priority level. In this initial state, the memory network 100 may treat memory access requests from applications executing in the computing system 601 as best effort memory traffic and process the memory access requests accordingly. In this continuing illustration, the non-elevated priority level is referred to as priority P.sub.2, which may be the lowest memory access priority level supported by the computing system 601 and the monitoring system 600 may elevate the memory access priority level of an application, e.g., the particular application with a violated SLA requirement possibly caused by memory access contention for the shared memory 201 or in the memory network 100. The monitoring system 600 may assign an elevated priority for the affected application, which is referred to as P.sub.1 in this continuing illustration. To elevate the priority of the affected application, the monitoring system 600 may instruct elements of the computing system 601 to label memory access traffic for the affected application as elevated priority level P.sub.1. For example, the monitoring system 600 may identify the specific memory address range in the shared memory 201 used by the affected application as an elevated priority memory address range. The monitoring system 600 may further instruct memory controllers of the compute nodes, the memory network 100, and/or other elements of the computing system 601 to label memory access traffic with a target memory address in the elevated priority memory address range as elevated priority P.sub.1. Along similar lines, for node-based labeling schemes, the monitoring system 600 may identify and indicate elevated priority nodes to elements of the computing system 601, thus causing the computing system 601 treat memory access traffic involving the elevated priority nodes to be labeled as elevated priority P.sub.1. Thus, in the second state, the memory network 100 may prioritize handling of memory access traffic for the affected application, e.g., via a weighted round robin arbitration of selection of queues 320 in the memory network 100 to process memory access requests to correspond to the claimed limitation].
Claim 24 is rejected under 35 U.S.C. 103(a) as being unpatentable over Bae in view of Li in view of Janik in view of Klein, as applied to claims 1 above, and further in view of Mamidala et al. (US PGPUB 2013/0326180) (hereinafter ‘Mamidala’).
As per dependent claim 24, Bae/Janik discloses the method of claim 1.
Bae does not appear to explicitly disclose wherein data for the second process is stored in the second memory device.
Mamidala discloses wherein data for the second process is stored in the second memory device [(Paragraphs 0008-0009 and 0024-0026; FIGs. 1 and 2) wherein Mamidala teaches method, in one aspect, may include allocating a bucket comprising a memory array and hardware control logic that supports message passing interface semantics, for communicating data between a first process on a first memory domain and a second process on a second memory domain, wherein the first memory domain and the second memory domain are not shared, and wherein the bucket is not part of the first memory domain or the second memory domain. FIG. 1 illustrates components of a multi-nodelet chip in one embodiment of the present disclosure. Multiple nodelets (e.g., 104, 106) may be integrated in a chip 102. Each nodelet (e.g., 104, 106) may have one or more homogeneous or heterogeneous processor cores. Each nodelet (e.g., 104, 106) also has its separate memory system. Memory between nodelets (e.g., 104, 106) is not shared. Nodelets (e.g., 104, 106) participate in a larger multi-node system using network connections 114 and the MPI protocol. Messages from a process within a nodelet to other processes located on different chips are sent vie network interface and network. Messages from a process within a nodelet to another process in a different nodelet on the same chip is not preformed via the network but by exchanging messages in the point-to-point messaging buckets (e.g., 108, 110, 112) between the nodelets. In one embodiment, point-to-point messaging buckets (e.g., 108, 110, 112) are used for transferring MPI data between the nodelets (e.g., 104, 106) on the same chip 102. A bucket (e.g., 108, 110, 112) comprises memory space and hardware control logic that obeys messaging protocol such as MPI, and can be used by all nodelets on the chip to transfer messages from one nodelet to another nodelet on the same chip to correspond to the claimed limitation].
Bae and Mamidala are analogous art because they are from the same field of endeavor of memory management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Bae and Mamidala before him or her, to modify the method of Bae to include the allocation of the process data to memory devices of Mamidala because it will increase efficiency and effectiveness in accessing a shared memory in a computing system.
The motivation for doing so would be to [to have fast and efficient way of communicating between the local nodes (Paragraph 0022 by Mamidala)].
Therefore, it would have been obvious to combine Bae and Mamidala to obtain the invention as specified in the instant claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED M GEBRILohamed Gebril whose telephone number is (571)270-1857 and email address is mohamed.gebril @uspto.gov. The examiner can normally be reached on Monday-Friday 9-5 ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
Prosecution Insights