DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6-11, and 16-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Henderson (US 2021/0215807 A1).
Regarding Claim 1, Henderson discloses a depth sensing system ([0002], [0003]), comprising:
a plurality of photon sensors for detecting photons during an exposure window after a laser event (Figure 1; [0027]);
a plurality of event registers configured to store photon-detection events detected by the plurality of photon sensors during the exposure window ([0028]: “a Light Detection and Ranging (LIDAR) detector circuit includes one or more photodetector elements defining a LIDAR detector pixel, a buffer memory device, a main memory device, and at least one processor circuit. The at least one processor circuit is configured to execute first and second memory storage operations to store data indicated by detection signals received from the LIDAR detector pixel in the buffer and main memory devices during first and second portions of a time between pulses of a LIDAR emitter signal; [0030]: “ the at least one processor circuit may include a sampler circuit that is configured to execute the first memory storage operations to sample the data from the detection signals at a predetermined sampling rate and write the data to respective bins of the buffer memory device.” The buffer memory here satisfies the limitation of an event register under the broadest reasonable interpretation.);
an SRAM ([0021]: “the second memory may be static random access memory (SRAM)”) disposed under the plurality of photon sensors (The memory must necessarily be beneath the detectors in the configuration of Henderson (e.g., Figure 4A1)), the SRAM comprising: a plurality of memory cells associated with each photon sensor of the plurality of photon sensors ([0032]: “each of the LIDAR detector pixels may be associated with a respective buffer memory device and a respective main memory device.”), wherein the plurality of memory cells is configured to store a histogram of photon-detection events detected by the associated photon sensor during the exposure window ([0030]: “The respective bins of the main memory device may include histogram data for an imaging distance subrange corresponding to the strobe window.”), and each memory cell of the plurality of memory cells is configured to store photon-detection events detected during a predetermined time period after the laser event ([0007]: “In addition, thousands of time bins (each corresponding to respective photon arrival times) may typically be used to form a histogram sufficient to cover the typical time range of a LIDAR system”);
and an in-memory incrementor configured to update the plurality of memory cells based on the photon-detection events stored by the plurality of event registers, wherein for each of the photon-detection events stored in the plurality of event registers ([0083]), the in-memory incrementor is configured to read an event count stored in a selected one of the plurality of memory cells, increment the event count, and write the incremented event count back to the selected memory cell ([0083]: “ For example, in a precharge-read-modify-write operation, the current contents of a given histogram bin, which may be indexed by the clock period, are readout and added to the data stored in a corresponding bin of the buffer memory device 305b. The result (e.g., H<n−1:0>) may then be written back to the respective histogram bin of the main memory device 305a.”).
Regarding Claim 2, which depends from rejected Claim 1, Henderson further discloses wherein the plurality of memory cells and the in-memory incrementor are coupled to a row decoder and a column decoder to decode a row address and a column address for each of the plurality of memory cells associated with each photon sensor of the plurality of photon sensors ([0101]: “In some embodiments, a readout signal may be output responsive to a read signal that is sequentially applied to respective rows (or columns) of the main memory 605a, and may be used to calculate an estimated time of arrival of photons incident on the photodetector elements.”).
Regarding Claim 6, which depends from rejected Claim 1, Henderson further discloses wherein the SRAM disposed under the plurality of photon sensors performs one or more operations on SRAM values for the plurality of memory cells using the event count stored in the plurality of memory cells ([0083]: “ For example, in a precharge-read-modify-write operation, the current contents of a given histogram bin, which may be indexed by the clock period, are readout and added to the data stored in a corresponding bin of the buffer memory device 305b. The result (e.g., H<n−1:0>) may then be written back to the respective histogram bin of the main memory device 305a.”).
Regarding Claim 7, which depends from rejected Claim 6, Henderson further discloses wherein the one or more operations include a read operation, a write operation, a fresh operation, and an update operation ([0083]: “ For example, in a precharge-read-modify-write operation, the current contents of a given histogram bin, which may be indexed by the clock period, are readout and added to the data stored in a corresponding bin of the buffer memory device 305b. The result (e.g., H<n−1:0>) may then be written back to the respective histogram bin of the main memory device 305a.” Under the broadest reasonable interpretation of ‘fresh operation’, the examiner identifies this with the precharge operation. Applicant’s ‘fresh operation’ nomenclature is in analogy to the DRAM ‘refresh operation’ and indicates setting voltages to a known value for the first time before read/write operations.).
Regarding Claim 8, which depends from rejected Claim 6, Henderson further discloses wherein the one or more operations are performed using row/column address for each of the plurality of memory cells ([0101]: “In some embodiments, a readout signal may be output responsive to a read signal that is sequentially applied to respective rows (or columns) of the main memory 605a, and may be used to calculate an estimated time of arrival of photons incident on the photodetector elements.”).
Regarding Claim 9, which depends from rejected Claim 1, Henderson further discloses wherein the SRAM disposed under the plurality of photon sensors determines a direct time to flight using a time to digital converter ([0007]; [0062]: “The detectors 110d include time-of-flight sensors (for example, an array of single-photon detectors, such as SPADs).”) based on the histogram of photon-detection events detected by the associated photon sensor during the exposure window ([0018]: ”The respective bins of the second memory may include histogram data for an imaging distance subrange corresponding to the strobe window.”).
Regarding Claim 10, which depends from rejected Claim 1, Henderson further discloses wherein the SRAM disposed under the plurality of photon sensors is coupled to a global synchronous clock ([0058]: “some embodiments may provide processing and/or control circuits that are configured to store photon counts (e.g., SPAD photon counts, as a log 2(k)-bit number) during a strobe window into a temporary memory (e.g., a buffer memory, such as an SRAM buffer, with a number of bins n) at or within the shorter clock cycle (e.g., less than 5 ns).” The SRAM is coupled to a clock.) that re-times all input logic ([0058] The main memory can be accessed at a shorter clock rate, which is identified with re-timing input logic under the broadest reasonable interpretation).
Regarding Claim 11, Henderson discloses the method for detecting photons ([0002], [0003]), comprising:
detecting photons during an exposure window after a laser event using a plurality of photon sensors (Figure 1; [0027]);
determining photon-detection events detected by the plurality of photon sensors during the exposure window using a plurality of event registers ([0028]: “a Light Detection and Ranging (LIDAR) detector circuit includes one or more photodetector elements defining a LIDAR detector pixel, a buffer memory device, a main memory device, and at least one processor circuit. The at least one processor circuit is configured to execute first and second memory storage operations to store data indicated by detection signals received from the LIDAR detector pixel in the buffer and main memory devices during first and second portions of a time between pulses of a LIDAR emitter signal; [0030]: “ the at least one processor circuit may include a sampler circuit that is configured to execute the first memory storage operations to sample the data from the detection signals at a predetermined sampling rate and write the data to respective bins of the buffer memory device.” The buffer memory here satisfies the limitation of an event register under the broadest reasonable interpretation.);
determining a histogram of photon-detection events detected by the associated photon sensor during the exposure window using an SRAM ([0021]: “the second memory may be static random access memory (SRAM)”) disposed under the plurality of photon sensors (The memory must necessarily be beneath the detectors in the configuration of Henderson (e.g., Figure 4A1)), wherein the SRAM comprises a plurality of memory cells associated with each photon sensor of the plurality of photon sensors ([0032]: “each of the LIDAR detector pixels may be associated with a respective buffer memory device and a respective main memory device.”), and each memory cell of the plurality of memory cells is configured to store photon-detection events detected during a predetermined time period after the laser event ([0007]: “In addition, thousands of time bins (each corresponding to respective photon arrival times) may typically be used to form a histogram sufficient to cover the typical time range of a LIDAR system”); and
updating the plurality of memory cells and the histogram based on the photon-detection events stored by the plurality of event registers using an in-memory incrementor, wherein for each of the photon-detection events stored in the plurality of event registers ([0083]), the in-memory incrementor is configured to read an event count stored in a selected one of the plurality of memory cells, increment the event count, and write the incremented event count back to the selected memory cell ([0083]: “ For example, in a precharge-read-modify-write operation, the current contents of a given histogram bin, which may be indexed by the clock period, are readout and added to the data stored in a corresponding bin of the buffer memory device 305b. The result (e.g., H<n−1:0>) may then be written back to the respective histogram bin of the main memory device 305a.”).
Regarding Claim 12, which depends from rejected Claim 11, Henderson further discloses coupling the plurality of memory cells and the in-memory incrementor to a row decoder and a column decoder to decode a row address and a column address for each of the plurality of memory cells associated with each photon sensor of the plurality of photon sensors ([0101]: “In some embodiments, a readout signal may be output responsive to a read signal that is sequentially applied to respective rows (or columns) of the main memory 605a, and may be used to calculate an estimated time of arrival of photons incident on the photodetector elements.”).
Regarding Claim 16, which depends from rejected Claim 11, the method of Henderson further comprises performing one or more operations on SRAM values for the plurality of memory cells using the event count stored in the plurality of memory cells, wherein the one or more operations include a read operation, a write operation, a fresh operation, and an update operation ([0083]: “ For example, in a precharge-read-modify-write operation, the current contents of a given histogram bin, which may be indexed by the clock period, are readout and added to the data stored in a corresponding bin of the buffer memory device 305b. The result (e.g., H<n−1:0>) may then be written back to the respective histogram bin of the main memory device 305a.”).
Regarding Claim 17, which depends from rejected Claim 16, Henderson further discloses wherein the one or more operations are performed using row/column address for each of the plurality of memory cells ([0101]: “In some embodiments, a readout signal may be output responsive to a read signal that is sequentially applied to respective rows (or columns) of the main memory 605a, and may be used to calculate an estimated time of arrival of photons incident on the photodetector elements.”).
Regarding Claim 18, which depends from rejected Claim 11, Henderson further discloses determining a direct time to flight using a time to digital converter ([0007]; [0062]: “The detectors 110d include time-of-flight sensors (for example, an array of single-photon detectors, such as SPADs).”) based on the histogram of photon-detection events detected by the associated photon sensor during the exposure window ([0018]: ”The respective bins of the second memory may include histogram data for an imaging distance subrange corresponding to the strobe window.”).
Regarding Claim 19, which depends from rejected Claim 11, Henderson further discloses coupling the SRAM disposed under the plurality of photon sensors to a global synchronous clock ([0058]: “some embodiments may provide processing and/or control circuits that are configured to store photon counts (e.g., SPAD photon counts, as a log 2(k)-bit number) during a strobe window into a temporary memory (e.g., a buffer memory, such as an SRAM buffer, with a number of bins n) at or within the shorter clock cycle (e.g., less than 5 ns).” The SRAM is coupled to a clock.) that re-times all input logic ([0058] The main memory can be accessed at a shorter clock rate, which is identified with re-timing input logic under the broadest reasonable interpretation).
Regarding Claim 20, Henderson discloses one or more computer-readable non-transitory storage media embodying software that is operable when executed to ([0012]):
detect photons during an exposure window after a laser event using a plurality of photon sensors (Figure 1; [0027]);
determine photon-detection events detected by the plurality of photon sensors during the exposure window using a plurality of event registers ([0028]: “a Light Detection and Ranging (LIDAR) detector circuit includes one or more photodetector elements defining a LIDAR detector pixel, a buffer memory device, a main memory device, and at least one processor circuit. The at least one processor circuit is configured to execute first and second memory storage operations to store data indicated by detection signals received from the LIDAR detector pixel in the buffer and main memory devices during first and second portions of a time between pulses of a LIDAR emitter signal; [0030]: “ the at least one processor circuit may include a sampler circuit that is configured to execute the first memory storage operations to sample the data from the detection signals at a predetermined sampling rate and write the data to respective bins of the buffer memory device.” The buffer memory here satisfies the limitation of an event register under the broadest reasonable interpretation.);
determine a histogram of photon-detection events detected by the associated photon sensor during the exposure window using an SRAM ([0021]: “the second memory may be static random access memory (SRAM)”) disposed under the plurality of photon sensors (The memory must necessarily be beneath the detectors in the configuration of Henderson (e.g., Figure 4A1)), wherein the SRAM comprises a plurality of memory cells associated with each photon sensor of the plurality of photon sensors ([0032]: “each of the LIDAR detector pixels may be associated with a respective buffer memory device and a respective main memory device.”), and each memory cell of the plurality of memory cells is configured to store photon-detection events detected during a predetermined time period after the laser event ([0007]: “In addition, thousands of time bins (each corresponding to respective photon arrival times) may typically be used to form a histogram sufficient to cover the typical time range of a LIDAR system”); and
update the plurality of memory cells and the histogram based on the photon-detection events stored by the plurality of event registers using an in-memory incrementor, wherein for each of the photon-detection events stored in the plurality of event registers ([0083]), the in-memory incrementor is configured to read an event count stored in a selected one of the plurality of memory cells, increment the event count, and write the incremented event count back to the selected memory cell ([0083]: “ For example, in a precharge-read-modify-write operation, the current contents of a given histogram bin, which may be indexed by the clock period, are readout and added to the data stored in a corresponding bin of the buffer memory device 305b. The result (e.g., H<n−1:0>) may then be written back to the respective histogram bin of the main memory device 305a.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henderson in view of Pacala (WO 2021072397 A1).
Regarding Claim 3, which depends from rejected Claim 1, Henderson does not teach and Pacala does teach wherein the SRAM disposed under the plurality of photon sensors comprises 128 memory cells associated with each photon sensor of the plurality of photon sensors ([0119]: “In this example, the memory block 1004 may include 128 rows corresponding to 128 time bins in an optical measurement. This number of time bins is provided merely by way of example and is not meant to be limiting.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Pacala to use 128 histogram bins (memory cells) into the device of Henderson. The number of histogram bins within a given time interval effectively determines the time resolution of the instrument, and may be adjusted by a worker skilled in the art to meet the needs of a given measurement. It has been held that if the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 13, which depends from rejected Claim 11, Henderson does not teach and Pacala does teach wherein the SRAM disposed under the plurality of photon sensors comprises 128 memory cells associated with each photon sensor of the plurality of photon sensors ([0119]: “In this example, the memory block 1004 may include 128 rows corresponding to 128 time bins in an optical measurement. This number of time bins is provided merely by way of example and is not meant to be limiting.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Pacala to use 128 histogram bins (memory cells) into the device of Henderson. The number of histogram bins within a given time interval effectively determines the time resolution of the instrument, and may be adjusted by a worker skilled in the art to meet the needs of a given measurement. It has been held that if the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henderson in view of Rae (US 2017/0176250 A1).
Regarding Claim 4, which depends from rejected Claim 1, Henderson teaches wherein a quenching transistor ([0005]: “The avalanche is quenched by a quench circuit”), an event synchronizer ([0068]: “The timing circuit 106 may be phase-locked to the driver circuitry 116 of the emitter array 115.”) are coupled to the plurality of memory cells to generate a plurality signals for laser event time ([0068], a laser event signal is necessarily generated to satisfy this linkage), precharge time, row address time, sense time, and write time ([0102]: “The SRAM precharge-read-modify-write (PRWM) loop is accomplished within each T.sub.sample cycle, thereby limiting the cycle time.” The remaining times are all inherent in the PRWM loop.).
Henderson does not teach and Rae does teach an OR tree coupled to the plurality of memory cells ([0007]-[0012], the SPAD is coupled to on OR tree and to memory.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rae to use an OR tree into the device of Henderson. Rae notes in [0049] that since the SPAD array shares the OR tree, the output network of the array is greatly simplified, and ultimately needs only one output, and that “this eases congestion of SPAD 412 output nets significantly.” This reduces circuit complexity and therefore cost of the devices as well.
Regarding Claim 14, which depends from rejected Claim 11, Henderson teaches coupling a quenching transistor ([0005]: “The avalanche is quenched by a quench circuit”), an event synchronizer ([0068]: “The timing circuit 106 may be phase-locked to the driver circuitry 116 of the emitter array 115.”) to the plurality of memory cells to generate a plurality signals for laser event time, precharge time, row address time, sense time, and write time ([0102]: “The SRAM precharge-read-modify-write (PRWM) loop is accomplished within each T.sub.sample cycle, thereby limiting the cycle time.” The remaining times are all inherent in the PRWM loop.).
Henderson does not teach and Rae does teach an OR tree coupled to the plurality of memory cells ([0007]-[0012], the SPAD is coupled to on OR tree and to memory.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rae to use an OR tree into the device of Henderson. Rae notes in [0049] that since the SPAD array shares the OR tree, the output network of the array is greatly simplified, and ultimately needs only one output, and that “this eases congestion of SPAD 412 output nets significantly.” This reduces circuit complexity and therefore cost of the devices as well.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henderson in view of Rae and in view of Hong (US 2022/0165331 A1).
Regarding Claim 5, which depends from rejected Claim 4, Henderson teaches wherein the SRAM disposed under the plurality of photon sensors further comprises:
a plurality of bitlines, each of the plurality of bitlines being coupled to a corresponding one of the plurality of memory cells ([0021]: “the second memory may be static random access memory (SRAM)”; Bitlines are an inherent part of SRAM technology.);
Henderson does not teach and Rae does not teach and Hong does teach a precharge circuit ([0018]: “The memory device 100 further includes an input/output (IO) block 112 configured to read and write data from and to the memory array 110, and a precharge circuit 102 configured to precharge the bit lines of the memory cells”) configured to determine a precharge time for the plurality of bitlines using the precharge time signal ([0025]: “Further, the control block 120 outputs precharge and word line enable signals based on a common clock pulse…. Thus, to insure proper precharging of the bit lines 203, 204 before asserting the word lines 202, the control block 120 includes a variable delay circuit 122 to delay the word line select signals 300 until after the bit lines 203, 204 are precharged.”) and the row address time signal ([0036]: “The variable word line delay circuit 122 further includes an address input 350 that receives the ADD<7> row address bit, and based on this input delays the clock pulse CKP by either the first or second delay period 332 or 334.”, [0032], [0033]);
a bit line settling circuit configured to determine a bit line settling time for the plurality of bitlines using the row address time signal and the sense time signal ([0027]: “ a variable delay circuit 122 varies the delay time period the word line enable signals 302 output to the word line driver 104 by the control block 120 based on the address of the selected word lines 202. In other words, to insure the bit line precharge circuit 102 is able to fully precharge the bit lines 203, 204 before asserting the selected word lines 202, word lines 202 with a low address such as the word line WL<0>, which is closer to the control block 120, are delayed for a first delay time.” Here the wordline times are taken to be analogous to the row address times.) ;
a sense amplitude ([0019]: “In a read operation, for example, the memory cell bit lines are precharged to a predefined threshold voltage by the precharge circuit 102. When the word line is enabled by the word line driver 104, a sense amplifier of the IO block 112 connected to the bit lines senses and outputs stored information.”) and incrementor delay circuit configured to determine a sense amplitude and incrementor delay time for the plurality of bitlines using the sense time signal and the write time signal ([0025]: “For best operation of the memory array 100, the bit lines 203, 204 should be fully precharged before the word lines 202 are asserted for read or write operations.”);
and a write delay circuit configured to determine a write delay time for the plurality of bitlines using the row address time signal and the write time signal ([0025]: “For best operation of the memory array 100, the bit lines 203, 204 should be fully precharged before the word lines 202 are asserted for read or write operations. For instance, if the word line 202 is asserted before the bit lines 203, 204 are adequately precharged to the desired precharge voltage level, the read and write operations could result in data errors. Further, the control block 120 outputs precharge and word line enable signals based on a common clock pulse. Thus, to insure proper precharging of the bit lines 203, 204 before asserting the word lines 202, the control block 120 includes a variable delay circuit 122 to delay the word line select signals 300 until after the bit lines 203, 204 are precharged.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hong to calculate precharge and settling times to effect better read and write characteristics into the device of Henderson in view of Rae. Hong notes in [0025] that “for best operation of the memory array 100, the bit lines 203, 204 should be fully precharged before the word lines 202 are asserted for read or write operations.” The times calculated and utilized in Hong therefore result in better and more reliable operation of the memory.
Regarding Claim 15, which depends from rejected Claim 14, Henderson teaches wherein each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells ([0021]: “the second memory may be static random access memory (SRAM)”; Bitlines are an inherent part of SRAM technology.)
determining a precharge time for a plurality of bitlines using the precharge time signal ([0025]: “Further, the control block 120 outputs precharge and word line enable signals based on a common clock pulse…. Thus, to insure proper precharging of the bit lines 203, 204 before asserting the word lines 202, the control block 120 includes a variable delay circuit 122 to delay the word line select signals 300 until after the bit lines 203, 204 are precharged.”) and the row address time signal ([0036]: “The variable word line delay circuit 122 further includes an address input 350 that receives the ADD<7> row address bit, and based on this input delays the clock pulse CKP by either the first or second delay period 332 or 334.”, [0032], [0033]);
determining a bit line settling time for the plurality of bitlines using the row address time signal and the sense time signal ([0027]: “ a variable delay circuit 122 varies the delay time period the word line enable signals 302 output to the word line driver 104 by the control block 120 based on the address of the selected word lines 202. In other words, to insure the bit line precharge circuit 102 is able to fully precharge the bit lines 203, 204 before asserting the selected word lines 202, word lines 202 with a low address such as the word line WL<0>, which is closer to the control block 120, are delayed for a first delay time.” Here the wordline times are taken to be analogous to the row address times.) ;
determining a sense amplitude ([0019]: “In a read operation, for example, the memory cell bit lines are precharged to a predefined threshold voltage by the precharge circuit 102. When the word line is enabled by the word line driver 104, a sense amplifier of the IO block 112 connected to the bit lines senses and outputs stored information.”) and incrementor delay circuit configured to determine a sense amplitude and incrementor delay time for the plurality of bitlines using the sense time signal and the write time signal ([0025]: “For best operation of the memory array 100, the bit lines 203, 204 should be fully precharged before the word lines 202 are asserted for read or write operations.”); and
determining a write delay circuit configured to determine a write delay time for the plurality of bitlines using the row address time signal and the write time signal ([0025]: “For best operation of the memory array 100, the bit lines 203, 204 should be fully precharged before the word lines 202 are asserted for read or write operations. For instance, if the word line 202 is asserted before the bit lines 203, 204 are adequately precharged to the desired precharge voltage level, the read and write operations could result in data errors. Further, the control block 120 outputs precharge and word line enable signals based on a common clock pulse. Thus, to insure proper precharging of the bit lines 203, 204 before asserting the word lines 202, the control block 120 includes a variable delay circuit 122 to delay the word line select signals 300 until after the bit lines 203, 204 are precharged.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hong to calculate precharge and settling times to effect better read and write characteristics into the device of Henderson in view of Rae. Hong notes in [0025] that “for best operation of the memory array 100, the bit lines 203, 204 should be fully precharged before the word lines 202 are asserted for read or write operations.” The times calculated and utilized in Hong therefore result in better and more reliable operation of the memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN WADE CLOUSER whose telephone number is (571)272-0378. The examiner can normally be reached M-F 7:30 - 5:00.
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/B.W.C./ Examiner, Art Unit 3645
/ISAM A ALSOMIRI/ Supervisory Patent Examiner, Art Unit 3645
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