Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Response to Arguments
Applicant's arguments filed 24 February 2026 have been fully considered but they are not persuasive.
Applicant’s amendment filed 24 February 2026 is not sufficient to overcome the previous rejections under 35 U.S.C. 101 and 112 discussed below.
Regarding the rejection under 35 U.S.C. 112, the selecting step in the claim as amended merely requires selecting fewer than all pieces of circuit information classified into each group. However there seems to be no criteria for “fewer”. It is not clear which piece(s) are selected.
Regarding the generating step, applicant argues at page 14 of the response: “The present Specification, for instance, explicitly discusses "training data in which circuit information is associated with a simulation result of electromagnetic wave analysis for the circuit information" (paragraph [0004]) and further elaborates on generating "training data in which the current distribution and the EMI intensity are associated" (paragraph [0081]). It also specifies that training data involves a "current distribution image" and "EMI intensity" (paragraph [0084]). Given that the preceding steps explicitly define the circuit information (including physical parameters and a netlist), and the process of selecting a relevant subset, the generation of corresponding training data for a neural network model would be understood by a person of ordinary skill in the art in light of the specification. Therefore, the revised "generating" step, in conjunction with the clarified "selecting" step, overcomes the alleged indefiniteness by providing a clear and technically grounded description of the generation process and the intended use of the generated data”.
In response the examiner is not persuaded. The claimed generating as amended still seems to depend on which pieces of circuit information are obtained from the selecting step. However no criteria is specified other than “fewer” than all pieces, which is not supported by the specification, thus does not provide any clarification. Furthermore the “to be used” is merely intentional, does not require any actual training of a model for circuit analysis. Note although claims are interpreted in light of the specification, the specification cannot be read into the claims. as written, the metes and bounds of the claimed subject matter cannot be ascertained.
For all the reasons discussed above, the rejection of all pending claims under 35 U.S.C. 112 is maintained.
Regarding the rejection under 35 U.S.C. 101, applicant argues at page 17 of the response filed 24 February 2026: “Given the volume and complexity of circuit information and the precise, iterative nature of the calculations and classifications required, in light of the Specification, a person skilled in the art would understand that these are not mere observations, evaluations, judgments, or opinions but specified technical procedures requiring computational processing. Therefore, the claimed invention, when viewed as a whole, especially after amendment, does not recite judicial exceptions that can practically be performed in the human mind, and thus the claims are not directed to a mental process. Thus, we believe that the amended claims do not recite any judicial exception (Step 2A - Prong 1: No)”.
In response the examiner is not persuaded. As written the recited “calculating, classifying, selecting, generating under their broadest reasonable interpretation cover performance of the limitations by a human user with the aid of pen and paper, thus considered mental processes. Furthermore, an abstract idea even when processed by a computer is not less abstract.
For all the reasons discussed above, the rejection of all claims under 35 U.S.C. 101 is maintained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
An analysis of subject matter patentability is presented below for method claim 8
Step 1: claim 8 recites a method thus is one of the statutory categories of invention.
Step 2A Prong 1: Claim 8 recites: classifying…, selecting… These limitations are processes that, under their broadest reasonable interpretation, covers performance of the limitation by a human user. Note nothing in the claim element precludes the steps from practically being performed by a human user with the aid of pen and paper. If a claim limitation, under its broadest reasonable interpretation, cover performance of the limitation in the mind, then it falls within the "Mental Processes' grouping of abstract idea (concept performed in the human mind including an observation, evaluation, judgment and opinion). The mere nominal recitation of "by a computer" does not take the claim limitation out of the mental processes grouping.
Step 2A Prong 2: the judicial exception is not integrated into a practical application. The claim recites the additional element "generating...", The generating step recited at a high level of generality amounts to mere insignificant extra solution activity because they do not impose any meaningful limits on practicing the abstract idea (see MPEP 2106.05(g)).
Step 2B: the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The limitation of "calculating for each piece of circuit information of a first plurality of piece of circuit information, ,,,the calculating of the characteristic impedance being performed based on the netlist and the physical parameters of the respective circuit in the each piece of circuit information" is mere well understood, routine and conventional activities for any generic computer to calculate circuit information (see MPEP 2106.05(d) (II) (IV). Accordingly these additional elements do not integrate the abstract idea into a practical application.
Claims 1, 15 merely recite the limitations of claim 8 in form of computer program product and system respectively, thus are not patent eligible for the same reasons discussed in claim 8 above.
Claims 2, 9, 16 merely further describe the generating includes generating training data, considered insignificant extra solution activity (see MPEP 2106.05(g)).
Claims 3, 10, 17 merely add training a neural network model, considered mere insignificant extra solution activity (see MPEP 2106.05(g)).
Claims 4, 11, 18 merely further describe the training data generation, considered mere insignificant extra solution activity (see MPEP 2106.05(g)).
Claims 5, 12, 19 merely further describe the classifying and calculating, considered mere insignificant extra solution activity (see MPEP 2106.05(g)).
Claims 6, 13, 20 merely further describe the classifying includes calculating a distance, considered mere insignificant extra solution activity (see MPEP 2106.05(g)).
Claims 7, 14 merely further exclude pieces of circuit information outside of a range, considered mere insignificant extra solution activity (see MPEP 2106.05(g)).
As discussed above although the dependent claims seem more detailed than their parent claims, none amount to significantly more than the abstract idea. No claim is eligible.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “selecting one or more of pieces of circuit information fewer than all pieces of circuit information classified into the each group”.
The specification as originally filed does not support the “fewer” now recited in all independent claims 1, 8, 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “selecting one or more of pieces of circuit information fewer than all pieces of circuit information classified into the each group”. It is not clear how a piece of circuit information is selected from each group.
Furthermore the term “fewer” is a relative term which renders the claim indefinite. The term “fewer” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The claimed “generating” still seems to depend on the pieces of circuit information obtained from the selecting step. However there seems to be no criteria for the selection. Note “fewer” is a relative term that renders the claim indefinite, thus does not provide any further clarification.
Furthermore the language of “to be used” seems merely intentional, does not require any actual training of a model for circuit analysis.
Art rejection is not being applied because the limitations cannot be ascertained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Salahuddin et al (US 12099788 B2) teach a method of predicting performance in electronic design based on machine learning using at least one processor, the method including: providing a first machine learning model configured to predict performance data for an electronic system based on a set of input design parameters for the electronic system; providing a second machine learning model configured to generate a new set of parameter values for the set of input design parameters for the electronic system based on a desired performance data provided for the electronic system; generating, using the second machine learning model, the new set of parameter values for the set of input design parameters for the electronic system based on the desired performance data provided for the electronic system; evaluating the set of input design parameters having the new set of parameter values for the electronic system to obtain an evaluated performance data associated with the set of input design parameters having the new set of parameter values; generating a new set of training data based on the set of input design parameters having the new set of parameter values and the evaluated performance data associated with the set of input design parameters having the new set of parameter values; and training the first machine learning model based on at least the new set of training data. There is also provided a corresponding system for predicting performance in electronic design based on machine learning.
Sivaswamy et al (US 11790139 B1) teach a design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).
RAO et al (US 20180197110 A1) is directed to machine learning (ML) based network-on-chip (NoC) construction. Methods, systems, and computer readable mediums of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is actually the most optimal and efficient one or not during construction of a NoC. ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a machine learning algorithm/predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, a quality metrics) obtained by implementing a mapping strategy on the NoC, and one or more performance function (user requirement) to generate an output showing whether the selected strategy for the construction of the NoC yields a good result or a bad result based on learning/training.
Dutta et al (US 20220027536 A1) teach a method of generating training data for a machine learning model for predicting performance in electronic design using at least one processor, the method including: generating a first set of training data based on a first set of input design parameters and an electronic design automation tool; generating a first covariance information associated with the first set of input design parameters based on the first set of training data; determining a second set of input design parameters based on the first covariance information; and generating a second set of training data based on the second set of input design parameters and the electronic design automation tool. There is also provided a corresponding system for generating training data for a machine learning model for predicting performance in electronic design.
Pehlivan, Huseyin, Celal Atalar, and Sultan Zavrak. "Development and implementation of an analysis tool for direct current electrical circuits." Computer Applications in Engineering Education 29.5 (2021): 1071-1086.
Abstract- Electrical circuits constitute the core of many courses at the undergraduate level in electrical and electronics engineering. For most undergraduate students, learning and analyzing such circuits are a difficult process. A significant drawback of Simulation Program with Integrated Circuit Emphasis (SPICE)-based simulation tools in terms of e-learning is that they only generate circuit simulation outputs, such as the current and voltage of electrical elements contained in a particular circuit. The users are not provided with the detailed information about the steps that are followed to obtain the related outputs. This study describes the development of a new software tool, called ECDAT (a shorthand for the Electrical Circuit Description and Analysis Tool), which can serve as a practical component of electrical circuits courses. The developed tool currently analyzes simple direct electric circuits in a similar way as the existing circuit analysis and simulation ones, and it produces an output document that includes the certain equations and intermediate calculations, using the well-known circuit laws differently from the previous works. Another contribution of the study is that, unlike the modified nodal analysis method used in SPICE-based circuit analysis programs, it employs a graph analysis method for circuit analysis.
Podlejski, Anne-Sophie, et al. "Layout modelling to predict compliance with EMC standards of power electronic converters." 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC). IEEE, 2015.
Abstract- In power electronics, the layout of a converter is known to have a significant impact on its conducted emissions. This paper focuses on layout modelling in order to predict converter compliance with EMC standards before prototype manufacturing. Inductive effects and capacitive parasitic effects should be considered and models in the form of equivalent circuits are required by time domain simulators. In recent works, a software was used to obtain an equivalent circuit of the inductive effects and analytic calculations were performed to add equivalent capacitors. In this paper a single software is used to generate a model which includes both capacitive and inductive effects. The existing method and the proposed one show very similar results and fit well with experimental results. The proposed method requires less efforts and is more scalable since it can be applied to complex geometries.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/UYEN T LE/Primary Examiner, Art Unit 2156 20 March 2026